JPH02290367A - Processor for adding stereoscopic shadow - Google Patents

Abstract

PURPOSE:To facilitate picture reading by discriminating the presence of a picture based on plural picture data with a picture area discriminating means and applying the processing as to whether or not shadow is added thereby avoiding the addition of shadow to a character with thin line thickness, a drawing picture or noise picture or the like. CONSTITUTION:A picture data signal IM1 from a picture input device is inputted to an FF 31 and a picture data signal IM2 is outputted from a terminal Q synchronously with a picture element synchronizing signal inputted to a CLK terminal. The signal IM2 is inputted to an input terminal P of a comparator 32 as a picture area discrimination means and an input terminal B of a selector 33 as a picture data selection means. The comparator 32 compares the signal IM 2 with a threshold level signal TH inputted to the terminal Q and a picture area signal 1A is outputted from an inverse of P>Q terminal. Moreover, a selector 35 corresponds to a shadow length data selection means 15 and when an input level of a selector terminal the inverse of A/B represents the presence of logical level, a shadow length selection value signal SS inputted to a terminal A is selected and when no logic level exists, a shadow length residual signal SR 1 is selected and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a three-dimensional shadow addition processing device in an image processing device.

In a conventional image processing device, when a character image is input,
As a type of image processing, it is sometimes desired to output a character image in a predetermined direction, for example, in the lower right 45° direction, to give it a three-dimensional effect by adding a shadow.

Here, as a processing device that adds such a three-dimensional shadow,
Although there is nothing particularly known in the past, a configuration as shown in FIG. 10 can be easily considered.

First, an image area determination block 1 is provided which processes input image data to determine the presence or absence of an image, and outputs an H level when an image is present and an L level when no image is present. Four line buffers 2 each delaying the output (image determination signal) from the image area determination block l by l scanning lines.
a to 2d are provided. Furthermore, D flip-flops 3a to 3d are provided that delay the image determination signals output by these line buffers 2a to 2d by one pixel.

Here, one D flip-flop 3a is provided for the line buffer 2a, two D flip-flops 3b, 3b, are provided for the line buffer 2b, and three D flip-flops are provided for the line buffer 2C. D flip-flops 3c, ~3c, are provided, and four D flip-flops 3d, ~3d are provided for the line buffer 2d.
4 is provided.

Therefore, the output from the D flip-flop 3a is data delayed by one scanning line and one pixel, and the output from the D flip-flop 3b is data delayed by two scanning lines and two pixels. The output from 3c, is 3
The data is delayed by 3 scanning lines/3 pixels, and the output from the D flip-flop 3d4 is data delayed by 4 scanning lines/4 pixels. These D flip-flops 3a,
The outputs from 3b, 3c, 3d are input to NOR gate 4. The output of the NOR gate 4 is input to the NOR gate 5 together with the output from the image area determination block l. And image data and shadow data generation means (not shown)
A selector 6 is provided which inputs the shadow data from the NOR gate 5 and selects and outputs either the image data or the shadow data according to the output of the NOR gate 5.

In the example shown in FIG. 10, the length of the generated shadow is equivalent to 4 pixels, and an image exists in any of the 4 pixels in the direction of 45 degrees to the upper left of the current pixel (that is, the length of the generated shadow is equivalent to 4 pixels). output is L level) and there is no image at the current pixel (that is, the output of the image area determination block l is L level), the pixel is determined to be a shadow area pixel, and the selector 6 selects and outputs the shadow data. It turns out.

Problem to be Solved by the Invention However, when configuring a stereoscopic shadow adding processing device using the method shown in FIG. 10, the length of the generated shadow is 4 in the example shown in FIG.
It is not easy to increase the length of the shadow because it is necessary to increase or decrease the number of delay means such as line buffers and D flip-flops according to the number of pixels (equivalent to pixels). For example, if the reading pixel density is 16 pixels/pixel and the shadow length is 16 m=256 pixels, a line buffer of at least 256 bits is required. Therefore, in the case of the method shown in FIG. 10, it is difficult to inexpensively realize a device that can increase the length of the generated shadow. Furthermore, as the number of parts increases, reliability also decreases.

Means for Solving the Problem Basically, there are a shadow area specifying means for specifying a shadow area based on image data input from an image data generating means, a shadow data generating means for generating shadow data, and a shadow area specifying means for generating shadow data. and an image data selection means for selectively outputting either one of the shadow data and the shadow data to the image data receiving means based on the identification result of the shadow area identification means, and the shadow area identification means is configured to determine the length of the shadow to be generated. shadow length data generation means for generating a setting value of , image area determination means for determining the presence or absence of an image based on the image data, and shadow length data generation means for determining the presence or absence of an image based on the image data; long data delay means;
a shadow length data counting means for counting data representing the length of the residual shadow; and data representing the length of the residual shadow or the shadow length delayed by the shadow length data delay means and counted by the shadow length data counting means. Shadow length data updating means for selecting one of the shadow length data generated by the data generating means based on the determination result of the image area determining means and updating data representing the length of the remaining shadow with respect to the set value; and a shadow area determination means for determining a shadow area based on image data and data representing the length of the residual shadow whose update has been delayed.

Further, the image area determining means is configured to determine the presence or absence of an image based on a plurality of image data inputted from the image data generating means, and the image area determining means is configured to determine the presence or absence of an image based on a plurality of image data inputted from the image data generation means. It has a data number selection means for selecting the number of data, and in accordance with the number of image data selected by the data number selection means, the presence or absence of an image is determined based on the image data input from the image data generation means. Configured.

When adding a shadow to the image input from the effect image data generation means, the shadow area specifying means specifies the shadow area to which the shadow should be added, and the shadow data indicates what density of the shadow to add. is generated by the shadow data generation means, and the image data selection means is controlled according to the result of specifying the shadow region, and if the shadow region is a shadow region, the shadow data is output as image data to the image data reception means, and if the shadow region is not a shadow region, the input The image data may be directly outputted to the image data receiving means.

By the way, when adding a shadow to an image, the shadow is generally diagonally downward with respect to the image, but this can be expressed by dividing it into the main scanning direction and the sub-scanning direction. That is, when an image exists, if the length of the shadow is taken in the sub-scanning direction and this is delayed by a number of pixels in the main-scanning direction for each sub-scanning, a pixel area in the diagonal direction will be obtained. Based on such a premise, first, the data representing the length of the shadow to be generated is an arbitrary set value generated by the shadow length data generating means. Then, based on the input image data, the image area determining means determines the presence or absence of an image. Data representing the length of the remaining shadow is updated by the shadow length data updating means in accordance with the image resulting from this determination. Here, if it is the first time, the data representing the length of the remaining shadow matches the set value. By delaying this in the main and sub-scanning directions by the shadow length data delay means, it is moved to the shadow area.

Such processing is similarly performed for the next sub-scanning line.

At this time, for pixels where an image exists following the previous sub-scanning line, the setting value is updated as data representing the length of the remaining shadow, but in the previous sub-scanning line, even if an image exists, the setting value is updated. For pixels for which no image exists in the scanning line, a value obtained by subtracting the length of one pixel from the initial setting value is updated as data representing the length of the remaining shadow. Then, delay processing is also performed on this remaining shadow length data. In parallel with such processing, data representing the length of the remaining shadow is counted by the shadow length data counting means to determine whether or not there is no data representing the length of the remaining shadow. In this way, when updating processing that involves delay processing and counting processing of the data representing the length of the remaining shadow is performed based on the image data, the result becomes a shadow region candidate, so the final shadow region determination is performed. By excluding the actual image portion based on the image data, the shadow area can be identified.

In other words, by focusing on the data representing the length of the remaining shadow relative to the set value of the length of the shadow to be generated, and updating, delaying, and counting the data according to the image data, the shadow to be generated can be calculated as image data. Regardless of the length of the pixel, it is only necessary to know the image data of the current pixel of interest. Therefore, there is no need to delay and hold image data for a plurality of sub-scanning lines over the length of a generated shadow as in the conventional method, and a long shadow can be added using a small-capacity memory.

Furthermore, if the image area determining means determines the presence or absence of an image based on a plurality of image data inputted from the image data generating means, it is possible to eliminate shadows from characters, figures, etc. with thin line widths, and noise pixels. You can avoid adding . In particular, it is provided with a data number selection means for selecting the number of image data for determining the presence or absence of an image, and in accordance with the number of image data selected by the data number selection means, the image data generated by the image data generation means is By determining the presence or absence of an image, the user can select the line width of the image to which a three-dimensional shadow is added, and the legibility of characters with thin line widths can be prevented from being impaired.

Embodiment A first embodiment of the present invention will be described with reference to FIGS. 1 to 5.

FIG. 1 shows the basic block diagram configuration of a stereoscopic shadow addition processing device according to this embodiment. First, image area determining means 12 and image data selecting means 13 are provided, each of which receives an image data signal 11 output from a rask image signal input means and image data generating means (not shown). The image area determination means 12 processes the image data signal, determines the presence or absence of an image for each pixel, and outputs the determination result as an image area signal l4. Shadow length data selection means 15 and shadow region determination means 16 to which this image region signal 14 is input are provided.

The shadow length data selection means 15 constitutes a shadow length data updating means 17 for updating data representing the length of the remaining shadow, and is configured to update data representing the length of the shadow updated in accordance with the image area signal 14. The residual value of is outputted as a shadow length residual value signal l8. Specifically, the shadow length data selection means 15
selects the shadow length setting value signal 20 output by the shadow length data generating means 19 when the image area signal l4 means that the image r exists, and when it means that the image r is "absent", selects the shadow length setting value signal 20. 21 is selected, and the shadow length residual value signal 18 is updated. Here, the shadow length setting value signal 20 outputted by the shadow length data generating means 19 means "the setting value of the length of the shadow to be generated."

The shadow length residual value signal 18 output from the shadow length data selection means 15 is input to the shadow length data delay means 23. This shadow length data delaying means 23 delays the shadow length residual value signal l8 outputted by the shadow length data selection means l5 by a time corresponding to l scanning lines and several pixels, and outputs the delayed shadow length residual value signal 24. This is what is output. The reason why the delay time has a width of several pixels is because the required delay time changes depending on the direction of the generated shadow. Delayed shadow length residual value signal 2
4 is input to the shadow area determining means 16 together with the shadow length data counting means 2l.

The shadow length data counting means 2l calculates the same data (i.e., indicates that the length of the residual shadow is rOJ) when the length of the residual shadow indicated by the delayed shadow length residual value signal 24 is rQJ. data) is output as a shadow length residual value signal 22, and when the data representing the length of the residual shadow implied by the delayed shadow length residual value signal 24 is not "0", this shadow length residual value signal 24 means A predetermined length is subtracted from the length of the remaining shadow, and a value indicating the subtracted length of the remaining shadow is output as a shadow length residual value signal 22.

The shadow area determination means l6 processes the image area signal l4 and the delayed shadow length residual value signal 24, determines whether or not each pixel is a shadow area, and outputs the result as a shadow area signal 25. be. More specifically, the image area signal I4 corresponds to the image "
The pixel of interest is determined to be a shadow area if the data representing the length of the residual shadow implied by the shadow length residual value signal 24 is not "0". This shadow area signal 25 is input to the image data selection means 13.

The image data selection means 13 selects the image data signal 11 or the shadow data signal 27 (image data to be generated for the portion determined to be a shadow area) output from the shadow data generation means 26 in accordance with the shadow area signal 25. Either one is selected and outputted as an image data signal 28 to a rask image signal output means=image data reception means (not shown) or the like. That is, the image data selection means 13 selects the shadow data signal 27 when the shadow area signal 25 means "shadow area", and selects the shadow data signal 27.
If it means "non-shadow area", the image data signal l1 is selected and output.

In this way, the image area determining means 12, the shadow area determining means 16, the shadow length data updating means 17, the shadow length data generating means 19, the shadow length data counting means 2l, and the shadow length data delaying means 2
3 constitutes a shadow area specifying means 29.

According to such a configuration, there is no need to delay the image area determination results for multiple scanning lines as shown in FIG. It is only necessary to update the data representing the length of the shadow, delay and count processing, and it is possible to add a long shadow using a small memory capacity.

In FIG. 1, the delayed shadow length residual value signal 24 output by the shadow length data delaying means 23 is input to the shadow length data counting means 2l, and the shadow length residual value output from the shadow length data counting means 2l is Although the signal 22 is inputted to the shadow length data selection means l5, the shadow length data signal outputted from the shadow length data selection means l5 is inputted to the shadow length data counting means,
The shadow length data signal output from the shadow length data counting means is input to the shadow length data delay means, and the shadow length data signal output from the shadow length data delay means is input to the shadow length data selection means. Good too. That is, the flow direction is opposite to that shown in FIG.

Next, a specific example of this embodiment will be explained with reference to FIGS. 2 to 5.

First, the operation control of this embodiment includes a frame synchronization signal FSYNC synchronized with the frame of the input/output image data signal;
A scanning line synchronization signal LSYNC synchronized with the scanning line and a pixel synchronization signal CLOCK synchronized with the pixels are used.

An 8-bit image data signal IMI output from an image input device (not shown) is input to an input terminal D of the flip-flop 3l. Then, an 8-bit image data signal IM2 is output from the Q terminal of this flip-flop 3l in synchronization with the pixel synchronization signal CLOCK input to the CLK terminal.

This image data signal IM2 is input to the input terminal P of the converter 32 (corresponding to the image area determining means l2) and the selector 33.
(corresponding to the image data selection means l3) is inputted to the input terminal B.

The converter 32 receives an image data signal IM2 input to a P terminal and an 8-bit threshold signal TH input to a Q terminal.
and compare the result with the image area signal I from the P>Q terminal.
Output as A. Here, the value of the threshold signal TH input to the Q terminal is a threshold for determining the presence or absence of an image in each pixel of the image data signal IM2, and is set by the threshold setting switch 34 on the operation unit (not shown). The value can be selected according to the darkness of the original. Therefore, the image area signal IA output from the comparator 32 represents the determination result of the presence or absence of an image. In this embodiment, if the image area signal IA is at L level, it means that there is an image; if it is at H level, it means that there is no image.

Further, this image area signal IA is input to the select terminals A/B of the selector 35 and the two-man NAND gate 36.

The selector 35 corresponds to the shadow length data selection means 15, and when the input to the select terminal A/B is at L level, that is, when the image is present, an 8-bit shadow length setting value signal S is input to the A terminal.
S is selected, and when the input to the select terminal A/B is H level, that is, the image is "no", the 8-bit shadow length residual value signal SRI input to the B terminal is selected, and the 8-bit shadow length signal is input from the Y terminal. The shadow length residual value signal SR2 is output as the shadow length residual value signal SR2. Here, the value of the shadow length setting value signal SS input to A@ of the selector 35 represents data representing the length of the shadow to be generated, and the shadow length setting switch 37 (shadow length data generation Means 19
(equivalent to), the length can be set to any length from 0 (no shadows at all) to 255 dots. Further, the shadow length residual value signal SR2 is input to the input terminal Di of the line buffer 38.
has been entered.

This line buffer 38 operates in synchronization with the scanning line synchronization signal LSYNC input to the RST terminal and the pixel synchronization signal CLOCK input to the CLK terminal, and transfers the shadow length residual value signal SR2 input to the Di terminal for one scanning line. minutes late, D
It is output from the O terminal as an 8-bit shadow length residual value signal SR3. As such a line buffer 38, a high-speed line memory such as μPD42505C (manufactured by NEC Corporation) may be used, for example. This line buffer 38
The shadow length residual value signal SR3 is input to the D terminal of the flip-flop 39.

This flip-flop 39, together with the line buffer 38, corresponds to the shadow length data delay means 23, and operates in synchronization with the pixel synchronization signal CLOCK input to the CLK terminal, and outputs the shadow length residual input to the D terminal. value signal SR
3 is further delayed by 1 pixel and output from the Q terminal as an 8-bit shadow length residual value signal SR4. This shadow length residual value signal SR4 is connected to the A terminal of the adder 40 and the 8-man OR gate 4l.
is input to each input terminal.

The adder 40 receives the shadow length residual value signal SR input to the A terminal.
8-bit fixed value signal DEC input to 4 and B terminals
(here, 255) and outputs the result from the Σ terminal as an 8-bit shadow length residual value signal SR5.6 At the same time, this adder 40 outputs a carry signal CY from the CO terminal.

Each bit of the shadow length residual value signal SR5 outputted from the adder 40 is input to each gate input terminal of a group of eight two-way AND gates 42. On the other hand, each A of the AND gate group 42
The carry signal CY output from the adder 40 is input to the other input terminal of the ND gate. Also, each AN
The output signal of the D gate becomes the shadow length residual value signal SRI for the B terminal of the selector 35.

Therefore, the adder 40 outputs the delayed shadow length residual value signal SR4.
Equivalent processing is performed by subtracting 1 from the value of , and the result is output from the AND gate group 42.
The adder 40 and the AND gate group 42 correspond to the shadow length data counting means 21. Also, the value of the shadow length residual value signal SR4 is O
(In other words, if the data representing the remaining length of the shadow is O),
Since the carry signal CY output from the adder 40 becomes L level, the value of the shadow length residual value signal SRI output from the AND gate group 42 also becomes O (that is, the data representing the residual length of the shadow is O). As it is, no subtraction processing is actually performed.

On the other hand, the delayed shadow length residual value signal SR4 by 8 bits
The OR processing result of the OR gate 41 to which each bit is input is output as a shadow candidate signal SC. This shadow candidate signal SC is at H level unless the value of the shadow length residual value signal SR4 is O (that is, the data representing the residual length of the shadow is O). This shadow candidate signal SC is input to the NAND gate 36, which together with the NAND gate 36 corresponds to the shadow area determining means l6.

An image area signal IA is input to this NAND gate 36, and this image area signal IA is at H level, and
When the shadow candidate signal SCfJ<H level, it becomes L level. In other words, this is a case where the image is a candidate for a shadow area with no J. In other words, the output signal of the NAND gate 36 means whether or not it is a shadow area of the pixel of interest currently being processed; If it is a level, it represents a shadow area.Therefore, in the following, N
The output signal of the AND gate 36 will be referred to as a shadow area signal SA. This shadow area signal SA is input to select terminals A/B of the selector 33.

The input of the select terminal A/B of the selector 33 is L level,
That is, if it is a shadow area, the 8-bit shadow data signal SD input to the A terminal is selected, and if the input to the select terminal A/B is at H level, that is, if it is not a shadow area, the 8-bit shadow data signal SD input to the B terminal is selected. The image data signal IM2 is selected and output from the Y terminal as an 8-bit image data signal IM3 to the image output device (
(not shown). Here, the value of the shadow data signal SD input to the A terminal represents the density of the shadow to be generated, and the value of the shadow data signal SD inputted to the A terminal represents the density of the shadow to be generated, and the value of the shadow data signal SD is set by the shadow density setting switch 43 (corresponding to the shadow data generation means 26) of the operation section. It can be set to any density from (white) to 255 (black).

In addition, the frame synchronization signal FSYNG and the scanning line synchronization signal L
The clear signal CLR output by the two-man AND gate 44 which receives SYNC as an input is output from the flip-flop 31.3.
It is input to the CLR terminal of No. 9, and is used to clear the flip-flops 31 and 39 at the beginning of the line of the image signal and the line buffer 38 at the beginning of the frame of the image signal.

FIG. 3 shows the timing relationship among the frame synchronization signal FSYNC, the scanning line synchronization signal LSYNC, and the image data signal IMI. As shown in this figure, in the operation of this embodiment, before a valid image data signal IMl is input,
First, the frame synchronization signal FSYNC becomes L level.

In this case, according to the configuration in FIG. 2, the clear signal CLR is also low.
level, so flip-flops 31 and 39 are cleared. As a result, the image data signal IM2 becomes 0, so the image area signal IA becomes H level regardless of the setting of the threshold setting switch 34. Therefore, selector 35
selects the shadow length residual value signal SRI and outputs it to the line buffer 38. On the other hand, since the shadow length residual value signal SR4 also becomes O due to the clear signal CLR, the carry signal CY becomes L level, and the shadow length residual value signal SRI output from the AND gate group 42 becomes O. Therefore, 0 is written into the line buffer 38 while the frame synchronization signal FSYNC is at L level. On the other hand, the frame synchronization signal FSYNC of this embodiment is
As shown in the figure, the frame synchronization signal FSYNC changes in synchronization with the falling edge of the scan line synchronization signal LSYNG, and the L level period of the frame synchronization signal FSYNC is longer than l period of the scan line synchronization signal LSYNC, and the line buffer 38 is filled with O and cleared.

Furthermore, when the frame synchronization signal FSYNC changes from the L level to the H level, as shown in FIG. Line image data signals are input one after another.

Therefore, with the stereoscopic shadow addition processing device shown in Fig. 2,
Taking the case of processing an input image as shown in FIG. 4(a) as an example, the processing operation will be explained with reference to the timing chart of FIG. 5. Here, to simplify the explanation,
The value of each pixel in the image shown in Figure 4(a) is
Assume that the black part (image part) is 255.

Furthermore, the frame indicates the area of each pixel when the image is sampled in the main and sub-scanning directions. The main scanning direction and the sub-scanning direction are as shown in the drawing.

FIG. 5 shows the scanning line synchronization signal LSYN when the image shown in FIG. 4(a) is input to the device having the configuration shown in FIG.
C, pixel synchronization signal CLOCK, image data signal IMI,
It shows the relationship between IM2 and shadow length residual value signals SR4 and SR2.

First, in this embodiment, as shown in FIG. 5, the scanning line synchronizing signal LSYNC changes in synchronization with the fall of the pixel synchronizing signal CLOCK, and during the L level period of the scanning line synchronizing signal LSYNC, the pixel synchronizing signal LSYNC changes. It is more than one cycle of CLOCK. Referring to FIG. 5, frame synchronization signal FSY
NC goes high in synchronization with the falling of the scanning line synchronization signal LSYNC.
When the level changes (FIG. 3), the image data of the first line of the input image appears in the image data signal IMI.

Here, the image data signal IMI includes a scanning line synchronization signal LS.
The image data DI of the first pixel of each line appears in synchronization with YNC changing to L level, but the image data D2 of the second pixel appears due to the scanning line synchronization signal LSY.
This timing is synchronized with the first rise of the pixel synchronization signal CLOCK after the rise of NC. Further, the image data of the third and subsequent pixels appear in sequence in synchronization with the rise of the pixel synchronization signal CLOCK.

Here, in the case of the input image of FIG. 4(a), since there is no image on the I-th line, the image data signal IMI of the first line
The values of are all O. The value of the image data signal IM2 takes a value obtained by delaying the image data signal IMI by one clock of the pixel synchronization signal CLOCK. Furthermore, while the scanning line synchronization signal LSYNC is at the L level, the clear signal CLR is also at the L level as described above, so the image data signal IM2
The value of is 0 during this time. On the other hand, the l-th shadow length residual value signal S output from the flip-flop 39
The values of R4 are all 0 because the line buffer 38 is cleared by the frame synchronization signal FSYNC. Furthermore, since the values of the l-th line image data signal IM2 are all 0, the image area signal IA from the converter 32 remains at H level, and the l-th line shadow length residual value signal output from the selector 35 SR2 is O. In the case of Figure 4(a), there is no image on the second line, so
Although the line is not particularly shown, the values of the image data signals IMI, IM2 and the shadow length residual value signals SR4, SR2 are all O, similar to the first line.

Next, the value of the image data signal IM2 of the third line becomes 255 in synchronization with the rise of the fourth pixel synchronization signal CLOCK after the rise of the scanning line synchronization signal LSYNC, and the value of the third pixel synchronization signal CLOCK becomes 255. O again in synchronization with the rise
becomes. That is, the value of the image data signal IM2 of the third line is the value from the rise of the scanning line synchronization signal LSYNC to the rise of the fourth pixel synchronization signal CLOCK until the rise of the 13th pixel synchronization signal CLOCK. , 255. Hereinafter, such a state will be abbreviated as, for example, "the value of the image data signal IM2 becomes 255 in the period of 4 to 13 clocks".

On the other hand, the value of the third line shadow length residual value signal SR4 output from the flip-flop 39 remains O.

Here, if the value of the threshold signal TH is now set to 128, the image area signal IA from the comparator 32
is at the L level during the period from 4 to 13 clocks, and at the H level during the other periods. Therefore, the value of the shadow length residual value signal SR2 of the third line outputted by the selector 35 during the period of 4 to 13 clocks becomes the value SS set by the shadow length setting switch 37, and becomes O during the other periods. In the case of FIG. 5, the shadow length setting value signal S by the shadow length setting switch 37
The case where S is 2 is shown. That is, this is a case where the length of the shadow to be generated is two dots.

Next, the processing for the fourth line will be explained. The value of the image data signal IM2 on the fourth line is 2 during the period of 4 to 14 clocks.
55, and becomes O in other periods. On the other hand, the value of the fourth line shadow length residual value signal SR4 output from the flip-flop 39 is the third line shadow length residual value signal SR2.
is delayed by one clock of the pixel synchronization signal CLOCK.

That is, it becomes 2 during the period of 5 to 14 clocks, and becomes 0 during the other periods. Also, the shadow length residual value signal S of the fourth line
The value of R2 is the value set by the shadow length setting switch 37 = 2 during the period of 4 to 14 clocks, and the value of R2 is 2 during the period of 4 to 14 clocks, and the value of R2 is 2 during the period of 4 to 14 clocks, and the value of R2 is
becomes.

Furthermore, the value of the image data signal IM2 on the fifth line is 4 to
25 during the 7 clock period and the 11-15 clock period.
5, and O during other periods. On the other hand, the value of the shadow length residual value signal SR4 of the 5th line output from the flip-flop 39 is the value obtained by delaying the shadow length residual value signal SR2 of the 4th line by one clock of the pixel synchronization signal CLOCK, that is, 5~ It becomes 2 during the l5 clock period and becomes 0 during other periods. Therefore, the shadow length residual value signal S of the 5th line
Since the image area signal IA is at L level during the 4th to 7th clock period and the 11th to 15th clock period, the value of R2 is as follows.
During this time, the value set by the shadow length setting switch 37 is 2. On the other hand, for other periods, the shadow length residual value signal SR4 is a value obtained by performing subtraction processing. That is, it becomes 1 during the period of 7 to 11 clocks, and becomes 0 during the other periods.

The value of the image data signal IM2 on the 6th line is 255 during the 4th to 7th clock period and the 12th to 15th clock period, and 0 during the other periods.

On the other hand, the value of the shadow length residual value signal SR4 of the 6th line outputted from the flip-flop 39 is the value obtained by delaying the shadow length residual value signal SR2 of the 5th line by 1 clock of the pixel synchronization signal CLOCK, that is, 5~ period of 8 clocks and 12~l
It becomes 2 during a period of 6 clocks, becomes 1 during a period of 8 to 12 clocks, and becomes O during other periods. Therefore, the value of the shadow length residual value signal SR2 on the 6th line becomes 2 during the period of 4 to 7 clocks and the period of 12 to 15 clocks.

On the other hand, for other periods, the value is obtained by subtracting the shadow length residual value signal SR4, so for periods of 7 to 8 clocks and 1
It becomes 1 during the period of 5 to 16 clocks, and becomes 0 during other periods.

Next, the value of the image data signal IM2 on the seventh line is 4 to
7 clocks and 12 to 15 clocks.
5, and O during other periods. On the other hand, the value of the shadow length residual value signal SR4 of the 7th line outputted from the flip-flop 39 is determined for the period from 5 to 8 clocks and from 13 to l6.
2 in the clock period, 8-9 clock and 16-
It becomes 1 during the l7 Glock period, and becomes O during other periods. Therefore, the value of the shadow length residual value signal SR2 on the 7th line becomes 2 in the period of 4 to 7 clocks and the period of 12 to 15 clocks. On the other hand, in other periods, the value is obtained by subtracting the shadow length residual value signal SR4, so it becomes 1 in the 7th to 8th clock period and 15th to 16th clock period, and 0 in other periods. Become.

Moreover, the value of the image data signal IM2 of the 8th line is 4 to
25 during the 7 clock period and during the 11-14 clock period.
5, and O during other periods. On the other hand, the value of the shadow length residual value signal SR4 of the 8th line outputted from the flip-flop 39 is for the period of 5 to 8 clocks and the period of 13 to 16 clocks.
2 in the clock period, 8-9 clock and 16-
It becomes 1 during the period of 17 clocks, and becomes O during the other periods. Therefore, the value of the shadow length residual value signal SR2 on the 8th line becomes 2 during the 4th to 7th clock period and the 11th to 14th clock period. On the other hand, in other periods, the value is obtained by subtracting the shadow length residual value signal SR4, so in the period of 7 to 8 clocks and the period of I4 to 16 clocks! , and becomes 0 during other periods.

On the other hand, the shadow area signal SA from the NAND gate 36 is determined to be at L level, that is, a shadow area, when the value of the shadow length residual value signal SR4 is not 0 and the image area signal IA is at the I'' level. to show that

Here, in the case of FIG. 5, the image area signal IA is H.
Since the level is the same as when the value of the image data signal IM2 is O, it is determined that it is a shadow area when the value of the shadow length residual value signal SR4 is not O and the image data signal IM2 This is the case when the value of is O. In Fig. 5, this condition is satisfied during the 7th to 11th clock period at the 5th line entrance, the 7th to 12th clock period at the 6th line entrance, the 15th to 16th clock period, and the 7th to 9th clock period at the 7th line entrance. period, 1
These are the 5th to 17th clock period, the 7th to 9th clock period of the 8th line, and the 15th to 17th clock period. Therefore, the shadow data signal SD is selected by the selector 33 during these periods, and the image data signal IM2 is output during other periods. In addition, here, the shadow density setting switch 4
3, the shadow data signal SD is set to 128.

In the above example, the processing up to the 8th line of the input image in FIG. 4(a) is explained, but the 9th line and subsequent lines are processed in the same way.

FIG. 4(b) shows the results of applying the above-described processing to all the images shown in FIG. 4(a). Figure 4(b)
The shaded area in the middle is a shaded area, and the pixel value thereof is 128. The number of pixels in the white part is 0, and the number of pixels in the black part (image part) is 255, which remains as shown in FIG. As shown in this shadow casting result, a three-dimensional shadow with a length of 2 dots set by the shadow length setting switch 37 is placed in the lower right direction of 45 degrees in the figure, with a density set by the shadow density setting switch 43. It is something that can be added.

In addition, in the case of the configuration shown in FIG. 2, the line buffer 38
Since the time delay of one scanning line + one pixel is caused by the flip-flop 39, a shadow is added in the direction of 45 degrees to the lower right, but if the order of the line buffer 38 and the flip-flop 39 is changed By connecting flip-flops in multiple stages, it is possible to obtain a time delay of one scanning line and several pixels, and to make a shadow directed in a direction other than the lower right 45° direction. Furthermore, the delay time may be made variable so that the direction of the added shadow can be selected.

In addition, in FIG. 2, since the input image signal is multivalued data, a comparator 32 and a threshold value setting switch 34 are required to determine the presence or absence of an image, but the input image signal If the data is binary data from the beginning, the comparator 32 and threshold setting switch 34 are unnecessary.

Furthermore, when the input image signal is binary data, the number of bits of the selector 33 decreases, so the shadow data signal S
It is advantageous to use binary data for D as well. In this case, the shadow data signal SD is not a fixed value set by the shadow density setting switch 43 as shown in FIG.
A periodic signal such as that obtained by counting K, scanning line synchronization signal LSYNC, etc. may be used.

Furthermore, although the configuration example in Figure 2 assumes the case where a three-dimensional shadow is added to a monochrome image, the three-dimensional shadow addition processing device invented by Kishi is also applicable to the case where a three-dimensional shadow is added to a full-color image. applicable.

In addition, in the case of Figure 2, it is possible to generate a shadow with a length of up to 255 dots by simply delaying the 8-bit shadow length residual value signal by one scanning line + one pixel. The addition of a long 3D shadow can be realized at low cost using a small memory capacity.

Next, a second embodiment of the present invention will be described with reference to FIGS. 6 to 9.

Generally, when a three-dimensional shadow is added to a character or graphic image with a thin line width, the original image is hidden by the added shadow and becomes difficult to read. Here, in the case of the above embodiment, since the presence or absence of an image is determined based only on the image data of one pixel of interest, a shadow is added even to a thin character image with a one-dot width, for example. . Also, noise (generally dot-like) may appear in the input image data.
If such a noise image contains a stereoscopic shadow, the noise will be magnified and the output image will become even more smudged. That is, the three-dimensional shadow addition processing device of this embodiment is, for example, a digital copying machine comprising a scanner 46 equipped with a document mounting table 45, an image processing section 47, and a printer section 48, as schematically shown in FIG. It also applies in cases such as
When the scanner 46 reads a document set on the document table 45 and outputs it as image data, dirt or the like in the document may be mixed in as a noise image, causing the above-mentioned problem. Although it is possible to remove such a noise image by noise removal processing before inputting it to the image area determining means, this is not preferable since thin lines and the like in the character image will also be erased at the same time.

Therefore, in this embodiment, the configuration of the image area determination means l2 is devised so that the presence or absence of an image is determined based not only on one image data but also on a plurality of image data.
For example, a three-dimensional shadow is not added to a thin line image or the like.

First, in FIG. 7, the timing control circuit 50, the image data generating means 5l, and the image data receiving means 52, which are not shown in FIG. 2 and the like, are illustrated. As in the previous embodiment, the timing control circuit 50 outputs a frame synchronization signal FSYNC, a line synchronization signal LSYNC, and a pixel synchronization signal CLOCK as shown in FIG. 8, and controls the operation timing of the circuit shown in FIG. . The image data generating means 5l outputs a Rusk type image data signal IMI in synchronization with the above signal as shown in FIG. In this embodiment, the image data signal IM1 is 8 bits and has 256 gradations of gradation (dark: 255 to light 20). This image data signal IMI is input to the image area determining means 12 together with the selector 33.

The image area determining means 12 of this embodiment includes a comparator 53
It also includes a main-scanning direction image presence/absence detection circuit 54 and a sub-scanning direction image presence/absence detection circuit 55 .

The comparator 53 compares the upper 4-bit signal TM2 in the image data signal IMI with the 4-bit density level signal output from the density level selection threshold setting switch 56. The agony value setting switch 56 allows the operator to make 4 bits=16 settings depending on the shading of the image to be processed. Therefore, the values indicated by the image data signal IMI are output from the comparator 53 as 16, 32, . . . , 240, 2 according to the setting of the threshold value setting switch 56.
When the number is 56 or more, that is, when there is a possibility that an image exists, an H level signal is output, and in other cases, an L level signal is output. Furthermore, since the image data signal IMI never exceeds 256, the output of the comparator 53 in this case is always at the L level.

The main scanning direction image presence detection circuit 54 includes a D flip-flop 57, an OR gate 58, and an AND gate 59. , D flip-flop 57 operates in synchronization with the pixel synchronization signal CLOCK input to the CI-K terminal, and outputs the signal input to the D terminal from the Q terminal with a delay of one pixel time. Therefore, when the signal output from the converter 53 becomes H level for two or three pixels in the main scanning direction consecutively, it is determined that there is a possibility that an image exists, and the AND gate 59 outputs [{ output a level signal. On the other hand, the signal input from the converter 53 is
If the width in the main scanning direction is one pixel or less, it is treated as "no image".

The sub-scanning direction image presence/absence detection circuit 55 includes the sub-scanning direction delay circuit 55, the FTFO memory 60, the OR gate 6l, and the NAN
It consists of a D gate 62. FIFO memory 56 is RST
Line synchronization signals LSYNC and CLK input to the terminals
It operates in synchronization with the pixel synchronization signal CLOCK inputted to the terminal, and outputs the signal inputted to the Di@ terminal from the DO terminal after being delayed by the time corresponding to one scanning line. Therefore,
From the comparator 53 to the main scanning direction image presence/absence detection circuit 54
When the signal outputted from the AND gate 59 through the NAND gate 59 becomes H level for 2 or 3 pixels consecutively in the sub-scanning direction, it is determined that "image exists", and the image area signal of L level is output from the NAND gate 62. Output IA. On the other hand, when the width of the signal input from the converter 53 in the main scanning direction is one pixel or less, it is determined that there is no image, and the image area signal IA becomes H level.

Using the image area signal IA determined based on the plurality of image data signals IMI in this manner, the rest of the processing is performed in the same manner as in the previous embodiment. Therefore, even if a character or graphic image with a width of 1 pixel is input, or a noise image of about 1 pixel is input, it is not determined that there is an image, so 3D shadows are not added to these, and thick line width Three-dimensional shadows are added only to character images, etc. Therefore, characters with thin line widths are not difficult to read due to shadows, and noisy images are not enlarged due to shadows. For example, as shown in FIG. 9(a), when a character image with a width of 2 to 3 pixels and a thin frame-shaped image with a width of 1 pixel coexist, according to the shadow addition process of this embodiment, As shown in FIG. 3B, shadows are added only to character images with thick line widths, and no shadows are added to frame-shaped images with thin line widths.

By the way, the legibility of a shaded character is related to the balance between the thickness of the character and the length of the added shadow. In this point,
According to the embodiment, the length of the shadow to be added can be selected by the shadow length setting switch 37, but if the length of the shadow to be added is set long in conjunction with a thick character image, it becomes easier to read a relatively thin character image. There is a tendency for the quality to decrease relatively.

In this regard, in this embodiment, the image area determination means l2 is provided with a pixel number selection switch 63 serving as data number selection means, and this pixel number selection switch 63 is connected to the OR gate 58.61. This pixel number selection switch 63 can be switched by the operator according to the line width of the image to be processed, and determines whether the criterion for determining the presence or absence of an image is two consecutive main and sub pixels, or three consecutive pixels. can be selected. in particular,
When the pixel number selection switch 63 is set to OFF state, OR
Since the gates 58 and 61 always output the H level, if the output of the comparator 53 or the AND gate 59 reaches the H level for two consecutive pixels, it is treated as "image present".

When the pixel number selection switch 63 is set to the ON state, it will not be treated as "image present" unless three consecutive pixels reach the H level.

Therefore, according to this embodiment, the operator can select the line width of an image to which a three-dimensional shadow is added, and the three-dimensional shadow can be added without impairing the readability of images such as characters with thin line widths. I can do it.

The structure and operation of other parts in FIG. 7 are similar to those in FIG. 2, etc. however. Shadow length setting switch 3 of this embodiment
7, the length of the shadow to be generated is 0, 16, 32,...
There are 16 types of 240 pixels. Further, the shadow density setting switch 43 of this embodiment is the threshold value setting switch 6.
2, 8, 16,...,
It is assumed that it can take a value of 120. That is, the shadow data signal SD is configured to have a value of 1/2 of the threshold value set by the threshold value setting switch 62. Therefore,
This results in a clear difference between the values of the image part and the added shadow part, and it is possible to add a three-dimensional shadow without impairing the readability of the image.

In this embodiment, the line width of the image to which a shadow is added is 2 or 3 consecutive pixels in the main and sub-scanning directions, but generally speaking, the image area determining means l2 By changing the circuit configuration, it is possible to apply the method to a larger number of pixel widths.

Effects of the Invention Since the present invention is configured as described above, the length of the remaining shadow is calculated based on the set value of the shadow length by the shadow length data generation means and the image data of the current pixel of interest. It is only necessary to update, delay, and count the data that indicates the length of the shadow to identify whether it is a shadow area or not. Even when generating a long shadow, the length of the remaining shadow must be updated, delayed, or This can be dealt with by performing counting processing, and therefore, it is possible to solve the problem by performing counting processing, so that the number of sub-scanning lines can be calculated by counting the number of sub-scanning lines. ! ii) It is no longer necessary to hold the image area determination result of the image data itself with a delay, and a small memory capacity is required. In particular, by determining the presence or absence of an image based on a plurality of image data in the image area determination means and subjecting it to processing for adding a shadow, it is possible to eliminate characters with thin line width, graphic images, noise images, etc. There is no need to add 3D shadows, impair the readability of the image, or enlarge the noise image.In addition, if a means for selecting the number of data is provided, characters that add 3D shadows will not be added. The operator can select line widths such as , etc., and it becomes possible to add three-dimensional shadows that are well-balanced between the image and the shadows.

[Brief explanation of drawings]

1 to 5 show a first embodiment of the present invention, in which FIG. 1 is a conceptual block diagram, FIG. 2 is a block diagram showing a concrete example, and FIG. 3 is a timing chart. Fourth
The figures are explanatory diagrams showing examples of images before and after image processing, Fig. 5 is a timing chart, Figs. 6 to 9 show a second embodiment of the present invention, and Fig. 6 is an outline of a digital copying machine. 7 is a block diagram, FIG. 8 is a timing chart, FIG. 9 is an explanatory diagram showing an example of images before and after image processing,
FIG. 0 is a block diagram showing a conventional example. I1... Input image data, 13... Image data selection means, l6... Shadow area determination means, 17... Shadow length data updating means, 19... Shadow length data generation means, 2l...
- Shadow length data counting means, 23... Shadow length data delaying means, 26... Shadow data generation means, 27... Shadow data,
29...Shadow area specifying means, 33...Image data selection means, 35...Shadow length data updating means, 36.41...
・Shadow area determination means, 37...Shadow length data generation means, 3
8, 39...Shadow length data delay means, 40.42...
Shadow length data counting means, 43...Shadow data generation means, 5
1... Image data generation means, 52... Image data receiving means, 63... Data number selection means Applicant: Rico Co., Ltd.

Claims (1)

[Claims] 1. Shadow length data generation means for generating a setting value for the length of a shadow to be generated; and image area determination means for determining the presence or absence of an image based on image data input from the image data generation means. ,
shadow length data delay means for delaying data representing the length of the remaining shadow in the main scanning direction and sub-scanning direction; shadow length data counting means for counting the data representing the length of the residual shadow; and the shadow length data. Either the data representing the length of the remaining shadow delayed by the delay means and counted by the shadow length data counting means or the shadow length data generated by the shadow length data generation means is sent to the image area determining means. a shadow length data updating means for updating data representing the length of the residual shadow with respect to the set value selected based on the determination result; a shadow area specifying means having a shadow area determining means for determining a shadow area; a shadow data generating means for generating shadow data; and a specifying result of the shadow area specifying means for either the image data or the shadow data. 1. A three-dimensional shadow addition processing device comprising: image data selection means for selectively outputting image data to an image data reception means based on the image data reception means. 2. The stereoscopic shadow addition processing apparatus according to claim 1, wherein the image area determining means determines the presence or absence of an image based on a plurality of image data inputted from the image data generating means. 3. The image area determination means has a data number selection means for selecting the number of image data for determining the presence or absence of an image, and the image data generation means inputs data according to the number of image data selected by the data number selection means. 3. The stereoscopic shadow addition processing apparatus according to claim 2, wherein the presence or absence of an image is determined based on image data.