JPH02288929A - Shared memory access adjustment control method - Google Patents

Abstract

PURPOSE:To resolve the impossibility of accurate data transfer by judging whether the access to a shared memory is possible or not by output states of first and second access possibility/impossibility reporting means and enabling a CPU which judges the possibility of access to access the shared memory. CONSTITUTION:When both of a first CPU 1 and a second CPU 2 will execute the access to a shared memory 3, they request the access to a shared memory adjusting circuit 5 by program instructions and inquire whether the access is permitted or not. They fetch the output states of first and second access possibility/impossibility reporting means 11 and 12 as data values and judge whether the access to the shared memory 3 is permitted or not by these data values, and the CPU which judges that the access is permitted accesses the shared memory 3. Thus, trouble that accurate one-word data cannot be transferred is resolved.

Description

Detailed Description of the Invention <Industrial Application Field> The present invention provides shared memory access adjustment control that arbitrates whether or not each CPU can access the shared memory in order to avoid contention in access to the shared memory by CPUs with different bit numbers. Regarding the method.

<Prior Art> Recently, a method has been used in which two CPUs having different bit numbers access a shared memory using a dual port RAM. For such a shared memory, if there are two CPUs, say one is 8 bits and the other is 16 bits, then
The memory space for the shared memory is set as in the example shown in FIG.

In other words, the same memory space of the shared memory is, for example, 100H1IOII (address 8) on an 8-bit CPU.
It is set in units of bits (1 byte), and for a 16-bit CPU, it is set in 16 bits (1000 f-(, 1001H address)
It is set in bit (1 word) units. When reading the same memory space like this, the 8-bit CPU obtains lower data 065H when it reads address 100IT, obtains upper data 087H when it reads address 101H, and reads these two times. Access data 08765
H can be obtained. On the other hand, 16-bit Cp
u can read the 100IH address in units of 1 word at once and obtain data 08765H.Problem to be solved by invention 7> However, if either CPU accesses the shared memory, However, as in the example shown in FIG. 4, a problem occurs when both CPUs access the same memory space in the shared memory at a certain timing.

Specifically, after the 8-bit l-CPU reads address 100H, the 16-bit l-CPU reads address 1 of the same memory space.
001. When accessing address I (and writing data o1234H, the data at address 101 I
265 I (and the 8-bit CPU will obtain incorrect data.

In other words, in this way, when Cl)U with 1-byte access and CPU with 1-word access compete for their addresses on the shared memory, the CPU with 1-byte access makes 1 access, and the word-access CPU makes 1 access. (2) The upper byte data of the word data will be accessed in an undefined state, resulting in a problem that one word of accurate data cannot be transferred.

Means and operation for solving the above problems> In order to solve the above problems, a first access notification means for notifying a first CPU having a certain number of bits as to whether access to the shared memory is possible;
1st. a second access notification means for informing a second CPU having a bit number different from that of the CPU whether or not the shared memory can be accessed; A clock supply means for inputting a clock to the CPU is provided, and the respective outputs of the first and second access notification means are connected to the data buses of the first and second CPUs, respectively. a memory adjustment circuit, and a first
When both the first and second CPUs attempt to access the shared memory, both CPUs request access to the shared memory adjustment circuit by their respective program instructions and inquire as to whether access is possible. The output states of both access controller notification means in 2 are taken in as data values, and based on these data values, it is determined whether or not the shared memory can be accessed, and C■]U, which has been determined to be the access town, is allowed to access the shared memory. . and 1. In order to input the clock of the shared memory access adjustment circuit to each CPU in accordance with the program instructions of both the first and second CPUs.
The clock has a higher frequency than the basic clock of , and the clock input of the first access notification means and the clock input of the second access permission notification means are shifted in phase.

More specifically, the input condition for the first access notification means is the output of the second access notification means, and the input condition for the second access notification means is the output of the first access notification means. .

Therefore, even if the second CPU tries to access the shared memory and uses a program command to access the second access notification means while the first CPU is accessing the shared memory, the first cPU is accessing the shared memory. The output of the first access notification means is inverted, and the output of the second access permission notification means is not inverted and remains at the logic at reset. Therefore, the normal output of the second access notification means outputs logic "H" to the data bus of the second CPU. As a result, the second CPU sets any bit to logic "H", for example, the data value F.
FH (FFH regardless of which signal line of the data bus is connected)
and learn whether shared memory is inaccessible.

When the first CPU finishes accessing the shared memory, it resets the first access notification means and moves on to other operations. In this state, from time to time while performing other prescribed actions,
When the second CPU attempts to access the shared memory and accesses the second access notification means by a program command, the output of the second access notification means, which uses the output of the first access notification means as an input condition, is transmitted to the second CPU. It is reversed by the program instruction. Therefore, the inverted output of the second access notification means outputs a logic "L" to the data bus of the second CPU. Then, the second CPU takes in a data value with an arbitrary bit set to logic "L", for example, a data value FEH when connected to a data bus or signal line, and enables access to the shared memory. know.

The second CPU, which has finished accessing the shared memory,
Similar to the CPU, the second access notification means is reset and the process proceeds to other operations.

What has been described above is exactly the same even if the conditions for both CPUs are reversed.

Next, while both the first and second access notification means are being reset, each CPU accesses each access permission notification means at the same time. Since the clock input of the notifying means is inputted with the phase inverted, the output of one of the access notifying means is determined and fixed first, and both access notifying means do not invert their outputs at the same time. Only the CPUs in the shared memory can access the shared memory.

Example of implementation Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a circuit diagram of a circuit used in an embodiment of the present invention.

As can be seen from FIG. 1, the first CPU, ie, the 8-bit CPU 1 with 1-byte access, and the second CPU 2, ie, the 16-bit CPU 2 with 1-word access, each have an address and an address in the shared memory 3, which is a dual-port RAM.
Connected by data bus 1a12a, shared memory 3
has been accessed.

The adjustment circuit 5 that adjusts whether or not both CPUs 2 can access the shared memory 3 includes a flip-flop 11 that is controlled by the first CPUI and serves as a "first access notification means" that notifies the first CPU 1 whether or not the shared memory 3 can be accessed. The second CPU 2 is controlled by the 20th PU2.
A second flip-flop 12 serves as a "second access notification means" that informs the user whether access to the shared memory 3 is permitted or not.
and its peripheral circuits.

Specifically, the input terminal (J
) is connected to the output of the NOR gate circuit 13, and the other input terminal (K) is grounded. And NOR gate 1
The two inputs of 3 are connected to the second flip-flop 1, respectively.
The output from the normal rotation output terminal (Q) of the first flip-flop 11 is connected to the signal line INl outputted from the decoder circuit 4a according to the program command of the first CPU 1, and the reset terminal (CL R) of the first flip-flop 11 is The first flip-flop 11 is connected to a signal line ○UTI outputted from the first CPUI, and the first flip-flop 11 is reset by a program command from the first CPUI. Furthermore, the inverting output terminals (mutual) of the first flip-flop 11 are connected to the signal line I
It is connected to the input of a 3-state buffer 15 with output control and a non-inverted output whose gate is opened by the NL signal to obtain an output, and the output of the 3-state buffer 15 is connected to the first CPU 1.
It is one of the signal lines of the data bus of the address/data bus 1a. Connected to the signal line.

Similarly, the input terminal (J) of the second flip-flop 12
is connected to the output J of the NOR gate circuit 14, and the other input terminal (K) is grounded. And NOR gate 1
The two inputs of 4 are connected to the first flip-flop 1, respectively.
The output from the normal rotation output terminal (Q) of (2) is connected to the signal line IN2 which is output from the decoder circuit 4b according to the program command of the second CPU2, and the second flip-flop 12
The reset terminal (CLR) of the second flip-flop 12 is connected to the signal line 0UT2 outputted from the decoder circuit 4b, and the second flip-flop 12 is reset by a program command from the second CPU2. Furthermore, the inverting output terminal (Q) of the second flip-flop 12 is connected to the signal line IN
The output of the 3-state buffer 16 is connected to the input of the 3-state buffer 16 with output control, which has a non-inverted output and whose gate is opened by the signal of 2 to obtain an output. It's one of the lines. Connected to the signal line.

The oscillator 17 is also responsive to the output of the NOR gate 13.14, in particular to signals on the input lines INI, IN2 which carry program instructions from the first CPUI and the second CPU2. The oscillator has a higher frequency than the basic clocks X1 and X2.

The output of this oscillator 17 is input to the clock input terminal (i'') of the first flip-flop 11, inverted by the inverter circuit 18, and output to the second flip-flop 2.
This is to avoid simultaneous operation of each flip-flop when the first CPU 2 and the second CPU 2 control the first flip-flop 11 and the second flip-flop 12 at the same time. It's for a reason.

Next, the coordination and control method when both CPUs 1.2 access the shared memory 3 will be described.

First flip-flop 11 and second flip-flop 12
At the initial time, CP U ] and 2nd CP
It is reset by a predetermined program command of U2, and its normal output Q and inverted output Q are logics ``7'' and ``H'', respectively.Here, the first CPU 1 wants to access the shared memory 3. In this case, the first CPU inquires of the shared memory adjustment control circuit 5 and takes in the state of the output of the first flip-flop 11 as a data value, thereby knowing whether or not the shared memory 3 can be accessed. access.

Specifically, the +-th CPU 1 executes the program command [1N
When the command 0AI()l is generated, a logic "L" is output from the decoder circuit 4a to the signal line INI, and is input to one of the two NOR gates 13.

Here, the other input line of the NOR gate 13 is connected to the non-inverting output Q of the second flip-flop 12, and since the second flip-flop 12 is reset, the non-inverting output Q of the second flip-flop 12 is logic " It is "L".

Then, when this logic "■7" state is established, N OR keto 1
The gate of NOR gate 13 is opened, which causes the input voltage of the knee to become logic "L", so the output of NOR gate 13 is
The logic becomes "II" and is input to the input terminal J of the first flip-flop 11.

As a result, the input terminals J of the first flip-flop 11,
The logic is “H”, “L”, and this logic “■]”,■
,'' is determined by the falling edge of the clock CLK1 supplied from the oscillator 17 to the clock T of the first flip-flop 11, and the normal output Q of the first flip-flop 11 changes from logic "L" to logic "H". At the same time, the inverted output Q of the first flip-flop 11 changes from logic "TI" to logic "L".

Here, the inverted output Q is the output control of the non-inverted output, ]3
connected to the state buffer 15, whose output is the first C
PU1 address/data bus data)<S line. Since the signal line IN1 is connected to
``, the output control of the 3-state buffer 15 is released, and the logic ``■7'' is outputted.

The first CPUI is connected to the data bus.

Since it becomes logic "L'", this is taken in as a data value F E H, and it is known that the shared memory 3 can be accessed.

While the first CPUI is accessing the shared memory 3, the first
The outputs EQ and Q of the flip-flop 11 are logic "
It remains at "H" and "L".

When access to shared memory 3 is finished, the first CPU
generates a program command [:OUT IAH), which causes the signal line 0UT to be output from the decoder circuit 4a.
Logic "L" is generated at 1. Then, since the signal line 0UTI is connected to the reset terminal CLR of the first flip-flop 11, the first flip-flop 11 is forcibly reset, and its outputs Q and Q become logic "L" and "H" waiting for an inquiry. Then, after that, the first CPU1
moves to a predetermined execution operation.

The first CPUI is accessing the shared memory 3, that is, the outputs Q and Q of the first flip-flop 11 are at logic "H" or "
When the second CPU 2 needs to access the shared memory 3 in the "L" state, the second CPU 2 similarly asks the second flip-flop 12 of the shared memory access adjustment circuit 5 whether access is possible or not, and the second flip-flop 12
The state of the output is taken in as a data value, thereby knowing whether or not the shared memory 3 can be accessed, and when it is determined that the shared memory 3 can be accessed, the shared memory 3 is accessed.

Specifically, the second CPU 2 receives the program command [IN 0
When the command BH) is generated, the decoder circuit 4b outputs logic "L" to the IN2 signal line, and the two-man NO
It is input to one side of the R gate 14.

Here, the other input line of the NOR gate 1-14 is connected to the normal output Q of the first flip-flop 11.
Since the CPU 1 is accessing the shared memory 3, the normal output Q of the first flip-flop 11 is at logic "H". Therefore, the NOR gate 14 is closed, and the output of the NOR gate 14 becomes logic "L".

Then, this logic "L" output is output from the first flip-flop 1.
As a result, the logic "L", "L" is input to the input terminal J of the first flip-flop 11, and this logic "L", "L" is transmitted from the oscillator 7 to the inverter circuit 18. is inverted by the second flip-flop 12
However, the output of the second flip-flop 12 remains unchanged from the previous state, and the logic of the normal output Q is "L" as in the previous state. . At the same time, the logic of the inversion ratio horn ◇ remains "H".

Here, the inverted specific power negative is connected to a 3-state buffer 1G with output control of a non-inverted output, and its output is the data bus line of the address/data bus of the second CPU 2. Therefore, the output control of the 3-state buffer 16 is canceled by the logic "L" of the signal line 1N2, and the logic "H" is outputted.

Then, the second CPU 2 is connected to the data bus. is logic II
By becoming HI+, for example, the data value F
FH, and know whether the shared memory 3 cannot be accessed.

When the second CPU 2 learns that the first CPUI is accessing the shared memory 3, it queries the shared memory access adjustment circuit 5 from time to time while performing other predetermined operations, and repeats this until it learns that access is possible. Thereafter, as described above, it performs the same operations as the first CPU 1 and ends.

In the above explanation, we have taken as an example the control of the second CPU 2 when the tcput is accessing the shared memory 3, but the same applies when the states of the first CPU and the second CPU 2 are reversed. Data value FEH when access is possible, data value F when access is not possible.
Find out whether access is possible as FH.

Next, a case will be described in which the first CPU I and the second CPU 2 simultaneously inquire of the first flip-flop 11 and the second flip-flop 12 of the shared memory access adjustment circuit 5.

FIG. 2 is a time chart for explaining avoidance of simultaneous operation of the first flip-flop 11 and the second flip-flop 12 in the shared memory access adjustment circuit 5. The signal names in this figure are the same as in FIG. As can be seen from FIG. 2, the clocks CLK1 and CLK2 are out of phase and have inverted signal waveforms.

When both CPUs 1.2 access the shared memory access adjustment circuit 5 at the same time, when looking at the clock CLK1, the logic “H” including the rising edge of CLK1 is
” part (A in FIG. 2) and the falling edge part. This is a case where the signal lines INI and IN2 in the section ``(B in FIG. 2) become logic ``L'' at the same time.

In Fig. 2, ■ indicates the part A, which is the signal line INI and the signal line I.
This is a time chart 1 for avoiding simultaneous operations when N2 and N2 become logic "7" at the same time. INI and I in part A
When N2 is at logic "L" at the same time, both the first and second flip-flops 11.12 are reset, so both NOR gates 13.14
The gates of both flip-flops 11 and 12 are open, and their respective outputs become logic "H".
waits for the input of clocks CLK1, CT, and K2.

However, since the falling edge of CLKl comes first in time, this falling edge causes the first flip-flop 1
The output (Q) of 1 becomes logic "1-■". This results in N
The OR gate 14 is closed and its output is a logic “
Even if the falling edge of continuation <, CI, and K2 comes, the output of the second flip-flop 12 remains at the logic "■7" and the output does not change. Therefore, in this case, the output of the first C
P U 1 determines that the shared memory 3 can be accessed, and the other box 2 CPU 2 determines that it cannot be accessed, so that both of them will not be able to access it at the same time.

■ in Figure 2 is the part of ■3 (U return line INI and IN
This is a time chart 1 for avoiding simultaneous operations when the signals 2 and 2 become logic "L" at the same time. In this case, the operation is almost the same as in the part before, but the difference is that the clock CL K 2 falls first in time. Therefore, the output (Q) of the second flip-flop 12 is at logic "'H".
”. Then, as a result, the gate of NOR gate 1 13 is closed and its output returns to the logic “■7”, continuing <
Even when the falling edge of CLKI comes, the output of the first flip-flop 11 remains at logic "L" and the output does not change.

Therefore, in this case, the second CPU 2 determines that the shared memory 3 can be accessed, and the first CPU 2 determines that the shared memory 3 cannot be accessed, so that both of them will not be able to access the shared memory 3 at the same time.

In this manner, simultaneous access by the first CPUI and the second CPU 2 to the shared memory is avoided.

In the above embodiment, the first CPU 1 has 8 pins 1-CP.
Although the second CPU 2 is a 16-bit CPU, it goes without saying that the present invention can also be applied to CPUs with other bit numbers. Further, in this embodiment, the outputs of the first flip-flop 11 and the second flip-flop 12 are connected to the data bus of each CPU. Of course, it can also be connected to the signal line or to other signal lines of the data bus.

Furthermore, the present invention can also be implemented by replacing each circuit element constituting the shared memory access adjustment circuit 5 with another circuit element having an equivalent function.

<Effects of the Invention> As described above, according to the shared memory access adjustment control method according to the present invention, a shared memory access adjustment circuit with a simple circuit configuration including both the first and second access permission reporting means is provided, and different Both the first and second CPs have bi-soto numbers.
When U attempts to access the shared memory, both CPUs access the shared memory adjustment circuit according to their respective program instructions, and use the output states of both the first and second access notification means as data values. This data value is used to determine whether the shared memory can be accessed, allowing C)) U to access the shared memory, and preventing both CIs) U from accessing the shared memory at the same time. This has the effect of resolving the problem of not being able to transfer accurate data in the conventional technology, and also makes it possible for the CPU that cannot access the shared memory to This has the effect that it is possible to access other modules, thereby improving the processing efficiency of the CPU.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a circuit used in an embodiment of the present invention, FIG. 2 is a time chart diagram for explaining avoidance of simultaneous operation of the first flip-flop and the second flip-flop in the shared memory access adjustment circuit, and FIG. is a CPU with 1-byte (8-bit) access on one side.
Figure 4 shows an example of the memory space for a shared memory when the other CPU is a 1-word (16-bit) access CPU, and Figure 4 shows how a 1-byte access CPU and a 1-word access CPU write their addresses on the shared memory. FIG. 7 is a diagram illustrating an example of a case of competition. ■・-----1st CPU La, 2a ---------Address/data bus 2-・°°"2nd CPU 3-----1 Shared memory 4a, 4b-1111 Decoder circuit 5 --- Shared memory access adjustment circuit 11 ----1st flip-flop (first access notification means) 12 ---11 second flip-flop (second access notification device) 13 .14---2-manpower NOR gate 15.16---3-state buffer, 17-・
----Oscillator 18...--Inverter circuit.忿綜 (to), wood 1 (, k

Claims (2)

[Claims] (1) A shared memory access adjustment control method when a first CPU and a second CPU having different numbers of bits access a shared memory, the method comprising: a first access permission notification means that notifies the first CPU whether or not access to the shared memory is permitted; a second access notification means that informs the second CPU whether or not it can access the shared memory; and a clock supply for inputting program instructions of both the first and second CPUs to the first and second access notification means. means, and a first
and a shared memory adjustment circuit in which the respective outputs of the second both access notification means are connected to the respective data buses of both the first and second CPUs, so that both the first and second CPUs can access the shared memory. When attempting to execute , both CPUs access the shared memory adjustment circuit according to their respective program instructions, take in the output states of both the first and second access notification means as data values, and read this data value. Determine whether the shared memory can be accessed by
A shared memory access adjustment control method characterized by allowing a PU to access shared memory. (2) The clock of the shared memory access adjustment circuit is a clock having a higher frequency than the basic clock of both the first and second CPUs, and the clock input of the first access notification means and the clock input of the second access notification means are 2. The shared memory access adjustment control method according to claim 1, wherein the input signals are shifted in phase.