JPH0228340A - Method of mounting semiconductor chip - Google Patents

Method of mounting semiconductor chip

Info

Publication number
JPH0228340A
JPH0228340A JP63142181A JP14218188A JPH0228340A JP H0228340 A JPH0228340 A JP H0228340A JP 63142181 A JP63142181 A JP 63142181A JP 14218188 A JP14218188 A JP 14218188A JP H0228340 A JPH0228340 A JP H0228340A
Authority
JP
Japan
Prior art keywords
semiconductor chip
metal
resin paste
connection
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63142181A
Other languages
Japanese (ja)
Other versions
JP2541284B2 (en
Inventor
Toshio Matsuzaki
松崎 壽夫
Hiroaki Toshima
博彰 戸島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63142181A priority Critical patent/JP2541284B2/en
Publication of JPH0228340A publication Critical patent/JPH0228340A/en
Application granted granted Critical
Publication of JP2541284B2 publication Critical patent/JP2541284B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements

Abstract

PURPOSE:To enable face down mounting on a semiconductor chip having electrode pads without forming a connecting metallic projection by using metallic balls as connecting materials. CONSTITUTION:Resin paste 3 is formed by printing on metallic patterns 22 for connecting with a semiconductor chip 7 installed on the surface of a heat resisting insulating substrate 1 to mount the semiconductor chip 7 thereon and metallic balls 4 are stuck at the same height on the resin paste 3, directly connected with both the metallic patterns 22 for connection on the surface of the substrate 1 and electrode pads 21 on the semiconductor chip 7, and pressurized and heated. Therefore, metal and metal are substantially connected with each other. This enables easily mounting a semiconductor by face down bonding method.

Description

【発明の詳細な説明】 〔概要〕 本発明は、接続用電極パッドを有する半導体チップを、
フェースダウンで直接耐熱絶縁基板に載置、接続する実
装方法に関し、 従来のような接続用金属突起(以下「バンプ」という。
[Detailed Description of the Invention] [Summary] The present invention provides a semiconductor chip having connection electrode pads.
Regarding the mounting method of mounting and connecting directly to a heat-resistant insulating board face-down, conventional metal protrusions for connection (hereinafter referred to as "bumps") are used.

)を形成することなく、ANアルミニウム)電極パッド
を有する大多数の半導体チップでのフェースダウン実装
を実現することを目的とし、半導体チップを載置するた
めの耐熱絶縁基板の表面に設けた該半導体チップとの接
続用金属パターン表面に、樹脂ペーストを印刷形成する
工程と、該樹脂ペーストを未硬化としたまま、金属球を
該樹脂ペーストに付着固定させる工程と、該樹脂ペース
トを硬化させた後、該半導体チップの接続用電極パッド
面を該耐熱絶縁基板の表面に対向させる工程と、 該金属球の位置と該半導体チップの接続用電極パッド位
置とを互いに合わせる工程と、該接続用電極パッドと該
金属球とを、加圧及び加熱によって互いに接続する工程
と によって構成する。
), the semiconductor chip is provided on the surface of a heat-resistant insulating substrate on which the semiconductor chip is mounted, with the aim of realizing face-down mounting of the majority of semiconductor chips that have electrode pads (AN aluminum) without forming an electrode pad. A process of printing and forming a resin paste on the surface of a metal pattern for connection with a chip, a process of adhering and fixing a metal ball to the resin paste while leaving the resin paste uncured, and a process after the resin paste is cured. , a step of making the connection electrode pad surface of the semiconductor chip face the surface of the heat-resistant insulating substrate; a step of aligning the position of the metal ball and the connection electrode pad position of the semiconductor chip; and the step of aligning the connection electrode pad of the semiconductor chip with each other. and the metal ball are connected to each other by applying pressure and heating.

[産業上の利用分野] 本発明は、ハイブリッドIC、サーマルヘッド等に応用
される半導体チップの実装方法に関する。
[Industrial Application Field] The present invention relates to a semiconductor chip mounting method applied to hybrid ICs, thermal heads, etc.

近年、半導体製造技術は急速に進歩を遂げ、半導体チッ
プはより大規模化、かつより高密度化しつつある。
In recent years, semiconductor manufacturing technology has progressed rapidly, and semiconductor chips are becoming larger and more dense.

技術の高度化に伴った前述のような変化が、半導体チッ
プが小型化しつつあるにもかかわらず、外部接続用の電
極パッドを増加させた。
The above-mentioned changes that have accompanied the advancement of technology have led to an increase in the number of electrode pads for external connections, even though semiconductor chips are becoming smaller.

上述のような多数の電極パッドを有する半導体チップを
用い、かつ量産技術的見地から従来の例に劣るところの
ない実装方法が求められ、既存の技術を根本的に改良す
る必要が生じてきた。
There is a need for a mounting method that uses a semiconductor chip having a large number of electrode pads as described above and is no inferior to conventional methods from the standpoint of mass production technology, and it has become necessary to fundamentally improve existing technology.

[従来の技術] 従来、最も一般的に用いられている方法とじてワイヤボ
ンディング実装法がある。
[Prior Art] Conventionally, the most commonly used method is the wire bonding mounting method.

この方法は第4図(a)及び第4図(b)に示すように
、耐熱絶縁基板1表面に載置した半導体チップ7上の接
続用電極パッド21と該耐熱絶縁基板1表面に具備した
接続用金属パターン22との間をボンディングワイヤ4
1により接続するものである。
As shown in FIGS. 4(a) and 4(b), this method involves connecting electrode pads 21 on the semiconductor chip 7 placed on the surface of the heat-resistant insulating substrate 1 and connecting electrode pads 21 provided on the surface of the heat-resistant insulating substrate 1. The bonding wire 4 is connected between the connection metal pattern 22
1.

ところがこの方法は、前述の技術的進展を背景に改良が
なされ、第5図(a)および第5図(b)のフェースダ
ウンによる新しい方法が開発された。
However, this method has been improved against the background of the above-mentioned technological progress, and a new method using face-down method as shown in FIGS. 5(a) and 5(b) has been developed.

フェースダウンにより半導体チップを直接基板に載置、
接続する方法としては、「フリップチップ実装法」が最
も一般的に採られてきた。
Place the semiconductor chip directly on the board by face-down,
The most commonly used connection method has been the flip-chip mounting method.

この方法は、フェースダウンにより載置すべき半導体チ
ップ7に予めバンプ42を設け、半導体チップ側バンプ
42位置と耐熱絶縁基板1面の接続用金属パターン22
位置とを互いに合わせた後、加圧及び加熱によって実装
するものであった。
In this method, bumps 42 are provided in advance on the semiconductor chip 7 to be mounted face-down, and the positions of the bumps 42 on the semiconductor chip side and the connecting metal pattern 22 on the surface of the heat-resistant insulating substrate are
After aligning the positions with each other, it was mounted by applying pressure and heating.

しかし最近は、 1)基板面の半導体チップの接続用電極パッド位置にあ
らかじめ透孔を設け、半導体チップを載置して後透孔に
導電性樹脂を流し込み固化させるもの(特開昭59−1
88955号公報記載の発明)、 2)バンプを、半導体チップを載置すべき回路基板とは
異なる絶縁0体基板上に形成し、これをツールで半導体
チップ側に移し取るもの(特開昭61−50339号公
報記載の発明)及び、3)回路基板面の接続用金属パタ
ーン上の半導体チップを載置すべき位置に予めバンプを
印刷形成し、さらにバンブ上に導電性樹脂層を設けて半
導体チップを実装するもの(特開昭61−94330号
公報記載の発明) 等、種々の方法で改良がなされてきている。
However, recently, 1) a method in which a through hole is made in advance at the position of the connecting electrode pad of the semiconductor chip on the substrate surface, the semiconductor chip is placed, and then a conductive resin is poured into the through hole and solidified (JP-A-59-1
2) A bump is formed on an insulating substrate different from a circuit board on which a semiconductor chip is placed, and the bump is transferred to the semiconductor chip side using a tool (Japanese Patent Laid-Open No. 61 - Invention described in Publication No. 50339) and 3) Bumps are printed in advance at the positions where semiconductor chips are to be placed on the connection metal pattern on the surface of the circuit board, and a conductive resin layer is further provided on the bumps. Improvements have been made in various ways, such as mounting a chip (invention described in Japanese Patent Laid-Open No. 61-94330).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

バンプを形成する従来のフリップチップ実装法には以下
に掲げる利点がある。
The conventional flip-chip mounting method for forming bumps has the following advantages.

1)第4図のように、ワイヤボンディングに比べて実装
エリア9が小さくて済む。
1) As shown in FIG. 4, the mounting area 9 can be smaller compared to wire bonding.

2)基板上の接続用金属パターン22を設けるべき位置
は、半導体チップ7の外周に限定されることなく該半導
体子ツブ7の占める領域なら自由に選択しうる。
2) The position on the substrate where the connecting metal pattern 22 is to be provided is not limited to the outer periphery of the semiconductor chip 7, but can be freely selected as long as it is an area occupied by the semiconductor chip 7.

3)1回の位置合わせで同時に全ての結線ができ、より
作業の能率化が見込める。
3) All wires can be connected at the same time with one alignment, making work more efficient.

4)ワイヤボンディングに比べて機械的接続の信頼性に
優れている。
4) Superior mechanical connection reliability compared to wire bonding.

ところが、 1)接続用電極パッドを存する大多数の半導体チップは
利用できないという欠点 があり、かつ 2)バンプを半導体チップ側に予め設けなければならな
い という技術的困難が生じていた。
However, it has the following disadvantages: 1) Most semiconductor chips having connection electrode pads cannot be used, and 2) bumps must be provided in advance on the semiconductor chip, which is a technical difficulty.

一方で、バンプ形成を改良しようとした公知の王者には
、共通した欠点として、量産技術として実地に応用する
際の技術的困難を挙げることができる。
On the other hand, a common drawback among the known champions who have attempted to improve bump formation is the technical difficulty in practical application as a mass production technique.

個別に説明を加える。Add individual explanations.

まず、特開昭59−188955号公報記載の発明では
、基板の接続用金属パターンと接続用電極バッド両者に
接触しているのは、導電性樹脂である。
First, in the invention described in JP-A-59-188955, the conductive resin is in contact with both the connection metal pattern and the connection electrode pad of the substrate.

ところで導電性樹脂は、樹脂自体には導電性はなく、樹
脂中に金属微粒子を混入することによって導電性を得て
いるものであるために、接続部の電気抵抗が大きくなる
By the way, since the conductive resin itself does not have conductivity and obtains conductivity by mixing fine metal particles into the resin, the electrical resistance of the connection portion increases.

それだけでなく、接続用電極パッドを有する半導体チッ
プの大多数は、接続用電極パッド母材としてAI (ア
ルミニウム)を用いており、空気中の酸素によりAI電
極パッド表面に酸化膜の自然形成が不可避となる。
In addition, the majority of semiconductor chips with connection electrode pads use AI (aluminum) as the base material for the connection electrode pads, and the natural formation of an oxide film on the surface of the AI electrode pads due to oxygen in the air is unavoidable. becomes.

この為に、接続用電極パッドとの接続は、実際には酸化
膜を通してであり、安定した接触は得られない。
For this reason, the connection with the connection electrode pad is actually made through the oxide film, and stable contact cannot be obtained.

つまり、 3)電気的接続の信顛性に問題がある。In other words, 3) There is a problem with the reliability of electrical connections.

加えて導電性樹脂自体の粘性の為に封止せねばならない
部分に気泡が入るという不具合が生じる。
In addition, due to the viscosity of the conductive resin itself, there is a problem that air bubbles may enter the area that needs to be sealed.

また特開昭61−50339号公報記載の発明では、バ
ンプの形成が著しく困難である。
Furthermore, in the invention described in JP-A-61-50339, it is extremely difficult to form bumps.

すなわち、別に用意した絶縁体基板上に設けた4)金属
突起の形成が面倒である上、転写する工程が技術的に著
しく困難である。
That is, 4) forming the metal protrusions provided on a separately prepared insulating substrate is troublesome, and the transfer process is technically extremely difficult.

詳述すれば、該公知例では金属突起の形成には電解メツ
キ法を用いている。
To be more specific, in this known example, an electrolytic plating method is used to form the metal protrusions.

このとき、メツキ用電極をなす金属膜を形成した後、絶
縁膜を該金属膜上に形成する手段によっている。
At this time, after forming a metal film forming an electrode for plating, an insulating film is formed on the metal film.

しかし、該金属膜は金属突起形成後、剥離し易いもので
あるとともにある程度の強度を有しておらねばならない
However, the metal film must be easily peeled off after the metal protrusions are formed and must have a certain degree of strength.

この条件を満足するように均衡をとることは、極めて困
難である。
It is extremely difficult to strike a balance that satisfies this condition.

また、金属突起の形成はフォトリソグラフィの複雑な工
程、すなわち洗浄〜蒸着〜レジスト塗布〜マスクパター
ン形成〜現像という一連の工程によらねばならないため
、なおさら面倒になる。
Furthermore, the formation of the metal protrusions is even more troublesome because it requires a series of complicated steps of photolithography, ie, cleaning, vapor deposition, resist coating, mask pattern formation, and development.

以上のように、原理的あるいは実験的には利用可能であ
っても、量産に実地に応用する上では極めて問題が多い
As described above, even if it is possible to use it in principle or experimentally, there are many problems when it comes to practical application in mass production.

一方、特開昭61−94330号公報記載の発明では、
バンブを印刷等の方法で回路基板上に形成し、更にこの
ハンプ上の極小範囲に導電性樹脂を少量形成せねばなら
ない。
On the other hand, in the invention described in JP-A No. 61-94330,
The bump must be formed on the circuit board by a method such as printing, and a small amount of conductive resin must be formed in a very small area on the hump.

つまり、この方法を利用すれば、 5)二つの印刷を重ねて正確に行なうことが必須要件に
なるが、これは現状では、印刷技術的に極めて困難な課
題である。
In other words, if this method is used, 5) It is essential to accurately perform two printings overlapping each other, which is currently an extremely difficult problem in terms of printing technology.

本発明は、以上述べてきた類似の公知例の欠点1)〜5
)すべての克服を課題としている。
The present invention addresses disadvantages 1) to 5 of the similar known examples described above.
) The challenge is to overcome all of them.

すなわち、フリップチップ実装の有している最大の利点
としてすでに述べてきた「省スペース、高密度な実装を
、能率よく可能ならしめる。」という点を承継した上で
、従来利用できなかった大多数の半導体チップを利用し
た技術的容易なフェースダウンボンディングを、電気的
接続の信顛性を向上させつつ実現しようとするものであ
る。
In other words, in addition to inheriting the point that flip-chip mounting has already mentioned as its greatest advantage, ``space-saving, high-density mounting is possible efficiently,'' it also has the ability to The aim is to realize technically easy face-down bonding using semiconductor chips while improving the reliability of electrical connections.

〔課題を解決するための手段〕[Means to solve the problem]

第1図(a)〜(d)参照。 See FIGS. 1(a) to (d).

このような課題を解決するために、半導体チップ7を載
置するための耐熱絶縁基板1の表面に設けた該半導体チ
ップ7との接続用金属パターン22表面に、樹脂ペース
ト3を印刷形成する工程と、該樹脂ペースト3を未硬化
としたまま、金属球4を該樹脂ペースト3に付着固定さ
せる工程と、該樹脂ペースト3を硬化させた後、該半導
体チップ7の接続用電極パッド21面を該耐熱絶縁基板
1の表面に対向させる工程と、 該金属球4の位置と該半導体チップ7の接続用電極バッ
ド21位置とを互いに合わせる工程と、該接続用電極パ
ッド21と該金属球4とを、加圧及び加熱によって互い
に接続する工程と、によって半導体チップ7を実装する
In order to solve this problem, a process of printing and forming a resin paste 3 on the surface of a metal pattern 22 for connection with the semiconductor chip 7 provided on the surface of the heat-resistant insulating substrate 1 on which the semiconductor chip 7 is placed is performed. , a step of adhering and fixing the metal ball 4 to the resin paste 3 while the resin paste 3 remains uncured; and after curing the resin paste 3, the surface of the connection electrode pad 21 of the semiconductor chip 7 is a step of aligning the position of the metal ball 4 with the position of the connection electrode pad 21 of the semiconductor chip 7; and a step of aligning the connection electrode pad 21 and the metal ball 4 with each other. The semiconductor chip 7 is mounted by a step of connecting the two to each other by applying pressure and heating.

[作用〕 本発明では、半導体チップを載置するための耐熱絶縁基
板の表面に設けた該半導体チップとの接続用金属パター
ン上に樹脂ペーストを印刷形成する。
[Operation] In the present invention, a resin paste is printed and formed on a metal pattern for connection with a semiconductor chip provided on the surface of a heat-resistant insulating substrate on which a semiconductor chip is placed.

該樹脂ペースト上に付着した金属球は、後にその高さを
一定とし、更に後には基板面の接続用金属パターンと半
導体チップ側電極パ・ノド両者に直に接触し、加圧及び
加熱によって、金属相互を実質的に接続するものである
The metal balls adhering to the resin paste are later kept at a constant height, and later come into direct contact with both the connection metal pattern on the substrate surface and the electrode pads and nodes on the semiconductor chip side, and are pressed and heated. It essentially connects the metals together.

従って導電性樹脂に起因する接続の問題は解消されるこ
ととなる。
Therefore, connection problems caused by conductive resin can be solved.

一方実際の製造工程を考えても、面倒なフォトリソグラ
フィの工程によらずとも、ハンプの代わりを成す物を極
めて容易に形成でき、しかも、従来の方法の利点を損な
う所がない。
On the other hand, when considering the actual manufacturing process, it is possible to form a substitute for a hump extremely easily without using a complicated photolithography process, and there is no loss in the advantages of the conventional method.

〔実施例] 以下、図面に従って本発明の一実施例について説明する
[Example] An example of the present invention will be described below with reference to the drawings.

第1図(a)参照。See Figure 1(a).

99.5χのアルミナを素材とした耐熱絶縁基板1を用
い、Ta−N抵抗膜、N iCr/^U導体膜を、DC
マグネトロンスパッタにより全面形成する。
Using a heat-resistant insulating substrate 1 made of 99.5χ alumina, a Ta-N resistive film and a NiCr/^U conductive film were coated with DC
The entire surface is formed by magnetron sputtering.

次に、フォトリソプロセスを用いて、Ta−N抵抗膜、
NiCr/Au導体パターンを形成する。この時半導体
装載置される部分は、半導体ペアチ・ノブパターンに対
応した接続用金属パターン22として形成する。
Next, using a photolithography process, a Ta-N resistive film,
Form a NiCr/Au conductor pattern. At this time, the portion on which the semiconductor device is mounted is formed as a connection metal pattern 22 corresponding to the semiconductor pair knob pattern.

第1図(b)参照。See Figure 1(b).

この後、該耐熱絶縁基板1上の半導体チップ7側電極パ
ツド21に接続すべき位置に樹脂ペースト3としてポリ
イミドベースのAg(ill)導電性樹脂ペーストラ3
25メツシユのステンレスマスクを用いて印刷形成する
After this, a polyimide-based Ag(ill) conductive resin paste 3 is applied as a resin paste 3 to the position on the heat-resistant insulating substrate 1 to be connected to the electrode pad 21 on the side of the semiconductor chip 7.
Printing is performed using a 25-mesh stainless steel mask.

第1図(c)参照。See Figure 1(c).

接続部材をなす金属球4には、AI (アルミニウム)
との親和を考え、^U(金)を用いた。
The metal ball 4 forming the connection member is made of AI (aluminum).
I used ^U (gold) in consideration of its affinity with

50〜60μmφのAu (金)を素材として用いた金
属球4を該耐熱絶縁基板1上に散布し導電性樹脂ペース
ト3上に付着させた後、不要な金属球4を揺動落下させ
る。
Metal balls 4 made of Au (gold) with a diameter of 50 to 60 μm are scattered on the heat-resistant insulating substrate 1 and adhered to the conductive resin paste 3, and then unnecessary metal balls 4 are swung and dropped.

金属球4自体の重量は極めて軽いものであり、しかも導
電性樹脂ペースト3の粘度は、多少の揺れで金属球4が
落下しない程度に十分である。
The weight of the metal ball 4 itself is extremely light, and the viscosity of the conductive resin paste 3 is sufficient to prevent the metal ball 4 from falling even with slight shaking.

ゆえに、付着させた金属球4を残しつつ余分な球を除去
することは、揺動の程度で調和をとれば容易に可能であ
る。
Therefore, removing the extra balls while leaving the attached metal balls 4 is easily possible if the degree of rocking is balanced.

また、導電性樹脂ペースト3の印刷面積は、金属球4−
個分しか付着しえない程度に形成が十分可能である。
In addition, the printing area of the conductive resin paste 3 is as follows:
It is possible to form the film to the extent that only individual parts can be attached.

よって、金属球4は必要分だけ所定の位置に付着するこ
ととなる。
Therefore, the required number of metal balls 4 will be attached to a predetermined position.

こうして第1図(c)のようになった該耐熱絶縁基板1
を、金属球4が付着した状態で、導電性樹脂ペースト3
を硬化させるべく150°Cで1時間、300 ’Cで
1時間加熱する。
The heat-resistant insulating substrate 1 thus became as shown in FIG. 1(c).
, with the metal ball 4 attached, conductive resin paste 3
Heat at 150°C for 1 hour and at 300'C for 1 hour to cure.

第2図参照。See Figure 2.

該耐熱絶縁基板1上導電性樹脂ペースト3を用いて付着
した金属球4の高さを一定にするために、平行調整用ツ
ール8により金属球4表面を±5μmの精度で該耐熱絶
縁基板1上の接続用金属パターン22表面と平行調整用
ツール8との接続用電極パッド21との間隔51が約5
0μmになるように加圧する。
In order to make the height of the metal sphere 4 adhered to the heat-resistant insulating substrate 1 using the conductive resin paste 3 constant, the surface of the metal sphere 4 is adjusted to an accuracy of ±5 μm on the heat-resistant insulating substrate 1 using the parallel adjustment tool 8. The distance 51 between the surface of the upper connection metal pattern 22 and the connection electrode pad 21 of the parallel adjustment tool 8 is approximately 5.
Pressure is applied to 0 μm.

第1図(d)、及びその部分拡大図である第3図参照。See FIG. 1(d) and FIG. 3, which is a partially enlarged view thereof.

間隔51が一定となった金属球4の付着した耐熱絶縁基
板工をホットプレート6上で350°C〜400°Cに
加熱する。
A heat-resistant insulating substrate work on which metal balls 4 are attached at constant intervals 51 is heated to 350° C. to 400° C. on a hot plate 6.

一方、圧着ツール5も350°C〜400°Cに加熱し
ておく。
Meanwhile, the crimping tool 5 is also heated to 350°C to 400°C.

該耐熱絶縁基板1面上の接続用金属パターン22と半導
体チップ7側接続用電極パッド21パターンにて両者別
個に位置合わせを行い、位置合わせ終了後に互いに対向
させた耐熱絶縁基板1と半導体チップ7とを、該半導体
チップ7の平行度±5μmを保ったまま、接続用電極パ
ッド21一箇所について100g〜300gの圧力にて
加圧接着する。
The connection metal pattern 22 on the surface of the heat-resistant insulating substrate 1 and the connection electrode pad 21 pattern on the semiconductor chip 7 side are aligned separately, and after the alignment is completed, the heat-resistant insulating substrate 1 and the semiconductor chip 7 are placed facing each other. While maintaining the parallelism of the semiconductor chip 7 by ±5 μm, each connection electrode pad 21 is bonded under pressure of 100 g to 300 g.

以上本発明を実施例により説明したが、本発明の方法に
よれば、バンプを具備せねばフリップチップ実装できな
いという従来法の欠点を克服でき、加えて従来のフリッ
プチップ実装法が有していた利点を何等損なう事もない
上、電気的接続の信頼性も十分に向上できる。
The present invention has been described above with reference to embodiments. According to the method of the present invention, it is possible to overcome the drawback of the conventional method that flip-chip mounting is not possible without providing bumps, and in addition, it is possible to overcome the drawback of the conventional flip-chip mounting method. The advantages are not compromised in any way, and the reliability of the electrical connection can be sufficiently improved.

なお、本発明は本発明の趣旨に従い、特に該金属球4の
付着に関して種々の変形が可能である。
Note that the present invention can be modified in various ways, especially regarding the attachment of the metal balls 4, in accordance with the spirit of the present invention.

例えば、金属球4の材質をAu (金)以外のものとし
でもよいし、樹脂ペースト3として銅ペースト、銀ペー
スト、金ペースト等自由に選んで利用しうる。
For example, the metal ball 4 may be made of a material other than Au (gold), and the resin paste 3 may be freely selected from copper paste, silver paste, gold paste, etc.

さらに、上記実施例では、樹脂ペースト3として導電性
樹脂ペーストを用いたが、本発明はこれに限定されず、
例えば樹脂ペースト3により金属球4が接続用電極パッ
ド21と直に接触することが確実ならば、該樹脂ペース
ト3は絶縁性のペーストを用いてもよい。
Furthermore, in the above embodiment, a conductive resin paste was used as the resin paste 3, but the present invention is not limited to this.
For example, if the resin paste 3 ensures that the metal ball 4 comes into direct contact with the connecting electrode pad 21, an insulating paste may be used as the resin paste 3.

同様に、耐熱絶縁基板1にはガラス等の他の耐熱絶縁素
材を用いてもよい。
Similarly, other heat-resistant insulating materials such as glass may be used for the heat-resistant insulating substrate 1.

また、半導体チップ7の実装に際し、超音波を併用して
も良い。
Further, when mounting the semiconductor chip 7, ultrasonic waves may be used in combination.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、従来のフリップチ
ップ実装を改良しようとした方法に比べて、電気的接続
の信頼性も十分である。
As explained above, according to the present invention, the reliability of electrical connection is also sufficient compared to the method of improving conventional flip-chip mounting.

つまり本発明では、本質的に接続部材をなすのは金属球
であり、樹脂は金属球を付着させる糊料として利用する
にすぎない。
In other words, in the present invention, the metal balls essentially form the connection member, and the resin is merely used as a glue to adhere the metal balls.

よって、導電性樹脂ペーストに起因した電気抵抗や電気
的接続の不具合の問題は解消された。
Therefore, the problems of electrical resistance and electrical connection problems caused by the conductive resin paste have been solved.

また金属球と接続用電極パッド及び接続用金属パターン
とは、加熱と加圧によって金属の拡散を起こさせ本質的
な金属相互の接続を得る構成になっている。
Further, the metal sphere, the connecting electrode pad, and the connecting metal pattern are configured to cause metal diffusion by heating and pressurizing to obtain an essential metal-to-metal connection.

一方、製造工程を見ても、従来例でバンプ、またはその
代わりをなす物を形成するために用いていたフォトリソ
グラフィの複雑な工程、すなわち洗浄〜蒸着〜レジスト
塗布〜マスクパターン形成〜現像という一連の工程は一
切不要となる。
On the other hand, if we look at the manufacturing process, we can see that the complicated photolithography process used in conventional examples to form bumps or their substitutes is a series of cleaning, vapor deposition, resist coating, mask pattern formation, and development. This process is completely unnecessary.

それとともに、バンプを正確に印刷したうえ、さらにバ
ンプ上に正確に導電性樹脂ペーストを印刷しなければな
らないという面倒もない。
At the same time, there is no need to print the bumps accurately and also to print the conductive resin paste accurately on the bumps.

以上考え合わせ、本発明は極めて容易にフェースダウン
ボンディング法による半導体の実装を可能にし、フリッ
プチップ実装の応用範囲が拡大する。
In view of the above considerations, the present invention makes it possible to extremely easily mount semiconductors by the face-down bonding method, thereby expanding the range of applications of flip-chip mounting.

よって製造コスト面でも利益が大きい。Therefore, there is a large profit in terms of manufacturing costs.

しかも従来使用できなかった大多数の半導体チップが従
来法の利点を損なうことなくまた、同等特別な事前処理
を施さすとも容易な製造工程を通じて利用できることど
なった。
Moreover, a large number of semiconductor chips that could not be used in the past can now be used through an easy manufacturing process without sacrificing the advantages of the conventional method and with equivalent special pretreatment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(d)は、本発明の実施例に則した工程
説明図(側面図)、 第2図は、平行調整工程の拡大説明図(側面図)、 第3図は、基板と半導体チップとの接続部の拡大説明図
(側面図)、 第4図(a)〜(b)は、ワイヤボンディング実装法の
説明図(上面図(a)及び側面図(b))、第5図(a
)〜(b)は、フリップチップ実装法の説明図(上面図
(a)及び側面図(b))である。 耐熱絶縁基板 接続用電極パッド 接続用金属パターン 樹脂ペースト(4電性) 金属球 ボンディングワイヤ バンプ(接続用金属突起) 圧着ツール ホットプレート 半導体チップ 平行調整用ツール 実装エリア である。 ビl 往leWg電オ如マーノド 67r−ブトプレート 7、+導4本ナヴア 千竹匪贅工程−拡欠説明図 (イvIl1図) 早 図 基才反と午埠ホ拳、テップと、才饗縫郡(4劉面図)茅 デ 去y陀工、リア ワイヤホ゛ンディング濱装法nil明(上面図(σ)と
41道1δ(bす茅 図
Figures 1 (a) to (d) are process explanatory diagrams (side views) according to embodiments of the present invention, Figure 2 is an enlarged explanatory diagram (side view) of the parallel adjustment process, and Figure 3 is: An enlarged explanatory diagram (side view) of the connection part between the substrate and the semiconductor chip, FIGS. 4(a) and 4(b) are explanatory diagrams of the wire bonding mounting method (top view (a) and side view (b)), Figure 5 (a
) to (b) are explanatory diagrams (top view (a) and side view (b)) of the flip-chip mounting method. Metal pattern resin paste for connecting electrode pads for connecting heat-resistant insulated substrates (4-electroconductivity) Metal ball bonding wire bumps (metal protrusions for connection) Crimping tool hot plate Semiconductor chip parallel adjustment tool mounting area. Bill OleWg Den Oyomanodo 67r-Butoplate 7, +4 conductors Navua Chichiku Ibo process-enlarged explanatory diagram (IvIl1 figure) Quick drawing Kisaihan and Ubo Hoken, Tep and Saiju Nuigun (4 Liumian map) Rear wire binding method nil light (top view (σ) and 41 road 1δ (b grass map)

Claims (1)

【特許請求の範囲】 接続用電極パッド(21)を有する半導体チップ(7)
を、耐熱絶縁基板(1)の表面に、フェースダウンで直
接載置する実装方法において、 半導体チップ(7)を載置するための耐熱絶縁基板(1
)の表面に設けた該半導体チップ(7)との接続用金属
パターン(22)表面に、樹脂ペースト(3)を印刷形
成する工程と、 該樹脂ペースト(3)を未硬化としたまま、金属球(4
)を該樹脂ペースト(3)に付着固定させる工程と、 該樹脂ペースト(3)を硬化させた後、該半導体チップ
(7)の接続用電極パッド(21)面を該耐熱絶縁基板
(1)の表面に対向させる工程と、 該金属球(4)の位置と該半導体チップ(7)の接続用
電極パッド(21)位置とを互いに合わせる工程と、 該接続用電極パッド(21)と該金属球(4)とを、加
圧及び加熱によって互いに接続する工程と、を有する半
導体チップ(7)の実装方法。
[Claims] Semiconductor chip (7) having a connection electrode pad (21)
In a mounting method in which the semiconductor chip (7) is placed directly on the surface of the heat-resistant insulating substrate (1) face-down, the heat-resistant insulating substrate (1)
) a step of printing and forming a resin paste (3) on the surface of a metal pattern (22) for connection with the semiconductor chip (7) provided on the surface of the semiconductor chip (7); Ball (4
) to the resin paste (3), and after curing the resin paste (3), the connecting electrode pad (21) surface of the semiconductor chip (7) is attached to the heat-resistant insulating substrate (1). a step of aligning the position of the metal ball (4) and the position of the connection electrode pad (21) of the semiconductor chip (7) with each other; A method for mounting a semiconductor chip (7), comprising the step of connecting the spheres (4) to each other by applying pressure and heating.
JP63142181A 1988-06-09 1988-06-09 Semiconductor chip mounting method Expired - Lifetime JP2541284B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63142181A JP2541284B2 (en) 1988-06-09 1988-06-09 Semiconductor chip mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63142181A JP2541284B2 (en) 1988-06-09 1988-06-09 Semiconductor chip mounting method

Publications (2)

Publication Number Publication Date
JPH0228340A true JPH0228340A (en) 1990-01-30
JP2541284B2 JP2541284B2 (en) 1996-10-09

Family

ID=15309259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63142181A Expired - Lifetime JP2541284B2 (en) 1988-06-09 1988-06-09 Semiconductor chip mounting method

Country Status (1)

Country Link
JP (1) JP2541284B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997033313A1 (en) * 1996-03-06 1997-09-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device and process for producing the same
US6103551A (en) * 1996-03-06 2000-08-15 Matsushita Electric Industrial Co., Ltd. Semiconductor unit and method for manufacturing the same
US7363704B2 (en) 2004-07-15 2008-04-29 Fujitsu Limited RFID tag and method of manufacturing RFID tag

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154746A (en) * 1985-12-27 1987-07-09 Casio Comput Co Ltd Bonding method for electronic part

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154746A (en) * 1985-12-27 1987-07-09 Casio Comput Co Ltd Bonding method for electronic part

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997033313A1 (en) * 1996-03-06 1997-09-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device and process for producing the same
US6103551A (en) * 1996-03-06 2000-08-15 Matsushita Electric Industrial Co., Ltd. Semiconductor unit and method for manufacturing the same
US6452280B1 (en) 1996-03-06 2002-09-17 Matsushita Electric Industrial Co., Ltd. Flip chip semiconductor apparatus with projecting electrodes and method for producing same
US7363704B2 (en) 2004-07-15 2008-04-29 Fujitsu Limited RFID tag and method of manufacturing RFID tag

Also Published As

Publication number Publication date
JP2541284B2 (en) 1996-10-09

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