JPH0521519A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0521519A
JPH0521519A JP3175113A JP17511391A JPH0521519A JP H0521519 A JPH0521519 A JP H0521519A JP 3175113 A JP3175113 A JP 3175113A JP 17511391 A JP17511391 A JP 17511391A JP H0521519 A JPH0521519 A JP H0521519A
Authority
JP
Japan
Prior art keywords
electrodes
chip
substrate
wiring
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3175113A
Other languages
Japanese (ja)
Inventor
Hisashi Shin
久司 新
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP3175113A priority Critical patent/JPH0521519A/en
Priority to DE4223280A priority patent/DE4223280A1/en
Publication of JPH0521519A publication Critical patent/JPH0521519A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29399—Coating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0212—Resin particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0215—Metallic fillers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the occurrence of defective connection in an electrode section and, at the same time, to lower the electric resistance value of an inter- electrode section by providing stress absorbing members which absorb stresses caused by the difference in coefficient of linear expansion between the first and second substrates between the electrodes and wiring. CONSTITUTION:This semiconductor device 1 has a semiconductor chip 3 and wiring board 5. An electronic circuit which is connected with chip electrodes 7 is formed on the chip 3 and the wiring formed on the substrate 5 is connected with substrate electrodes 11. Stress absorbing balls 13 are formed by plating high polymer balls formed by polymerizing styrene, divinylbenzene, etc., with Pb-Sn eutectic solder 19. Since the balls 15 absorb stresses even when the stresses are produced, the connection between the chip electrodes and substrate electrodes does not become defective. In addition, since the solder 19 and parent solder metal of the electrodes 7 and 11 are connected to each other by diffused junction, the electric resistance of the connecting sections between the chip electrodes 7 and substrate electrodes 11 can be lowered.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は半導体装置に関するも
のであり、特にフェイスダウンボンディングによって接
続されている部品を有する半導体装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having parts connected by face down bonding.

【０００２】[0002]

【従来の技術】従来、各種の配線基板上に半導体ベアチ
ップを搭載する技術としてＩＢＭ社によって開発された
ハンダバンプを用いたものがよく知られている（いわゆ
るＣ４接続法、Ｐ．Ａ．Ｔｏｔｔａ ａｎｄ Ｒ．Ｐ．
Ｓｏｐｈｅｒ：ＩＢＭ Ｊｏｕｒｎａｌ ｏｆ Ｒｅｓ
ｅａｒｃｈ ａｎｄ Ｄｅｖｅｌｏｐｍｅｎｔ，Ｖｏ
ｌ．１３（１９６９）ｐ．２２６）。この技術を図３を
用いて説明する。2. Description of the Related Art Conventionally, as a technique for mounting a semiconductor bare chip on various wiring substrates, a technique using a solder bump developed by IBM Corporation is well known (so-called C4 connection method, PA Total and R. P.
Sopher: IBM Journal of Res
search and Development, Vo
l. 13 (1969) p. 226). This technique will be described with reference to FIG.

【０００３】半導体装置１は半導体チップ３と配線基板
５とを備えている。半導体チップ３には電子回路が形成
されており、この電子回路はチップ電極７と接続されて
いる。配線基板５には配線が形成されており、この配線
は基板電極１１と接続されている。The semiconductor device 1 comprises a semiconductor chip 3 and a wiring board 5. An electronic circuit is formed on the semiconductor chip 3, and this electronic circuit is connected to the chip electrode 7. Wirings are formed on the wiring board 5, and the wirings are connected to the board electrodes 11.

【０００４】チップ電極７と基板電極１１とはハンダバ
ンプ９によって接続されている。すなわち、半導体チッ
プ３は配線基板５にフェイスダウンボンディングによっ
て接続されている。The chip electrode 7 and the substrate electrode 11 are connected by a solder bump 9. That is, the semiconductor chip 3 is connected to the wiring board 5 by face down bonding.

【０００５】しかし、この技術では温度変化が激しい条
件下で使用した場合、チップ電極７と基板電極１１との
接続が不良になることが多い。すなわち、半導体チップ
３、配線基板５、ハンダバンプ９それぞれの線膨張係数
やヤング率の差に起因する熱応力のため、ハンダバンプ
９が破損したり、ハンダバンプ９と電極７、１１との接
続が外れることがあるのである。However, in this technique, the connection between the chip electrode 7 and the substrate electrode 11 often becomes defective when used under conditions where the temperature changes drastically. That is, the solder bump 9 may be damaged or the connection between the solder bump 9 and the electrodes 7 and 11 may be lost due to the thermal stress caused by the difference in the coefficient of linear expansion and the Young's modulus of the semiconductor chip 3, the wiring board 5, and the solder bump 9. There is.

【０００６】この欠点を解決する１つの技術として、半
導体チップ３と配線基板５との界面にハンダバンプ９と
ほぼ等しい線膨張係数をもつエポキシ樹脂を封入するこ
とが考えられる。このようにすれば熱応力はハンダバン
プ９とエポキシ樹脂とに作用するので、ハンダバンプ９
に作用する熱応力が小さくなる。しかし、このようなエ
ポキシ樹脂を開発する期間や材料コストの点で不利であ
る。As one technique for solving this drawback, it is conceivable to encapsulate epoxy resin having a linear expansion coefficient substantially equal to that of the solder bump 9 at the interface between the semiconductor chip 3 and the wiring board 5. In this way, the thermal stress acts on the solder bumps 9 and the epoxy resin, so that the solder bumps 9
The thermal stress acting on is reduced. However, it is disadvantageous in terms of the period for developing such an epoxy resin and the material cost.

【０００７】接続が不良になるという欠点を解消する他
の技術として、Ｍ．Ｍａｓｕｄａｅｔ ａｌ：Ｐｒｏｃ
ｅｅｄｉｎｇｓ ｏｆ １９８９ Ｉｎｔｅｒｎａｔｉ
ｏｎａｌ Ｅｌｅｃｔｒｏｎｉｃｓ Ｍａｎｕｆａｃｔ
ｕｒｉｎｇ Ｔｅｃｈｎｏｌｏｇｙ Ｓｙｍｐｏｓｉｕ
ｍ（１９８９）ｐ．５７がある。この技術を図４、図５
を用いて説明する。As another technique for solving the drawback of poor connection, M. Masuda et al: Proc
needs of 1989 Internet
onal Electronics Manufact
uring Technology Symposium
m (1989) p. There is 57. This technique is shown in FIGS.
Will be explained.

【０００８】この技術はチップ電極７と基板電極１１と
の間に応力吸収球１３を介在させている。応力吸収球１
３は図５に示すように、弾性を有する高分子球１５の表
面にＡｕメッキ１７を施したものである。熱応力が発生
しても高分子球１５が吸収してくれるので、チップ電極
７と基板電極１１との接続が不良になることはない。In this technique, a stress absorbing sphere 13 is interposed between the chip electrode 7 and the substrate electrode 11. Stress absorbing sphere 1
As shown in FIG. 5, 3 is an elastic polymer ball 15 with Au plating 17 applied on its surface. Even if thermal stress occurs, the polymer spheres 15 absorb it, so that the connection between the chip electrode 7 and the substrate electrode 11 does not become defective.

【０００９】[0009]

【発明が解決しようとする課題】しかし、図４に示す技
術は応力吸収球１３と電極７、１１とを接着剤で加圧接
触させているだけなので、接続部の電気抵抗値が０．１
〜１Ωと大きくなる欠点を有している。However, in the technique shown in FIG. 4, the stress absorbing sphere 13 and the electrodes 7 and 11 are only brought into pressure contact with each other with an adhesive, so that the electric resistance value of the connecting portion is 0.1.
It has a drawback that it becomes as large as ~ 1Ω.

【００１０】この発明は係る従来の問題点を解決するた
めになされたものである。この発明の目的は、熱応力が
原因で電極部の接続が不良になることなく、かつ電極間
部の電気抵抗値を下げることができる半導体装置を提供
することである。The present invention has been made to solve the above conventional problems. An object of the present invention is to provide a semiconductor device capable of reducing the electric resistance value between the electrodes without causing a defective connection of the electrode parts due to thermal stress.

【００１１】[0011]

【課題を解決するための手段】この発明に従った半導体
装置はフェイスダウンボンディングによって接続されて
いる部品を有する半導体装置であって、電子回路および
電子回路と接続した電極が形成された第１基板と、配線
が形成された第２基板と、電極と配線との間に位置し、
第１基板の線膨張係数と第２基板の線膨張係数との差が
原因で生じる応力を吸収する応力吸収部材と、を備えて
いる。応力吸収部材は表面に導電部材を有し、導電部材
は電極および配線と拡散接合している。A semiconductor device according to the present invention is a semiconductor device having components connected by face-down bonding, and a first substrate on which an electronic circuit and an electrode connected to the electronic circuit are formed. And a second substrate on which wiring is formed, and is located between the electrode and the wiring,
And a stress absorbing member that absorbs stress caused by the difference between the linear expansion coefficient of the first substrate and the linear expansion coefficient of the second substrate. The stress absorbing member has a conductive member on its surface, and the conductive member is diffusion-bonded to the electrode and the wiring.

【００１２】[0012]

【作用】この発明に従った半導体装置は、電極と配線と
の間に第１基板の線膨張係数と第２基板の線膨張係数と
の差が原因で生じる応力を吸収する応力吸収部材があ
る。このため電極と配線との接続部に熱応力が作用して
も応力吸収部材が熱応力を吸収するので、接続が不良に
なることはない。In the semiconductor device according to the present invention, there is a stress absorbing member between the electrode and the wiring, which absorbs the stress caused by the difference between the linear expansion coefficient of the first substrate and the linear expansion coefficient of the second substrate. . For this reason, even if thermal stress acts on the connection portion between the electrode and the wiring, the stress absorbing member absorbs the thermal stress, so that the connection does not become defective.

【００１３】また、応力吸収部材は表面に導電部材を有
し、導電部材は電極および配線と拡散接合しているの
で、第１，第２基板を接着剤で加圧接触させる場合に比
べ接続部の電気抵抗を下げることができる。Further, since the stress absorbing member has a conductive member on its surface, and the conductive member is diffusion-bonded to the electrodes and wirings, the connecting portion is different from the case where the first and second substrates are pressure-contacted with an adhesive. The electric resistance of can be reduced.

【００１４】なお、ここでいう第２基板には電子回路を
形成した基板および配線回路を形成した基板が含まれ
る。また、配線には電極も含まれる。The second substrate mentioned here includes a substrate on which an electronic circuit is formed and a substrate on which a wiring circuit is formed. The wiring also includes electrodes.

【００１５】[0015]

【実施例】図１はこの発明に従った半導体装置の一実施
例の断面図である。半導体装置１は半導体チップ３と配
線基板５とを備えている。半導体チップ３には電子回路
が形成されており、この電子回路はチップ電極７と接続
されている。配線基板５には配線が形成されており、こ
の配線は基板電極１１と接続されている。1 is a sectional view of an embodiment of a semiconductor device according to the present invention. The semiconductor device 1 includes a semiconductor chip 3 and a wiring board 5. An electronic circuit is formed on the semiconductor chip 3, and this electronic circuit is connected to the chip electrode 7. Wirings are formed on the wiring board 5, and the wirings are connected to the board electrodes 11.

【００１６】チップ電極７は最表層から順にＡｕ、Ｃ
ｕ、Ｎｉなどの親ハンダ金属層、Ｔｉ−Ｗ、Ｔｉ、Ｃｒ
のなどの拡散防止金属層、Ａｌ−Ｓｉ、Ａｌ−Ｓｉ−Ｃ
ｕなどの金属層からなる。金属層が半導体チップ３に形
成された配線層と接続している。拡散防止金属層は、親
ハンダ金属層中の原子が電子回路に拡散するのを防ぐ層
である。基板電極１１はＡｕ、Ｃｕ、Ｎｉなどの親ハン
ダ金属である。親ハンダ金属で配線が構成されている。
配線基板５には電子回路が形成されていないので拡散防
止金属層は形成されていない。The tip electrode 7 is composed of Au and C in order from the outermost layer.
u, Ni or other parent solder metal layer, Ti-W, Ti, Cr
Diffusion preventing metal layer such as Al, Si, Al-Si-C
It consists of a metal layer such as u. The metal layer is connected to the wiring layer formed on the semiconductor chip 3. The diffusion preventing metal layer is a layer that prevents atoms in the parent solder metal layer from diffusing into the electronic circuit. The substrate electrode 11 is a parent solder metal such as Au, Cu or Ni. Wiring is composed of parent solder metal.
Since no electronic circuit is formed on the wiring board 5, no diffusion preventing metal layer is formed.

【００１７】応力吸収球１３は図２に示すようにスチレ
ンやジビニルベンゼンなどを重合させた高分子球１５の
表面にＰｂ−Ｓｎ共晶ハンダ１９をメッキしたものであ
る。ハンダのメッキ方法としては、たとえば河内他：第
５回プリント回路学会学術講演会論文集に記載されてい
る。熱応力が発生しても高分子球１５が吸収してくれる
のでチップ電極７と基板電極１１との接続が不良になる
ことはない。As shown in FIG. 2, the stress absorbing spheres 13 are polymer spheres 15 obtained by polymerizing styrene, divinylbenzene or the like, and Pb--Sn eutectic solder 19 is plated on the surface of the polymer spheres 15. The solder plating method is described in, for example, Kawachi et al .: Proc. Even if thermal stress is generated, the polymer spheres 15 absorb the thermal stress so that the connection between the chip electrode 7 and the substrate electrode 11 does not become defective.

【００１８】Ｐｂ−Ｓｎ共晶ハンダ１９と電極７、１１
の親ハンダ金属とが拡散接合している。したがって、チ
ップ電極７と基板電極１１との接続部の電気抵抗を下げ
ることができる。ハンダの材料によって電極７、１１の
親ハンダ金属を変える必要がある。表１はハイブリッド
マイクロエレクトロニクス用材料すなわちここでいう親
ハンダ金属とハンダの成分元素との関係を示すものであ
る。表の縦の金属と表の横の金属との組合わせのうち、
合金組成の記載がある組合わせを用いる。この表は、ハ
イブリッドマイクロエレクトロニクス協会（編集）：
「ハイブリッドマイクロエレクトロニクスハンドブッ
ク」（１９８９・工業調査会）ｐ．７９０から引用した
ものである。Pb--Sn eutectic solder 19 and electrodes 7, 11
It is diffusion-bonded to its parent solder metal. Therefore, the electrical resistance of the connecting portion between the chip electrode 7 and the substrate electrode 11 can be reduced. It is necessary to change the parent solder metal of the electrodes 7 and 11 depending on the material of the solder. Table 1 shows the relationship between the materials for hybrid microelectronics, that is, the parent solder metal and the constituent elements of the solder. Of the combination of the vertical metal of the table and the horizontal metal of the table,
Use the combination with the description of alloy composition. This table is edited by the Hybrid Microelectronics Association:
"Hybrid Microelectronics Handbook" (1989, Industrial Research Board) p. It is quoted from 790.

【００１９】[0019]

【表１】 [Table 1]

【００２０】応力吸収球１３は基板電極１１またはチッ
プ電極７上に配置する必要があるが、応力吸収球１３を
半導体チップ３のうちチップ電極７上に選択的に配置す
る技術として、たとえば次の３つがある。回路基板５の
うち基板電極１１上に選択的に配置する場合も同じであ
る。The stress absorbing sphere 13 needs to be arranged on the substrate electrode 11 or the chip electrode 7, but as a technique for selectively arranging the stress absorbing sphere 13 on the chip electrode 7 of the semiconductor chip 3, for example, the following is adopted. There are three. The same applies to the case where the circuit board 5 is selectively arranged on the substrate electrode 11.

【００２１】 先に従来例で挙げたＭ．Ｍａｓｕｄａ
ｅｔ ａｌ：Ｐｒｏｃｅｅｄｉｎｇｓ ｏｆ １９８
９ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｅｌｅｃｔｒｏｎｉ
ｃｓＭａｎｕｆａｃｔｕｒｉｎｇ Ｔｅｃｈｎｏｌｏｇ
ｙ Ｓｙｍｐｏｓｉｕｍ（１９８９）ｐ．５７に示され
ているように熱硬化性樹脂や光硬化性樹脂の中に応力吸
収球１３を混ぜたものを印刷法によって電極１１上にだ
け供給する。この場合、熱硬化性樹脂あるいは光硬化性
樹脂は半導体チップ３と配線基板５との界面の封止の役
割もする。[0021] The M. Masuda
et al: Proceedings of 198
9 International Electroni
csManufacturing Technology
y Symposium (1989) p. As shown in 57, a mixture of a thermosetting resin or a photocurable resin with the stress absorbing spheres 13 is supplied only onto the electrodes 11 by a printing method. In this case, the thermosetting resin or the photocurable resin also plays a role of sealing the interface between the semiconductor chip 3 and the wiring board 5.

【００２２】 特開平０１−２２７４４４，特開平０
２−２３６２３に示されているように、予め半導体ウエ
ハの表面に塗布した応力吸収球１３の直径よりも薄い膜
厚の光硬化性樹脂層にマスク露光を施し、照射部と非照
射部とへの光硬化性樹脂の粘着力の差を利用してチップ
電極７上にだけ応力吸収球１３を供給する。この場合、
光硬化性樹脂は半導体チップ３と配線基板５との界面の
封止の役割もする。JP-A-01-227444, JP-A-0
2-23623, the photo-curable resin layer having a film thickness smaller than the diameter of the stress absorbing sphere 13 previously applied to the surface of the semiconductor wafer is subjected to mask exposure to expose the irradiated portion and the non-irradiated portion. The stress absorbing spheres 13 are supplied only on the chip electrodes 7 by utilizing the difference in the adhesive force of the photocurable resin. in this case,
The photocurable resin also plays a role of sealing the interface between the semiconductor chip 3 and the wiring board 5.

【００２３】 Ｍ．Ｋｉｎｏｓｈｉｔａ ｅｔ ａ
ｌ：Ｐｒｏｃｅｅｄｉｎｇｓ ｏｆｔｈｅ ６ｔｈ Ｉ
ｎｔｅｒｎａｔｉｏｎａｌ Ｍｉｃｒｏｅｌｅｃｔｒｏ
ｎｉｃｓ Ｓｙｍｐｏｓｉｕｍ（１９９０）ｐ．２４３
に示されているようにメタルマスクを用いてチップ電極
７上だけに応力吸収球１３を供給する。M. Kinoshita et a
l: Proceedings of the 6th I
international Microelectro
nics Symposium (1990) p. 243
The stress absorbing spheres 13 are supplied only on the chip electrodes 7 by using a metal mask as shown in FIG.

【００２４】たとえば直径８０μｍの電極をもつ半導体
チップ３にの方法を採用して直径１０μｍの応力吸収
球１３をチップ電極７上に配置した場合、約３０〜４０
個の応力吸収球１３を配置することができた。この半導
体チップ３と配線基板５とをフリップチップボンダーに
より加圧・加熱接続すると図１に示す半導体装置１が得
られた。加圧・加熱条件は、２００個のチップ電極７を
もつ１３ｍｍ×６ｍｍの半導体チップ３の場合、６Ｋｇ
ｆ、２００℃で適当である。For example, when the method for the semiconductor chip 3 having an electrode having a diameter of 80 μm is adopted and the stress absorbing sphere 13 having a diameter of 10 μm is arranged on the chip electrode 7, it is about 30-40.
It was possible to arrange the individual stress absorbing spheres 13. When the semiconductor chip 3 and the wiring board 5 are pressure-heated and connected by a flip chip bonder, the semiconductor device 1 shown in FIG. 1 is obtained. Pressurization / heating conditions are 6 kg for a 13 mm × 6 mm semiconductor chip 3 having 200 chip electrodes 7.
f, 200 ° C is suitable.

【００２５】この実施例では配線基板に半導体チップを
フェイスダウンボンディングによって接続していれば、
半導体チップ同士をフェイスダウンボンディングによっ
て接続してもよい。In this embodiment, if the semiconductor chip is connected to the wiring board by face down bonding,
The semiconductor chips may be connected to each other by face down bonding.

【００２６】また、高分子球は任意の大きさにできるの
で、電極とほぼ同じ大きさの高分子球も用いることがで
きる。Further, since the polymer spheres can have any size, polymer spheres having substantially the same size as the electrodes can also be used.

【００２７】さらに、高分子球はその重合度を変えるこ
とにより弾性係数を変えることができるので、ボンディ
ング時に必要な加圧力に応じて最適なる弾性係数をもつ
高分子球を採用すればよい。Further, since the elastic coefficient of the polymer sphere can be changed by changing the degree of polymerization, the polymer sphere having the optimum elastic coefficient according to the pressing force required at the time of bonding may be adopted.

【００２８】この実施例では応力吸収球は球状している
が、熱応力を吸収でき、かつ拡散接合できるものであれ
ばいかなる形状でもよい。Although the stress absorbing sphere is spherical in this embodiment, it may have any shape as long as it can absorb thermal stress and can be diffusion bonded.

【００２９】この実施例では、電極７，１１間に介在さ
せた材料を球形としたが、これ以外の形状でも機能が満
たされれば何ら問題はない。In this embodiment, the material interposed between the electrodes 7 and 11 has a spherical shape, but other shapes can be used as long as the function is satisfied.

【００３０】この実施例では応力吸収球は高分子球とＰ
ｂ−Ｓｎ共晶ハンダからなるが、電極と拡散接合し、か
つ熱応力を吸収できれば１つの材料でもよい。In this embodiment, the stress absorbing spheres are polymer spheres and P
Although it is made of b-Sn eutectic solder, one material may be used as long as it can be diffusion-bonded to the electrode and can absorb thermal stress.

【００３１】[0031]

【発明の効果】以上説明したようにこの発明によれば、
フェイスダウンボンディングによって接続されている接
続部を有する半導体装置であっても、熱応力によって接
続部の接続が不良となったりすることはない。また、接
続部の電気抵抗を下げることができる。As described above, according to the present invention,
Even in a semiconductor device having a connection part connected by face-down bonding, the connection of the connection part does not become defective due to thermal stress. Moreover, the electrical resistance of the connection portion can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明に従った半導体装置の一実施例の断面
図である。FIG. 1 is a sectional view of an embodiment of a semiconductor device according to the present invention.

【図２】この発明に従った半導体装置の一実施例に使わ
れる応力吸収球の断面図である。FIG. 2 is a sectional view of a stress absorbing sphere used in an embodiment of a semiconductor device according to the present invention.

【図３】従来の半導体装置の一例の断面図である。FIG. 3 is a cross-sectional view of an example of a conventional semiconductor device.

【図４】従来の半導体装置の他の例の断面図である。FIG. 4 is a cross-sectional view of another example of a conventional semiconductor device.

【図５】従来の半導体装置の他の例に使われる応力吸収
球の斜視図である。FIG. 5 is a perspective view of a stress absorbing sphere used in another example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 半導体装置 ３ 半導体チップ ５ 配線基板 ７ チップ電極 １１ 基板電極 １３ 応力吸収球 1 Semiconductor Device 3 Semiconductor Chip 5 Wiring Board 7 Chip Electrode 11 Substrate Electrode 13 Stress Absorbing Sphere

Claims (1)

【特許請求の範囲】 【請求項１】 フェイスダウンボンディングによって接
続されている部品を有する半導体装置であって、 電子回路および前記電子回路と接続した電極が形成され
た第１基板と、 配線が形成された第２基板と、 前記電極と前記配線との間に位置し、前記第１基板の線
膨張係数と前記第２基板の線膨張係数との差が原因で生
じる応力を吸収する応力吸収部材と、を備え、前記応力
吸収部材は表面に導電部材を有し、 前記導電部材は前記電極および前記配線と拡散接合して
いる半導体装置。Claim: What is claimed is: 1. A semiconductor device having components connected by face-down bonding, comprising: a first substrate on which an electronic circuit and an electrode connected to the electronic circuit are formed; and a wiring. And a stress absorbing member that is located between the electrode and the wiring and that absorbs stress caused by the difference between the linear expansion coefficient of the first substrate and the linear expansion coefficient of the second substrate. And the stress absorbing member has a conductive member on its surface, and the conductive member is diffusion bonded to the electrode and the wiring.
JP3175113A 1991-07-16 1991-07-16 Semiconductor device Withdrawn JPH0521519A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3175113A JPH0521519A (en) 1991-07-16 1991-07-16 Semiconductor device
DE4223280A DE4223280A1 (en) 1991-07-16 1992-07-15 Switching circuit carrier component - comprising appts. arranged between electrodes of two carriers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3175113A JPH0521519A (en) 1991-07-16 1991-07-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0521519A true JPH0521519A (en) 1993-01-29

Family

ID=15990503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3175113A Withdrawn JPH0521519A (en) 1991-07-16 1991-07-16 Semiconductor device

Country Status (2)

Country Link
JP (1) JPH0521519A (en)
DE (1) DE4223280A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100349896B1 (en) * 1994-12-28 2002-12-26 삼성에스디아이 주식회사 Mounting structure of ic and mounting method thereof
KR100376044B1 (en) * 1999-05-13 2003-03-15 한오근 Solder of semiconductor package and semiconductor package utilizing thereof
US8120188B2 (en) 2006-11-28 2012-02-21 Panasonic Corporation Electronic component mounting structure and method for manufacturing the same

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2722916A1 (en) * 1994-02-22 1996-01-26 Nec Corp Connection element comprising solder-coated core
US5393697A (en) * 1994-05-06 1995-02-28 Industrial Technology Research Institute Composite bump structure and methods of fabrication
EP0827190A3 (en) * 1994-06-24 1998-09-02 Industrial Technology Research Institute Bump structure and methods for forming this structure
US5578527A (en) * 1995-06-23 1996-11-26 Industrial Technology Research Institute Connection construction and method of manufacturing the same
FR2736569B1 (en) * 1995-07-13 1997-08-08 Thomson Csf CONNECTION DEVICE AND CONNECTION METHOD
FI970822A (en) * 1997-02-27 1998-08-28 Nokia Mobile Phones Ltd Method and arrangement for connecting a component
WO1999049536A1 (en) * 1998-03-24 1999-09-30 Raytheon Company Stacked electrical circuit having an improved interconnect and alignment system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667219A (en) * 1984-04-27 1987-05-19 Trilogy Computer Development Partners, Ltd. Semiconductor chip interface
JPS61173471A (en) * 1985-01-28 1986-08-05 シャープ株式会社 Heat compressed connector
US4902857A (en) * 1988-12-27 1990-02-20 American Telephone And Telegraph Company, At&T Bell Laboratories Polymer interconnect structure
JPH0793342B2 (en) * 1988-12-29 1995-10-09 シャープ株式会社 Method of forming electrodes
JPH0740496B2 (en) * 1989-03-01 1995-05-01 シャープ株式会社 Method of placing conductive particles on electrode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100349896B1 (en) * 1994-12-28 2002-12-26 삼성에스디아이 주식회사 Mounting structure of ic and mounting method thereof
KR100376044B1 (en) * 1999-05-13 2003-03-15 한오근 Solder of semiconductor package and semiconductor package utilizing thereof
US8120188B2 (en) 2006-11-28 2012-02-21 Panasonic Corporation Electronic component mounting structure and method for manufacturing the same

Also Published As

Publication number Publication date
DE4223280A1 (en) 1993-01-21

Similar Documents

Publication Publication Date Title
US5801446A (en) Microelectronic connections with solid core joining units
US6583515B1 (en) Ball grid array package for enhanced stress tolerance
KR100886778B1 (en) Apparatus with compliant electrical terminals, and methods for forming same
US6265775B1 (en) Flip chip technique for chip assembly
JP4698125B2 (en) Flip chip for substrate assembly without bumps and polymer layers
US6696757B2 (en) Contact structure for reliable metallic interconnection
US4902857A (en) Polymer interconnect structure
JP2825083B2 (en) Semiconductor element mounting structure
US7423348B2 (en) Chip structure and chip package structure
KR19990022881A (en) Method of manufacturing semiconductor device, semiconductor mounting wiring board and semiconductor device
JPH09199535A (en) Electrode structure of semiconductor integrated circuit and its package formation
JP3450236B2 (en) Semiconductor device and manufacturing method thereof
JPH09232373A (en) Semiconductor device
KR20030080032A (en) Chip scale package with flip chip interconnect
US20020041037A1 (en) Semiconductor device and process of producing same
US6841884B2 (en) Semiconductor device
JPH0521519A (en) Semiconductor device
JP2000269271A (en) Semiconductor device and manufacture thereof
JP3339881B2 (en) Semiconductor integrated circuit device and method of manufacturing the same
US6649833B1 (en) Negative volume expansion lead-free electrical connection
JPH0666355B2 (en) Semiconductor device mounting body and mounting method thereof
JP4029255B2 (en) Adhesive member
JP3529507B2 (en) Semiconductor device
JP3739632B2 (en) Semiconductor device and manufacturing method thereof
US6831361B2 (en) Flip chip technique for chip assembly

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19981008