JPH02283065A - Manufacture of gate array type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form semiconductor integrated circuits of various sizes and scales from the same base wafer by selecting the size of a circuit in a metallizing step, and forming scribing lines of chips. CONSTITUTION:Gates 12 are formed on the whole surface of a silicon wafer 11 in a diffusing step. The sizes and scales of chips to be formed are not determined at this time point, and no scribing line is formed. When chips 13 are formed, for example, using 12 gates 12 on the wafer 11, wirings, input/output pads, scribing lines 14, etc., are formed with a shaded part as one chip 13 in a metallizing step to form a semiconductor integrated circuit. In this case, the boundary lines of the chip 13, so-called the scribing lines 14 coincide with those of the 12 gates used in the chip 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is utilized for manufacturing gate array type semiconductor integrated circuits, and particularly relates to a method for manufacturing gate array type semiconductor integrated circuits that improves the method for forming chips thereof.

〔overview〕

The present invention provides a method for manufacturing a gate array type semiconductor integrated circuit, in which the size and complexity of the circuit are selected during the metallization step and scribe lines of the chip are formed, thereby improving the design and performance of the circuit. This reduces the restrictions on

[Conventional technology]

An example of a conventional method for manufacturing a gate array type semiconductor integrated circuit is shown in FIGS. 5 and 6. FIG. 5 is a plan view showing a silicon wafer at the time when a so-called diffusion process for forming transistor elements, resistors, etc. has been completed in a conventional example. FIG. 6 is an enlarged view of the chip of FIG. The configuration includes a silicon wafer \11 on which transistor elements and resistors are formed, a gate 12 formed of a combination of transistor elements and resistors, a chip 13, and a scribe line 14.

In the conventional example, as shown in FIGS. 5 and 6, chip boundaries, so-called scribe lines 14, are formed when the diffusion process is completed, and the shape, size, scale, etc. of the chips are determined. There is.

[Problem that the invention seeks to solve]

In the conventional gate array type semiconductor integrated circuit manufacturing method described above, the size and scale of the semiconductor integrated circuit are determined at the stage of forming transistor elements, resistors, etc., and wiring must be performed within that scale. However, there are disadvantages in that the design and performance of semiconductor integrated circuits are limited.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a gate array type semiconductor integrated circuit, which can reduce restrictions on circuit design, performance, etc. by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention relates to a method for manufacturing a gate array type semiconductor integrated circuit, which includes a diffusion process for forming gates composed of combinations of transistors, resistors, etc. in an array over the entire surface of a wafer, and a metallization process for forming interconnections. In the metallization process, the size of the circuit is selected and the scribe lines of the chip are formed.

[Effect]

The present invention uses a base wafer for a gate array in which gates consisting of a combination of transistors, resistors, etc. are formed on the entire surface of a silicon wafer, and the size and scale of the semiconductor integrated circuit are selected in the metallization process for forming wiring. and form scribe lines on the chip.

Therefore, the size of the chip can be freely determined according to the size and scale of the circuit, and restrictions on circuit design, performance, etc. can be relaxed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a silicon wafer after the so-called diffusion process, which is the process of forming transistors, resistors, etc., according to the first embodiment of the present invention. A gate 12 is formed on the entire surface of the silicon wafer 11. At this point, the size and scale of the chip to be completed have not been determined, and scribe lines have not yet been formed.

FIG. 2 shows the gate 12 on the silicon wafer ll of FIG.
FIG. 3 is a plan view showing a chip 13 formed by using 12 pieces of the same. During the metallization process, the shaded area in Figure 2 is
As the second chip 13, wiring, human output pads, scribe lines 14, etc. are formed to constitute a semiconductor integrated circuit.

In the case of this first embodiment, the boundary line of the chip 13, so-called scribe line 14, coincides with the boundary line of the 12 gates used in the chip 13.

FIG. 3 is a plan view showing a silicon wafer after the diffusion process according to the second embodiment of the present invention.

Similar to the first embodiment, a gate 12 is formed on the entire surface of a silicon wafer 11, but the size and shape of the gate are different from the first embodiment. Further, at this point, no scribe lines have been formed, and the size and scale of the chip have not been determined.

FIG. 4 shows the gate 12 on the silicon wafer 11 in FIG.
FIG. 3 is a plan view showing a chip 13 in which a chip 13 is formed using 16 gates and one-half to one-fourth of the surrounding gates. In the metallization process, the shaded area is 1
Wiring as a chip, input/output bad scribe line 14
etc. to configure a semiconductor integrated circuit. In the case of this second embodiment, the boundary line of the chip 13, so-called scribe line 14, and the boundary line of the gate I2 do not coincide with each other, and the scribe line 14 passes through the inside of the gate 12.

〔Effect of the invention〕

As explained above, the present invention uses a base wafer for a gate array in which a combination of transistors, resistors, etc., i.e., gates are formed over the entire surface of a silicon wafer.
By selecting the size and scale of the semiconductor integrated circuit in the metallization process for forming wiring, semiconductor integrated circuits of various sizes and scales can be formed from the same base wafer, and the design and performance of semiconductor integrated circuits can be improved. This has the effect of reducing restrictions such as

[Brief explanation of drawings]

FIG. 1 is a plan view showing a silicon wafer after the diffusion process according to the first embodiment of the present invention. FIG. 2 is a plan view showing an example of a chip formed thereby. FIG. 3 is a plan view showing a silicon wafer after the diffusion process according to the second embodiment of the present invention. FIG. 4 is a plan view showing an example of a chip formed thereby. FIG. 5 is a plan view showing a silicon wafer after completing a conventional diffusion process. FIG. 6 is a plan view showing the chip. 11...Silicon wafer, 12...Game), 13
...Chip, 14...Scribe line.

Claims (1)

[Claims] 1. Manufacture of a gate array type semiconductor integrated circuit including a diffusion process for forming gates composed of combinations of transistors, resistors, etc. in an array over the entire surface of a wafer, and a metallization process for forming wiring. A method for manufacturing a gate array type semiconductor integrated circuit, characterized in that in the metallization step, the size of the circuit is selected and scribe lines of the chip are formed.