JPS60177651A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable to operate a semiconductor integrated circuit device at high speed even when the large scale logic circuit is constituted of a gate array by a method wherein a programmable logic array and the fundamental cells of the gate are integrally formed on the semiconductor substrate. CONSTITUTION:A PLA consisting of an AND circuit 6, an OR circuit 7, an input register 9 and an output register 11, which have been all disposed at the left lower part of a plane whereon fundamental cells 5 have been arranged, is subjected to a patterning. There is no trouble that the number of the PLA is plural pieces. Using this structure as a standard matrix body, a wiring layer on each wiring region 4 is formed and a semiconductor integrated circuit device is completed by connecting each element together. According to such a constitution, even when the circuit is enlarged on a large scale, the control of the circuit is simplified and the circuit can be actuated at high speed. As a result, the integration degree of the circuit can be improved and a large scale circuit can be designed in a short period.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device and a method for manufacturing the same.

It is particularly used in the design of large-scale integrated circuit devices.

[Technical background of the invention and its problems] Gate arrays, which are realized by building user-specified circuits on a diffused semiconductor (e.g., silicon) wafer by changing only the wiring process, are easier to develop than conventional custom LSIs. The conventional device will be described with reference to FIGS. 1 to 4 of the accompanying drawings, which have been widely used in recent years because they can significantly shorten the period and greatly reduce development costs. FIG. 1 is an overall structural diagram of one configuration example of a conventional gate array, and FIG. 2 is a circuit diagram of its basic cell. In addition,
In the following description, the same elements are indicated by the same reference numerals. Input/output cells 3 having input/output pads 2 are regularly arranged around the semiconductor substrate 10, and basic cells 5 are regularly arranged with wiring regions 4 in the column direction in areas other than the periphery of the semiconductor substrate 10. There is.

The basic cell 5 consists of two pairs of PMO8FETs as shown in Figure 2.
It is composed of TRI, TR2 and NMO8FETTRs, TRi.

As described above, the basic cells of the gate array are general-purpose, and 414 functional circuits are formed using standardized elements, resulting in poor element density and element utilization.

For this reason, 1. For example, when constructing a large-scale decoder using a gate array, many wirings are required.
The wiring area becomes large, leading to a decrease in operating speed. In particular, this trend has become more pronounced as large-scale decoders become necessary due to recent improvements in integrated circuit technology.

FIG. 3 is an overall structural diagram of one configuration example of a conventional PLA,
FIG. 4 is a detailed circuit diagram thereof. PLA consists of AND 6 and OR 7.

An input register 9 for manually inputting a signal is connected to the AND plane 6 via a signal line 8, and an input register 9 for manually inputting a signal is connected to the OR plane 7.
An output register 11 for outputting a signal via 0 is connected.

The input register 9 is composed of an inverting and non-inverting superbuffer and a MO8FIET K, and the output register 11 is composed of an inverting superbuffer and a MOSFET. Send the signal from input register 9 (i
input line 12 to AND array 6 and output register 1
The output line 13 from the OR array 7 sending a signal to
It intersects the product term line (product term line) R1-R4 at each grid point. Furthermore, the output line 13 from the OR array 7
The other end and the other end of the product term line R+ to R4 are connected to the power supply vD via MO8Fi/rumor ET for pull-up.
o is supplied. At each lattice point of the human output lines 12, 13 and product term lines R1 to R4 of the array, connection transistors 14 are provided at positions determined by the rational designer, thereby programming the PLA.

The PLA described above is as versatile as a gate array, and is suitable for constructing a combination circuit such as a decoder, multiplexer, comparator, etc. However, PLA has fixed functions and does not have a circuit for configuring a loop.

It is not suitable for configuring sequential logic circuits such as flip-flops and counters. [Object of the Invention] The present invention has been made to overcome the drawbacks of the prior art as described above. An object of the present invention is to provide a semiconductor device that can operate at high speed even when a large logic circuit is constructed, and a method for manufacturing the same.

[A wealth of inventions]

In order to achieve the above object, the present invention provides P
[Embodiments of the Invention] Some aspects of the present invention will be described below with reference to FIGS. 5 to 8 of the accompanying drawings. An example will be explained. FIG. 5 is an overall structural diagram of one embodiment. The lower left corner of the plane where basic cell 5 is placed (1/
A PLA consisting of an AND surface 6, an OR surface 71, and output registers 9 and 11 is provided in a pattern on each of the four and a half surfaces.

Note that the structure of the PLA may be one without the input register 9 or one without the output register 11.

In such cases, it is necessary to implement the function with a gate array. , some simple structures have no OR plane, and ANDA is possible regardless of the presence or absence of OR plane 7.
In some cases, the output 4d from the f-plane 6 is directly input to the basic cell 5 of the gate array.

Further, there is also one in which an output register is provided on the AND plane 6. Furthermore, the position of the PLA is not limited to the lower left part of the Y opening shown in the figure, but may be any position, and there may be a plurality of PLAs.

Using the structure shown in FIG. 5 as a standard base, wiring layers such as A/ are formed in the wiring area 4 in a wiring process near the final process, and each layer is connected to complete the device.

FIG. 6 is a detailed circuit diagram of a part of the A, ND plane 6 of FIG. Inputs a11. of the AND array connected to the manual register 9. Connection transistors 14 are provided at lattice points where the product term lines R8°R4 intersect. The gates of the connection transistors 14 are each connected to the input terminal 12, and one of the sources and drains is connected to a ground line (ground line) 15. However, in the standard matrix stage, the other of the source and drain is not connected to the product term line R4R4 (or the connection transistor 14 itself is not formed). The program of the PLA is determined by which connection transistor 14 is connected to the product term lines R11 and R4.

FIG. 7 is an explanatory diagram of an example of the pattern of the circuit shown in FIG. 6. The input line 12 is composed of a polysilicon layer (may be a two-layer metal Jm), the product term line R4 is composed of an aluminum layer, and the ground 1$315 is composed of a diffusion layer. The connection transistor 14 is formed at the intersection of the input line 12 and the ground line 15, and is connected to the ground? A through hole for connecting the connection transistor 14 to the product term line is formed at the end of fM15.

Using the above as a standard base, in a wiring step near the final step, aluminum m2 shown by diagonal lines is formed to connect the product term line R4 to the through hole connecting to the source or drain of the connection transistor 14.

FIG. 8 is an explanatory diagram of another example of the circuit pattern shown in FIG. 6. At the standard base stage, ground wire 15 and input wire 1
2 do not intersect, and the connection transistor 14 is not formed. Therefore, in the wiring process, the aluminum layer 21 shown with diagonal lines
A is formed to form the connection transistor 14, and a through hole connected to the source or drain of the connection transistor 14 is connected to the product term line R4K by the aluminum layer 21b.

〔Effect of the invention〕

As described above, according to the present invention, the PLA and the basic cells of the gate array are integrated on the semiconductor substrate to form a standard matrix, and a wiring layer is provided to connect each element in the arrangement surface process, so that one circuit is formed. It is possible to provide a semiconductor device and a method for manufacturing the same, which can operate at high speed by reducing circuit constraints even when the scale is increased. In addition, the degree of integration of the C circuit can be improved compared to a device with only gate arrays, and by using a computer to design circuits, large-scale circuits can be constructed in a short period of time without the need for specialized circuit engineers. Figure 1 is an overall structural diagram of an example of the configuration of a conventional gate array.
FIG. 2 is a circuit diagram of the basic cell shown in FIG. 1, and FIG. 3 is an overall structural diagram of an example of a PLA manufactured by Benmai.

4 is a detailed circuit diagram of the configuration example shown in FIG. 3, FIG. 5 is an overall structural diagram of an embodiment of the present invention, and FIG. 6 is a detailed circuit diagram of a part of the embodiment shown in FIG. Circuit diagram: FIG. 7 is an explanatory diagram of an example of the pattern of the circuit shown in FIG.

FIG. 8 is an explanatory diagram of an example of the pattern of the circuit shown in FIG. 6.

1... Semiconductor substrate, 2... Input/output pad, 3...
Input/output cell, 4... Wiring area, Death... Basic cell, 6.
...AND plane, 7...OR plane, 8.10...signal line, 9...input register, 11...output register, 12...input line, 14...connection transistor,
15...Ground wire, 20...Through hole,
21, 21a, 21b--1/l wiring layer.

RI"'-R4...Product term line.

Applicant's agent Kiyoshi Inomata Figure 1 Figure 2 Figure 3 Figure 8

Claims (1)

Claims: A semiconductor device comprising four semiconductor substrates, a PLA formed on the semiconductor substrate, and basic cells of a gate array formed on the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein a plurality of @iJ PLAs are formed on the semiconductor substrate. 3. A semiconductor substrate, a PLA formed as a standard matrix on the semiconductor substrate and basic cells of a gate array, and the PLA
A semiconductor device with wiring +vII connecting LA and basic cells to each other. 4. The semiconductor device according to claim 3, wherein a plurality of PLAs are formed on the semiconductor substrate. 5. The semiconductor device according to claim 3 (4) or 4 (4), wherein the self-arranged layer is in the order of gold. 6. Form basic cells of PLA and gate array on a semiconductor substrate as a standard matrix, and perform the wiring process (~) in step 1.
A method for manufacturing a semiconductor device in which a 5PLA and a basic cell are connected to each other. 7. Form PLA and the basic cells of the gate array on the semiconductor substrate as a standard matrix, and in the wiring process,
Connect LA and base cells randomly and connect the PLA
A method of manufacturing a semiconductor device in which connection transistors are formed at lattice points of an AND array and an OR array.