JPH02279040A - Fault detection system for multi-processor system - Google Patents

Abstract

PURPOSE:To detect the fault of a system without the provision of a master processor by applying processor fault detection notice when it is detected a reception section is in the nonreception state of an operation monitoring signal even after the prescribed time elapse and inputting a new operation monitoring signal to a transmission section. CONSTITUTION:When a fault takes place in a processor 2, a processor 3 cannot receive an operation monitoring signal S1 from the processor 2. A monitoring section 7 of the processor 3 resets a timer 8 at the transmission (point A) of the preceding operation monitoring signal S1 and counts the reception time based on a clock signal (c) from the timer 8, the elapse of the next signal reception timing time T111 is recognized and the occurrence of the fault in the processor 2 is discriminated. The monitoring section 7 based on the discrimination informs the fault detection of the processor 2 to reset the timer 8 to send the operation monitoring signals S1 to the processor 4. Thus, the fact of the occurrence of the fault is discriminated by individual processors 1-4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault detection method for a multiprocessor system that automatically detects the occurrence of a fault in each of a plurality of processors coupled to a bus.

(Prior Art) A conventional failure detection method for a multiprocessor system has a mask processor in the system that manages the operating state of each processor, and this mask processor sequentially sends operation monitoring signals to all other processors. The system detects the occurrence of a failure in all processors in the system by transmitting a response signal, monitoring the response, and determining that the processor is at fault if the response signal is not received within a predetermined time.

This technique will be specifically explained based on FIG.

The multiprocessor system connects one mask processor 31 and three processors 32 to 34 to a ring bus 3.
It has a configuration in which 5 are connected. Mask processor 31
manages the operating status of the other processors 32-34. The mask processor 31 transmits an operation monitoring signal Sll to the processor 32, and monitors whether the response signal S+Z is received within a predetermined time. The results are then managed as the operating state of the processor 32. Subsequently, the mask processor 31 is replaced by the processor 33 . By sequentially repeating the same procedure for the processors 34, failures in each of the processors 32 to 34 are detected.

[Problem to be solved by the invention]

In the conventional multiprocessor system failure detection method described above, a special processor 31 called a mask processor is provided in the system, and this mask processor 31
Since the system detects a failure in a processor by transmitting an operation monitoring signal S11 from one processor to all other processors 32 to 34 and monitoring the response signal Sl□, there are the following drawbacks.

(a) Since only the mask processor 31 performs fault monitoring, the load on the master processor 31 increases as the number of monitored processors 32 to 34 increases.

(b) If a failure occurs in the mask processor 31 itself, the failure detection function of the entire system will stop.

The purpose of this invention is to solve the above-mentioned conventional problems.
It is an object of the present invention to provide an economical and highly reliable fault detection method for a multiprocessor system that can perform fault detection operations using a plurality of processors.

(Means for Solving the Problem) The present invention is a fault detection method for a multiprocessor system that detects a fault in a processor by sequentially passing an operation monitoring signal to a plurality of processors connected via a bus. , each processor has a receiving section that receives the operation monitoring signal from the previous processor, a transmitting section that sends the operation monitoring signal to the next processor, and a receiving section that monitors the receiving state of the receiving section and receives the operation monitoring signal of the receiving section. When the operation monitoring signal is input to the transmitting section, or when the receiving section notices that the operation monitoring signal is not being received even after a predetermined period of time has elapsed, a processor fault detection notification is sent and a new operation monitoring signal is sent. It is characterized in that the transmitting section includes a monitoring section that is manually operated.

〔Example〕

Embodiments of the invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a fault detection method for a multiprocessor system according to an embodiment of the present invention.

The failure detection method of this multiprocessor system is such that processors 1 to 4 are connected in a ring through a bus 5, and an operation monitoring signal S is sent to the processors 1 to 4 in order to detect a failure in the processors.

Each processor l (~4) includes a receiving section 6, a monitoring section 7, a timer 8, and a transmitting section 9.

The receiving unit 6 receives an operation monitoring signal S from an adjacent processor,
This is for receiving and sending it to the monitoring section 7.

The monitoring unit 7 monitors the operation monitoring signal S1 from the receiving unit 6 and the clock signal C from the timer 8 to detect whether there is a failure in an adjacent processor.

The functions of the monitoring section 7 will be specifically described below. The monitoring unit 7 is
The operation monitoring signal SI received from the receiving section 6 is sent to the transmitting section 9, the timer is reset, and the clock signal C from the timer 8 is monitored. After sending the operation monitoring signal S1 to the transmitting section 9 based on this clock signal C, the time t until it is manually transmitted from the receiving section 6 is measured. If the time t is approximately equal to the preset next signal reception timing T, the monitoring unit 7 determines that the processor 4 is operating normally, resets the timer 8, and resets the transmitting unit. The operation monitoring signal S is sent to the terminal 9. The timing at which the operation monitoring signal S1 is sent to the transmitter 9 is set at the time when the transmission timing is out, which is T2 hours after the reception of the operation monitoring signal S. The measurement of the T2 time is performed by resetting the timer 8 when the monitoring unit 7 receives the operation monitoring signal S, and measuring the clock signal C input from the timer 8. On the other hand, if the monitoring unit 7 does not receive the operation monitoring signal S1 even after the next signal reception timing time T has elapsed, it determines that a failure has occurred in the processor 4, and sends a notification to that effect via a monitoring control (not shown). Send to equipment, etc. The monitoring section 7 has a function of resetting the timer 8 and sending out a new operation monitoring signal S1 to the transmitting section 9 in parallel with this notification.

The next signal reception timing time T1 is set to be at least longer than the time from when the operation monitoring signal S is sent from the processor 1 to when it passes through the processors 2, 3, and 4 and returns to the processor 1.

Next, the fault detection operation of this embodiment will be explained in Figs. 1 and 2.
This will be explained based on the diagram.

FIG. 2 is a sequence diagram of the failure detection operation shown by the failure detection method of the multiprocessor system of this embodiment.

The processor 1 resets the timer 8 and transmits the operation monitoring signal S1 from the transmitter 9 to the processor 2.

As shown in FIG. 2, the processors 2 to 4 receive the operation monitoring signal S from the previous processor, and send the operation monitoring signal S1 to the next processor when the signal transmission timing is out at time T2.

When all of the processors 1 to 4 are operating normally, the operation monitoring signal S passes through the processors 1 to 4 in order;
It returns to processor 1 again.

This operation monitoring signal S1 is received by the receiving section 6 of the processor 1. The monitoring section 7, which receives the operation monitoring signal S from the receiving section 6, recognizes based on the clock signal C from the timer 8 that the time of reception substantially coincides with the next signal reception timing time T1.

Thereby, the monitoring unit 7 determines that the processor 4 is operating normally. In parallel with receiving the operation monitoring signal Sl, the monitoring unit 7 resets the timer 8, measures the clock signal C from the timer 8, and determines the signal transmission timing out time T.
2, an operation monitoring signal Sl is sent to the transmitter 9. The transmitter 9 transmits this operation monitoring signal S1 to the next processor 2 (FIG. 2).

At this time, if a failure occurs in the processor 2, the processor 2 cannot receive the operation monitoring signal S from the processor 1, and cannot send the operation monitoring signal S1 to the processor 3 ( Figure 2).

Therefore, the processor 3 cannot receive the operation monitoring signal Sl from the processor 2. The monitoring unit 7 of this processor 3 monitors the previous operation monitoring signal S at the time of transmission (FIG. 2A).
Since the timer 8 is reset at point 8) and the reception time is measured based on the clock signal C from the timer 8, the passage of the next signal reception timing T is recognized and the processor 2
It is determined that a problem has occurred. Based on this judgment,
The monitoring unit 7 notifies the processor 2 of failure detection, and
In order to prevent timing out of reception of the next signal other than the own processor 2, the timer 8 is reset and the operation monitoring signal S is transmitted to the processor 4 via the transmitter 9 (second
figure).

In this way, the fact that a failure has occurred can be determined by each of the Bromo Sensors 1 to 4. Further, there is no need to stop the operation of processors other than the failed processor 2 due to the occurrence of a failure.

〔Effect of the invention〕

Since the fault detection method for the multiprocessor system of the present invention is configured as described above, it has the following effects.

(a) It is possible to realize a fault detection operation in the system without installing a special processor called a mask processor in the system, and as a result, it is possible to construct a more economical system.

(b) No matter which processor in the system fails, the failure detection operation within the system does not stop or stop. As a result, it is possible to improve the reliability of the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a fault detection method for a multiprocessor system according to an embodiment of the present invention, and FIG.
FIG. 3 is a sequence diagram of the failure detection operation performed by the failure detection method of the multiprocessor system shown in the figure. FIG. 3 is a block diagram showing the conventional failure detection method of the multiprocessor system. 1 to 4... Processor 5... Bus 6... Receiving section 7... Monitoring section 8... Timer 9... Transmitting section

Claims (1)

[Claims] (1) A failure detection method for a multiprocessor system that detects a processor failure by sequentially passing an operation monitoring signal to multiple processors connected via a bus, in which each processor receives a signal from the previous processor. A receiving section that receives the operation monitoring signal; a transmitting section that sends the operation monitoring signal to the next processor; and a transmitting section that monitors the receiving state of the receiving section and inputs the operation monitoring signal to the transmitting section when the receiving section receives the operation monitoring signal. or a monitoring unit that notifies the processor failure detection and inputs a new operation monitoring signal to the transmitting unit when the receiving unit detects that the operation monitoring signal is not being received even after a predetermined period of time has elapsed. A failure detection method for a multiprocessor system characterized by the following.