JP2917291B2 - Fault detection method for multiprocessor systems - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault detection method for a multiprocessor system that automatically detects the occurrence of a fault in each of a plurality of processors coupled to a bus.

[Conventional technology]

Conventional multiprocessor system fault detection methods are:
The system has a master processor that manages the operating state of each processor. This master processor sequentially sends operation monitoring signals to all other processors, monitors the response signal response, and responds within a predetermined time. If a signal cannot be received, the processor is determined to be faulty, so that the fault occurrence of all processors in the system is detected.

 This technique will be specifically described with reference to FIG.

The multiprocessor system has a configuration in which one master processor 31 and three processors 32-34 are connected by a ring-type bus 35. The master processor 31 manages the operation states of the other processors 32 to 34. Master processor 31 transmits an operation monitoring signal S ₁₁ to the processor 32, the response signal S ₁₂ within a predetermined time to monitor whether the received. Then, the result is managed as the operation state of the processor 32. Subsequently, the master processor 31 repeats the same procedure for the processors 33 and 34 in order to detect the failure of each of the processors 32 to 34.

[Problems to be solved by the invention]

In the conventional fault detection method of the multiprocessor system described above, a special processor 31 called a master processor is provided in the system, and the operation monitoring signal S is transmitted from the master processor 31 to all other processors 32-34.
₁₁ sends, because it was intended to detect faults in processors by monitoring the response signal S _12, has the following drawbacks.

(A) Since the failure monitoring is performed only by the master processor 31, the load on the master processor 31 increases as the number of the monitored processors 32 to 34 increases.

(B) When a failure occurs in the master processor 31 itself, the failure detection function of the entire system stops.

SUMMARY OF THE INVENTION An object of the present invention is to provide an economical and highly reliable fault detection method for a multiprocessor system in which a plurality of processors can perform a fault detection operation in order to solve the conventional problem.

[Means for solving the problem]

The present invention is a failure detection method for a multiprocessor system in which a plurality of processors coupled via a bus forward an operation monitoring signal to detect a failure of the processor. A receiving unit that receives the operation monitoring signal of the receiving unit, a transmitting unit that transmits the operation monitoring signal to the next processor, and monitors a receiving state of the receiving unit, and transmits the operation monitoring signal to the transmitting unit when the receiving unit receives the operation monitoring signal. A monitoring unit that inputs, or sends a new operation monitoring signal to the transmitting unit, and sends a processor failure detection notification to the monitoring control device when the receiving unit detects that the operation monitoring signal is not received even after the predetermined time has elapsed. And each processor monitors the failure of an adjacent processor without placing a special master processor.

〔Example〕

 An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a failure detection method for a multiprocessor system according to one embodiment of the present invention.

The fault detection method of the multiprocessor system, the processors 1-4 connected by a bus 5 in a ring shape, is a method of detecting a fault of the processor by allowing wound forward operation monitoring signals S ₁ to the processor 1-4.

Each of the processors 1 to 4 includes a receiving unit 6 and a monitoring unit 7
, A timer 8 and a transmission unit 9.

The receiving unit 6 receives an operation monitoring signal S ₁ from an adjacent processor.
Is received and sent to the monitoring unit 7.

Monitoring unit 7, by monitoring the clock signal c from the operation monitoring signals S ₁ and the timer 8 from the receiving unit 6, and detects the presence or absence of failure of the adjacent processor.

Hereinafter, the function of the monitoring unit 7 will be specifically described. Monitoring unit 7
Resets the timer sends out the operation monitoring signals S ₁ received from the receiving unit 6 to the transmission unit 9 monitors click 8 lock signal c from the timer 8. And this clock signal c
After issuing the operation monitoring signals S ₁ to the transmitter 9 on the basis of the measured time t until input from the receiving unit 6. If the time t is substantially equal to the next signal receiving timing period T ₁ which is set in advance, the monitoring unit 7 determines that the processor 4 is operating normally, the transmitting unit 9 resets the timer 8 It sends the operation monitoring signals S ₁ to. Transmission timing of the transmission unit 9 of the operation monitoring signals S ₁ from the reception operation monitoring signals S ₁
This is performed when the transmission timing is out _two hours after T. Measurements of T ₂ hours is carried out by the monitoring unit 7 timer 8 is reset when the reception operation monitoring signals S _1, to measure the clock signal c inputted from the timer 8. On the other hand, if the monitoring unit 7 does not receive the operation monitoring signals S ₁ even after T ₁ following the signal reception timing period, it is judged that the processor 4 has failed, not shown notification to that effect monitoring Send to control device. Monitoring unit 7 has a function of sending out a new operation monitoring signals S ₁ to the transmitting unit 9 resets the timer 8 in parallel with this notification. Incidentally, the next signal receiving timing period T ₁ is at least operation monitoring signal S ₁ is sent from the processor 1 is set to more than the time until return processor 2,3,4 sequentially turning the processor 1.

Next, the failure detection operation of this embodiment will be described with reference to FIGS.

FIG. 2 is a sequence diagram of a fault detecting operation of the fault detecting method of the multiprocessor system according to this embodiment.

Processor 1 sends to reset the timer 8 from the transmitting unit 9 an operation monitoring signals S ₁ to the processor 2.

The processor 2-4, as shown in FIG. 2, receives the operation monitoring signals S ₁ from the front of the processor, and sends the operation monitoring signals S ₁ to the next processor during signal transmission timing out of T ₂ hours Go.

If none of the processors 1-4 are operating properly, operation monitoring signals S ₁ is turned forward processors 1-4,
It returns to the processor 1 again.

This operation monitoring signal S ₁ is received by the receiving unit 6 of the processor 1. Operation monitoring signals S ₁ monitoring unit 7 that enter from the receiving unit 6 recognizes that the time at the time of reception on the basis of the clock signal c from the timer 8 substantially coincides with the next signal receiving timing period T ₁ .

Accordingly, the monitoring unit 7 determines that the processor 4 is operating normally. Operation monitoring signal monitoring unit 7 in parallel with the reception of the S ₁ resets the timer 8 measures the clock signal c from the timer 8 signal transmission timing out time T ₂
The operation monitoring signal S ₁ is sent to the transmission unit 9 when it is determined that the time has arrived. Transmitting unit 9 transmits the operation monitoring signals S ₁ to the next processor 2 (Figure 2).

At this time, if the processor 2 failure occurs, the processor 2 can not receive the operation monitoring signals S ₁ from the processor 1 can not transmit the operation monitoring signals S ₁ to the processor 3 to the processor 3 (FIG. 2).

Thus the processor 3 can not receive the operation monitoring signals S ₁ from the processor 2. Monitoring unit 7 of the processor 3 during the operation monitoring signals S ₁ in the previous transmission (Fig. 2 A
The timer 8 is reset to point), because it measures the received signal based on the clock signal c from the timer 8, it recognizes the lapse of the next signal receiving timing time T _1, when the processor 2 a failure has occurred to decide. Based on this determination, the monitoring unit 7 notifies the failure detection of the processor 2 and resets the timer 8 to monitor the operation via the transmission unit 9 in order to prevent the occurrence of the next signal reception timing out of the processor 2 other than the own processor 2. transmitting the signals S ₁ to the processor 4 (second
Figure).

In this way, the fact that a failure has occurred can be determined by the individual processors 1-4. Further, it is not necessary to stop the operations of the processors other than the processor 2 in which the failure has occurred due to the failure.

〔The invention's effect〕

Since the fault detection method of the multiprocessor system of the present invention is configured as described above, the following effects are obtained.

(A) The system can perform a failure detection operation without installing a special processor called a master processor in the system. As a result, a more economical system can be constructed.

(B) Even if any processor in the system fails, the failure detection operation in the system does not stop. As a result, the reliability of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a failure detection method for a multiprocessor system according to an embodiment of the present invention. FIG. 2 is a sequence diagram of a failure detection operation performed by the failure detection method of the multiprocessor system shown in FIG. FIG. 1 is a block diagram showing a failure detection method of a conventional multiprocessor system. 1-4 Processor 5 Bus 6 Receiver 7 Monitor 8 Timer 9 Transmitter

Claims (1)

(57) [Claims] 1. A failure detection method for a multiprocessor system in which a plurality of processors coupled via a bus forward an operation monitoring signal to detect a failure of a processor, wherein each processor comprises: A receiving unit for receiving an operation monitoring signal from the processor, a transmitting unit for transmitting the operation monitoring signal to the next processor, and a receiving unit for monitoring a receiving state of the receiving unit and transmitting the operation monitoring signal when the receiving unit receives the operation monitoring signal. Or when the receiving unit detects that the operation monitoring signal is not received even after the lapse of a predetermined time, sends a processor failure detection notification to the monitoring control device and inputs a new operation monitoring signal to the transmitting unit. And without a special master processor,
A fault detection method for a multiprocessor system, wherein each processor monitors a fault in an adjacent processor.