JPS59127160A - Fault detecting system - Google Patents

Abstract

PURPOSE:To detect a fault with just a single processor by connecting an originating and an incoming part to actuate for the information on a processor to be tested and monitoring the transferred information to detect the fault. CONSTITUTION:A calling signal CR delivered from the transmission part 301A of the originating part 301 of a CPU30 is received at the reception part 302B of the incoming part 302 via a transmission line 33. An incoming call reception signal CA is transmitted from a reception transmission part 302A, and the prescribed data DT1 received at a reception part 301B is delivered from the part 301A. The information on signals, data, etc. is transferred in such procedures to progress the working of the CPU30. Meanwhile the information transferred to a transmission circuit 33 is received by a fault detector 32, and the coincidence is confirmed with the expected information which is delivered with a prescribed procedure. Then a fault is decided if no information is transferred for a fixed period of time, and a fault report signal TR is transmitted to the fault reception part 303 of the CPU30.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fault detection method, and more particularly to a fault detection method for monitoring the operation of a processing device using input/output information.

Traditional fault detection methods interconnect two processing units,
When one is in actual operation, the other is placed on standby and receives and monitors information from the processing device in actual operation to detect abnormalities.

An example of the configuration of a conventional failure detection method is shown in FIG. 1 as a functional block diagram.
μ child CPU) l QA and standby processing unit (CPU) I
QB means information transmitting sections 101A and 101B and information receiving sections 102A and 102B, respectively.

The system includes failure report notifying units 103A and 103B, and a failure report receiving unit 104A@104B't'', each of which has its transmitting unit connected to the receiving unit of the other device, and its notifying unit connected to the receiving unit.Here, FIG. The failure detection procedure will be explained with reference to FIG. 2. FIG. 2 is a sequence diagram showing an example of the failure detection procedure in FIG. CPU10A sends a specific pattern code PT from transmitting unit 101A to receiving unit 102B of CPU10B at fixed time intervals. CPU10B measures time TM from reception of this code PT, and if the code PT does not arrive by a predetermined time limit, the time limit is exceeded. T.

Detect failures as follows. When the CPUI OB detects a failure, the failure report signal TR is sent from the notification unit 103B to the CPUI OB.
Reception unit 104 of A transfers the information to A, starts releasing and restoring the state of the CPU 10A, deletes the state of CPU OB itself, and executes the processing operation of the processing unit (CPU) QCPUIO
BCPU10B itself is normal. In this way, when the processing unit (CPU) is switched between operation and standby due to predetermined conditions, CPUl0B goes into the operating state, CPUIOA goes into the standby state, and at the same time, the CPU1oB is activated for failure detection according to instructions from the maintenance personnel after repair. Transmission unit 101 of CPU10B
Start monitoring reception of the specific pattern code PT from B.

After this switching, the broken line information line in FIG. 1 is used, and in FIG. 2, the code 101A becomes 102A,
Code 104A becomes 103 A, code 102 B becomes 101
At B, the arrows 103B and 104BK are reversed, and the directions and inclinations of the arrows PT and TR are reversed, and time TM and time limit To are moved to 10A.

As described above, the conventional fault detection method has the disadvantage that it requires two processing units to detect a fault in one transmitter, which is uneconomical.

SUMMARY OF THE INVENTION An object of the present invention is to provide a fault detection method that eliminates the above-mentioned drawbacks and improves the economical efficiency of equipment by configuring fault detection with only one processing device.

The failure detection method according to the present invention includes a processing device under test that includes a data transmitting section and a data receiving section and executes a predetermined functional operation based on information sent and received by the data transmitting and receiving section according to a predetermined procedure; It is characterized by comprising a failure detection means that intercepts and monitors the information transmitted by connecting the apparatus, compares it with a predetermined transmission procedure, and outputs the information as a failure to the processing apparatus under test when there is a discrepancy.

Next, the present invention will be explained with reference to FIGS. 3 and 4. FIG. 3 is a functional block diagram showing an embodiment of the fault detection method of the present invention, and FIG. 4 is a sequence diagram showing the fault detection procedure in FIG. 3.

In Figure 3, the processing device (hereinafter referred to as CPU) for the test object
Reference numeral 30 includes a data transmitting unit 301 and a receiving unit 302 for transmitting and receiving information, as well as a failure report receiving unit 303.
01 and 302 are information transmitting units 301A and 302, respectively.
A and receiving sections 301B and 302B. Transmission section 30
1 and the receiving section 302 are connected by a transmission path 33, and the transmitting section 3
When viewed from 01, the conditions are the same as when connected to another CPU through the transmission line 3, and the conditions for the 5-terminating section 302 are also the same as when connected to another CPU (not shown). A transmission section 301 is connected between the transmission section 301 and the reception section 302.
A, 302A are connected correspondingly to receiving sections 302B, 301B. Furthermore, the failure detection device 32 monitors the transmission line 33 and notifies the failure report receiving unit 303 of the CPU 30 when a failure is detected.

Next, the fault testing procedure will be explained with reference to FIGS. 3 and 4.

The transmission control procedure on the transmission path 33 is based on packet communication. The calling signal CR transmitted from the transmitting section 301A of the transmitting section 301 is intercepted by the detection device 32 and reaches the receiving section 302B of the receiving section 302.

The receiving unit 302 receives the call signal CR at the receiving unit 302B and receives the call acceptance signal CA? from the transmitting unit 302A. Message 5- Believe. The transmitter 301 receives this incoming call acceptance signal CA at the receiver 301B, and outputs predetermined data I)'I'l' from the transmitter 301A. Receiving unit 302B of incoming call unit 302
Upon reception of the data DTI, the transmitter 302A outputs a data acceptance signal DAe, and upon reception of this signal DA, the transmitter 301 outputs predetermined second data DT2ft.

While information such as signals and data is exchanged according to such a procedure and the operation of the CPU 30 progresses, the t information transferred to the transmission line 33 is intercepted by the failure detection device 32, and the expected information and output according to the predetermined procedure are transmitted to the transmission line 33. The match is confirmed. Here, when the expected second data DT2 is not output from the transmitter 301 of the CPU 30, the first data acceptance signal DA that requested data output is transferred, and a time TM is counted from time t, and a failure is detected when the time limit is exceeded TO. The device 32 determines that there is a failure, displays the failure, and sends a failure report signal TR to the failure report reception unit 303 of the CPU 30 to report it.

Normally, when the CPU 30 receives a failure report, it erases the set state and performs an interrupt/automatic start operation to restart the ongoing operation procedure from the first call.

In this embodiment, the processing device has a communication function and the transmission and reception of information using the transmission control procedure has been explained. However, when the information transmission/reception unit is a data bus, a processor bus, etc., a failure detection device that is suitable for each operation procedure is also described. In addition, although only the case of no data has been described, it also includes fault detection such as erroneous detection of r)f*@'c by means of comparison with sufficient information.

As explained above, according to the present invention, it is possible to operate a single processing device under test by connecting the information sending/receiving section and to monitor this transferred information to detect failures, thereby improving the economic efficiency of the equipment. You can get the effect that you can.

[Brief explanation of the drawing]

Fig. 1 is a functional block diagram showing an example of the configuration of a conventional fault detection method, Fig. 2 is a sequence diagram of the fault detection procedure in Fig. 1, and Fig. 3 shows an embodiment of the fault detection method of the present invention. FIG. 4 is a functional block diagram and a sequence diagram of the failure detection procedure in FIG. 3. 30...Processing device, 32...Fault detection device. 33.3... Transmission path, 3o1... Transmission section, 3o2/°°°°° Receiving section, 301 A.
302A・---・Transmission unit, 301B, 302B・
...Receiving section.

Claims (1)

[Claims] The data is transmitted by connecting the processing device under test, which is equipped with a data transmission section and a data reception section, and executes a predetermined functional operation based on the information exchanged by the data transmission and reception section according to a predetermined procedure. A failure detection method comprising: a failure detection means that intercepts and monitors information, compares it with a predetermined transmission procedure, and outputs the information to the processing device under test as a failure when there is a discrepancy.