JPH02278913A - Frequency divider circuit - Google Patents

Abstract

PURPOSE:To stably obtain a desired phase relation of outputs of 1st and 2nd frequency dividers by providing a selector outputting a prescribed signal with a select signal. CONSTITUTION:An output of an OR gate 6 is supplied to a terminal A of a selector 8, an output of an AND gate 7 connects to a terminal B, when a select signal (b) supplied to a terminal S is logical '0', a signal supplied to the terminal A is outputted to a terminal Y, and when the select signal (b) is logical '1', the signal fed to the terminal B is outputted to the terminal Y. For example, when the select signal (b) is logical '1' and a clock (a) descends first after the release of reset, a flip-flop 5 looks for the input being logical 1, the output (h) is brought from logical '0' into logical '1' and a signal (d) starts the clock from logical '0' independently of the relation of phase between the clock and the release of reset. Thus, a desired relation of phase from frequency division signals e, f is obtained from flip-flops 2, 3.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a frequency dividing circuit.

[Conventional technology]

A conventional frequency dividing circuit will be described in detail with reference to the drawings.

FIG. 4 is a circuit diagram showing an example of a conventional frequency dividing circuit.

The frequency dividing circuit shown in FIG. 4 includes a flip-flop 2.3 and an inverter 9.

Flip-flop 2.3 changes the period of clock signal a by 2.
The multiplied signals are multiplied and outputted as signals e and f whose phases are shifted by 1/4 period from each other.

[Problem to be solved by the invention]

The above-mentioned conventional frequency dividing circuit has a drawback that it cannot be determined whether to start frequency division from flip-flop 2 or from flip-flop 3, that is, the phase relationship between the two is not constant.

[Means to solve the problem]

The frequency divider circuit of the present invention includes: (A) a first flip-flop to which a clock signal is input; (B) a second flip-flop to which the clock signal is input via a first inverter; (C) the an OR gate to which a clock signal and the inverted output of the first flip-flop are input; (D) an AND gate to which the clock signal and the output of the second flip-flop are input;
E) The output of the OR gate is supplied to the A terminal, the output of the AND gate is supplied to the S terminal, a select signal is supplied to the S terminal, and when the select signal is logic "0", the output of the AND gate is supplied to the A terminal. a selector that outputs a signal supplied to the S terminal to the Y terminal, and outputs the signal supplied to the S terminal to the Y terminal when the select signal is logic "1°"; (G) a fourth flip-flop to which the output of the selector is supplied via a second inverter and outputs a second frequency-divided signal; be done.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The frequency divider circuit shown in FIG. (C) O to which the clock signal a and the inverted output g of the flip-flop 4 are input.
R gate 6, (D) AND gate 7 to which clock signal a and the output of flip-flop 5 are input, (E) The output of OR gate 6 is supplied to the A terminal, and the output of AND gate 7 is supplied to the S terminal. When the select signal is logic "O", the signal supplied to the A terminal is output to the Y terminal, and when the select signal is logic "1'', the signal is output to the S terminal. (F) a third flip-flop 2 to which the output d of the selector 8 is supplied and outputs the first frequency-divided signal e; CG) an output d of the selector 8; is supplied via the second inverter 10, and the fourth flip-flop 1 outputs the second frequency-divided signal f.
3. Consists of.

FIGS. 2 and 3 are time charts for explaining the operation of the frequency dividing circuit shown in FIG. 1.

FIG. 2 shows the case where the select signal is logic "0".

Set the reset signal C to logic "0" and set it to logic "1".
In other words, immediately after resetting and releasing, flip-flop 2,
3 starts from a logic "0" at its output, and the signal d starts from a logic "1" since the opposite of the output of the flip-flop 4 is a logic "1".

When the tarok rises for the first time after the reset is released, the flip-flop 4 sees the input as logic "1", changes the output from logic "1" to logic "0", and resets the clock. Regardless of the phase relationship of release, the divided clock is logic “1”.
The clock can be started from ``''.

FIG. 3 shows a case where the select signal is logic "1".

When the select signal C is set to logic "1" in advance and reset and released, the outputs of flip-flops 2 and 3 become logic "0".
Since the output of the flip-flop 5 is a logic "0°", the signal d starts from a logic "On".

When the clock falls for the first time after the reset is released, the input of the flip-flop 5 sees the logic "1" and the output becomes the logic "0".
” to logic “1” and d can start the clock from logic in On regardless of the phase relationship between the clock and reset release, so the flip-flops 2 and 3
The signal becomes as shown in FIG. 3, and a desired phase relationship can be obtained.

〔Effect of the invention〕

Since the frequency dividing circuit of the present invention can start frequency division from either the first or second frequency divider, it has the effect of stably realizing the phase relationship between the outputs of the first and second frequency dividers. .

Lop, 6...OR Kate, 7...
A N D Kate, 8...Selector 9.
10...Inverter.

Claims (1)

Claims: (A) a first flip-flop to which a clock signal is input; (B) a second flip-flop to which the clock signal is input via a first inverter; (C) the clock signal. (D) an AND gate to which the clock signal and the output of the second flip-flop are input; (E) the output of the OR gate to the A terminal; is supplied, the output of the AND gate is supplied to the B terminal, a select signal is supplied to the S terminal, and when the select signal is logic "0", the signal supplied to the A terminal is output to the Y terminal, and the a selector that outputs the signal supplied to the B terminal to the Y terminal when the select signal is logic "1"; (F) a third flip-flop to which the output of the selector is supplied and outputs the first frequency-divided signal; (G) A fourth flip-flop to which the output of the selector is supplied via a second inverter and outputs a second frequency-divided signal.