JPH02278834A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the number of lithographic processes, to reduce an alignment displacement and to make a device fine by using a multiple self-alignment process. CONSTITUTION:A lower-layer insulating film 3 and a base extraction electrode 4 on it are formed on the surface of a substrate 1 by using a first oxidation-resistant film 2. By using a second oxidation-resistant film 2A formed by etching a width of the first oxidation-resistant film 2, a base contact electrode 5 is formed between the oxidation-resistant film 2A and the lower-layer insulating film 3. An upper-layer insulating film 5 is formed on it. By using a third oxidation-resistant film 2B formed by further etching a width of the oxidation-resistant film 2A, a spacer insulating film 7 is formed between the oxidation-resistant film 2B and the base contact electrode 5. From an opening part formed by etching and removing the oxidation-resistant film 2B, impurities of one conductivity type are implanted into a formation region of an inner base 8 of the substrate 1; an emitter electrode 9 is formed. Impurities of an opposite conductivity type are implanted into the electrode; the whole substrate 1 is heat-treated; an outer base 10, the inner base 8 and an emitter 11 are formed one after another. Thereby, main parts of an element region can be formed without an alignment operation or by an alignment operation with rough accuracy.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Principle of the Invention 1) Principle of the Invention 2) Example of Action Examples of invention 1) Examples of invention 2) Examples of invention 1) and 2) Effects of the invention (Fig. 1) (Fig. 2) (Fig. 3) (Fig. 3) (Fig. 4) (Figure) [Summary] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a multiple self-alignment process.

The aim is to eliminate 2-position misalignment by reducing the number of lithography steps, and to promote miniaturization and higher integration of devices.

a step of partially forming a first oxidation-resistant film on the semiconductor substrate; and using the first oxidation-resistant film, forming a lower insulating film on the surface of the semiconductor substrate other than the first oxidation-resistant film. and a step of forming a base extraction electrode made of a conductive film thereon;
A base contact made of a conductive film is formed between the second oxidation resistant film and the lower insulating film using a second oxidation resistant film formed by reducing the width of the oxidation resistant film by etching. forming an electrode, forming an upper insulating film on the base contact electrode, and using a third oxidation-resistant film formed by further reducing the width of the second oxidation-resistant film by etching. , a step of forming a spacer insulating film between the third oxidation-resistant film and the base contact electrode, and an opening formed by removing the third oxidation-resistant film by etching,
a step of implanting an impurity of one conductivity type into a formation region of an internal base of a semiconductor substrate, forming an emitter electrode made of a conductive film in the opening, and implanting an impurity of an opposite conductivity type for forming an emitter into the emitter electrode; Furthermore, the entire semiconductor substrate is heat-treated to activate the previously implanted impurities and form the external base,
A bipolar transistor is formed by sequentially forming an internal base and an emitter.

Also, use the same method as above to form the CMO3 element region.

Construct by forming in a self-consistent manner.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a multiple self-alignment process.

(Prior Art) FIG. 5 is a schematic cross-sectional view of a conventional example of a bipolar transistor portion of B i CMO3.

In conventional self-alignment technology, ■emitter, ■internal base, ■link base, ■external base, ■lower insulating film, ■
Upper layer insulating film, ■Spacer insulating film.

The 10 steps of forming ■emitter electrode, ■base contact electrode, and [phase] base extraction electrode cannot be formed without a lithography process that requires precise alignment, or at least a lithography process that requires multiple precise alignments. I needed it.

[Problem to be solved by the invention]

Therefore, patterns are repeatedly misaligned due to alignment in each lithography process.

For example, even with a positioning accuracy of 0.1 am, if the operation is repeated 10 times, a positioning margin of 1 μm is required, which hinders the miniaturization and high integration of devices.

[Means to solve the problem] FIG. 1 and FIG. 2 are diagrams explaining the principle of the present invention.

In the figure, 1 is a semiconductor substrate, 2 is a first oxidation-resistant film,
2A is a second oxidation-resistant film, 2B is a third oxidation-resistant film, 3 is a lower insulating film, and 4 is a base extraction electrode.

5 is a base contact electrode, 6 is an upper layer insulating film, 7 is a spacer insulating film, 8 is an internal base, 9 is an emitter electrode, 1
0 is an external base, 11 is an emitter, 12 is an emitter extraction electrode, 13 is a semiconductor substrate, 14 is an oxidation-resistant film, 15
16 is a lower layer insulating film, 16 is a source/drain extraction electrode,
17 is a source/drain contact electrode, 18 is an upper layer insulating film, 19 is a spacer insulating film, 20 is a gate insulating film,
21 is a gate electrode, 22 is a source/drain, and 23 is a gate lead electrode.

The problem with the above-mentioned misalignment that hinders the miniaturization of device patterns is that even with the bipolar transistor pattern shown in Figure 1 as an example, the number of lithography steps that require precise alignment accuracy can be reduced as much as possible. This can be solved by using multiple self-alignment processes.

That is, as shown in FIG. 1 as a diagram illustrating the principle of the present invention 1), the steps are listed in the order of steps.

(a) A step of partially forming the first oxidation-resistant film 2 on the semiconductor substrate l.

(b) Using the first oxidation-resistant film 2, a lower insulating film 3 and a base extraction electrode 4 made of a conductive film are formed on the surface of the semiconductor substrate 1 other than the first oxidation-resistant film 2. The process of forming.

(C) Using a second oxidation-resistant film 2A formed by reducing the width of the first oxidation-resistant film 2 by etching.

between the second oxidation-resistant film 2A and the lower insulating film 3;

A base contact electrode 5 made of a conductive film is formed.

forming an upper insulating film 6 on the base contact electrode 5;

(d) Using a third oxidation-resistant film 2B formed by further reducing the width of the second oxidation-resistant film 2A by etching,
a step of forming a spacer insulating film 7 between the third oxidation-resistant film 2B and the base contact electrode 5;

(e) a step of implanting one conductivity type impurity into the formation region of the internal base 8 of the semiconductor substrate 1 through the opening created by removing the third oxidation-resistant film 2B by etching;

(f) An emitter electrode 9 made of a conductive film is formed in the opening, and an opposite conductivity type impurity for forming an emitter is implanted into the emitter electrode 9. Furthermore, the entire semiconductor substrate 1 is heat-treated and then implanted first. Activate the impurities, external base 10,
Internal base8. By including the step of sequentially forming the emitters 11, a bipolar transistor can be formed only by self-alignment.

Also, in MOS or CMO3, the second
As shown in the figure, a MOS element part can be formed. By combining both, BtCMO3 can be completed.

That is, FIG. 2 is a diagram illustrating the principle of the present invention 2), and the steps are listed in the order of steps.

(a) a step of partially forming the first oxidation-resistant film 14 on the semiconductor substrate 13;

(mountain) Using the first oxidation-resistant film 14, a lower insulating film 15 is formed on the surface of the semiconductor substrate 13 other than the first oxidation-resistant film 14.
and a step of forming source/drain lead electrodes 16 made of a conductive film thereon.

(c) SN Using a second oxidation resistant film 14A formed by reducing the width of the first oxidation resistant film 14 by etching.

A source/drain contact electrode 17 made of a conductive film doped with impurities is formed between the second oxidation-resistant film 4^ and the lower insulating film 15, and on the source/drain contact electrode 17. and a step of forming upper layer insulation W418.

(b) Using the third oxidation resistant film 14B formed by further reducing the size of the second oxidation resistant film 14A by etching, the third oxidation resistant film 14B and the source/drain contact electrode 17 are formed. and a step of forming a spacer insulating film 19 between the two.

(e) forming a gate insulating film 20 in the opening created by removing the third oxidation-resistant film 14B by etching;

(f) A step of forming a gate electrode 21 made of a conductive film in the opening on the spacer insulating film 19 and further heat-treating the entire semiconductor substrate 13 to activate the previously implanted impurity. Accordingly, the CMO3 element portion can be formed only by self-alignment.

Also, as shown in Fig. 3, by combining both of them, BicM
O3 can be completed.

[Effect]

In the present invention, by using a multiple self-alignment process, the number of lithography steps can be reduced, the misalignment can be reduced, and device miniaturization can be achieved. In this case, even if the alignment accuracy is as rough as that of Sogerahuie, there will be no problem in miniaturization.

〔Example〕

FIG. 3 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps.

In the figure, 24 is a Si substrate, and 25 is a buried collector layer.

26 is an epitaxial layer, 27 is a Si0g film, 28 is S
29 is Si3Nm film, 30 is SiO2 film,
31 is a 5iO1 film, 32 is a channel stopper, 33 is a poly 5i11, and 34 is a Si0g film.

35 is SOG, 36 is poly-Si film, 37 is resist,
38 is poly Si film, 39 is resist, 40 is link base, 41 is sto, 1.42 is 5ift film, 43 is internal base, 44 is poly 5i11.45 is emitter, 46
is an external base, 47 is an Al film, 48 is a Si substrate, 49 is an N0 buried well, 50 is a P0 buried well, 51 is an epitaxial layer, 52 is a P well, 53 is a channel stopper, 54 is a Sin film, 55 56 is poly-Si film, 57 is LDD, 58 is LDD, 59 is S
iO□ film, 60 is stow film, 61 is Si0g film, 62
is a channel.

63 is poly 5i11. 64 is source, 65 is drain,
66 is an Al film.

Hereinafter, the process will be explained in order by assigning step numbers, based on the drawings of FIGS. 3(a) 6 to 3(q).

As shown in FIG. 3(a).

Arsenic (As”
) at an accelerating voltage of 40 keV and a dose of lXl0”7cm.
'', and annealed in dry oxygen (Ol) at 1,150.degree. C. for 1 hour to form a buried collector layer 25 of n''.

2> Phosphorus-doped n-epitaxial layer 26 with a thickness of 2 μm
To the thickness of 1. (Grows at 150℃.

3〉Additionally, by wet oxidation at 850°C.

300 5iO1 films 27 are grown.

<4> The Si3N4 film 28 was formed at 800°C by the CVD method.
Laminate the film to a thickness of ays.

(5>5iz Na film 28 and Sing film 27 are patterned using a mask.

As shown in FIG. 3(b).

<6> 5isNn film 29 was formed at 800°C by CVD method.
Coat to a thickness of 0.00 people.

<7> By reactive ion etching (RIB).

By anisotropically etching 5iJ4H29, the 5iJ4 film 2 is formed only on the side walls of the Sin film 27 and the Si3Ng film 28.
Make sure to leave 9. This is done in order to reduce bird's beak when forming the SiO□ film 30, which will be described later.

<8> Form a Si film 30 as a lower insulating film on the epitaxial layer 26 to a thickness of 2,000 wafers in a self-aligned manner at 1,000° C. by wet oxidation.

<9> U grooves for element isolation are etched by anisotropic etching.

<10> Perform wet oxidation at 1.000° C. to form a Sin film 31 to a thickness of 2.000 μm in the U groove.

<11> By ion implantation using a patterned resist (hereinafter referred to as a "rough resist mask") that does not require highly accurate alignment.

Acceleration voltage of B is 70keV, dose amount is 5X1013
/c+m'' conditions to form a channel stopper 32.

<12> Poly S is applied inside the U groove at 600℃ using the CVO method.
The i film 33 is grown to a thickness of 3 μm to fill the U groove.

<13> Etch the surface and add poly-Si only inside the U groove.
Make sure that the film 33 remains.

<14> At 900℃ by wet oxidation, i,ooo
People's Sif! A film 34 is formed on the poly-Si film 33 within the U-groove.

<15> Apply 5OG35 to a thickness of 2 μm over the entire surface.

<16> Further, a resist (not shown) is applied to a thickness of 2 μm.

<17> Perform anisotropic etching on the entire surface using the RIB method so that 5OG 35 remains only on the poly-Si film 33 in the U groove.

Adjust the ratio of etching gas to remove resist and 5OG3.
Etching is performed so that the etching rates of No. 5 are the same.

The main point of the embodiment of the present invention is in the bipolar transistor formation region near the Si, N, and film 28, so that
Regarding the area within the dashed-dotted line shown in b).

A detailed explanation will be given from FIG. 3(C) onwards.

As shown in FIG. 3(c).

<18> Poly 5illi used as base extraction electrode
36 was grown to a thickness of 3,000 wafers at 600° C. using the CVO method.

<19> Apply resist 37 to a thickness of 1 μm over the entire surface.

As shown in FIG. 3(d).

<20> R11! By full-plane anisotropic etching using the method.

The gas ratio of chlorine and boron trichloride ((/!+Bl/!) is adjusted so that the etching rate of the resist 37 and the poly-Sl film 36 are the same. Form a base extraction electrode.

<21> In dry nitrogen, 1. (Annealing was performed at 150°C for 1 hour to grow grains of poly5il136.

Reduces the wiring resistance of the base lead electrode.

<22> Pattern poly 5ilI136 by etching.

Form a wiring pattern for the base lead electrode.

<23> SOG (not shown) is applied and etched back to planarize the surfaces of the wiring portion and the SiO film 30 portion.

<24> Using a rough resist mask, B was ion-implanted at an acceleration voltage of 40 keV and a dose of 4X10.
The wiring resistance of the base lead electrode made of the poly-Si film 36 is reduced by implanting under the condition of 'ゝ/c-8.

As shown in FIG. 3(e).

<25> By isotropic etching, 5isNa film 28
The S
An icoN4 film 28A is formed.

At this time, the poly-Si film 36 is hardly etched.

Furthermore, the 8° implanted region implanted into the 5isN4 film 28 in the previous step is removed in one step.

<26> Oxide 11127 is removed by RIB method.

As shown in FIG. 3(f).

<27> Poly-Si film 3 was formed at 600°C by CVD method.
8.

Grows to a thickness of 2,000 people.

<28> Apply resist 39 to a thickness of 1 μm.

As shown in Figure 3(g).

<29> Etch the entire surface using RIB to the same height as the poly-Si film 36 on the side wall of 5iiNJ128A.

A base contact electrode of the poly-Si film 38 is formed in a self-aligned manner.

<30> Bo is implanted using the ion implantation method at a dose of 4×10''/cab'' at 40 keV.This is mainly for the purpose of doping the external base region.
This is to inject into the poly-Si film 38.

As shown in FIG. 3(h).

<31> By CVD method, 800℃ Te, 3.000
(The film length of the DSiO1 film 41 is 1.

As shown in Figure 3(i).

<32> Using caustic potash and alumina, Sing
Polishing the membrane 41, in this case the 5iJa membrane 28
A is the brim of polishing, so poly 5tW
The Sing film 41 remains only on the A36 and the poly-Si film 38.

As shown in Figure 3 (J).

<33> By isotropic etching, 5iJa tll
28A is etched with phosphoric acid or the like to a predetermined thickness and width to form a Si, N, film 28B.

At this time, the Sing film 41 and the poly-Si film 38 are hardly etched.

<34> Using a rough resist mask, Bo was implanted by ion implantation at an acceleration voltage of 15 keV and a dose of 113×10
Under the condition of "/cts", it is injected in a self-aligned manner into the diffusion region of the link base 40 connecting the external base and the internal base.

As shown in FIG. 3(k).

<35> By CVD method or plasma CVD method, 8
A 2,000-layer SiO□ film 42 is grown at 00°C.

As shown in Figure 3 (1).

<36> The entire surface of the SiO□ film 41 is coated with RlE, Si, IN
, etched to the same height as the side walls of the membrane 28B, and
A Sing film 42 as an insulating film separating the base electrode and emitter electrode, leaving a space between the i film 38 and the SiJ film 28B.
spacers (or sidewalls) are formed in a self-aligned manner.

As shown in Figure 3(m).

<37> Etch the 5izNa film 28B with phosphoric acid or the like.

Remove.

<38> Subsequently, the thin film 27 of Sin is also removed using acid.

<39> A 5iO1 film (not shown) with a thickness of 200 mm is formed at 800° C. by wet oxidation.

<40> Using a rough resist mask, B + was accelerated by ion implantation at a voltage of 10 keV and a dose of 5X10.
In the diffusion region of the internal base 43 under the condition of "/cva",
Inject in a self-consistent manner.

<41> Remove the SiOz film with a thin layer of acid.

As shown in FIG. 3(n).

<42> Grow the Po'JSi film 44 to a thickness of 2,000 wafers at 600° C. using the CVD method.

<43> Using a rough resist mask, As” was implanted by ion implantation at an acceleration voltage of 100 keV and a dose of 1.
The poly-Si film 44 is implanted under the condition of 14×10”/cm” for the purpose of doping the diffusion region of the emitter 45.

<44> In dry oxygen, at 1,100°C, the whole was heated to 10
Anneal for ~100 seconds to activate impurity diffusion,
Emitter 45. Internal base 43. Linkbase 40. Each external base 46 is formed in a self-aligned manner.

As shown in FIG. 3(0).

<45> In pre-treatment, the thin oxide film on the poly-Si film 44 is removed.

<46> Grow an A1 film 47 as an emitter electrode to a thickness of s, ooo on the entire surface of the substrate by sputtering.

<47> Using a photomask, remove the Al film 47 and polyS
The i film 44 is patterned to form a wiring pattern.

Bipolar transistors and transistors are completed on the Si substrate 24.

The first example is a case where it is applied to a bipolar transistor, but it can easily be applied to MOS (or CMO3) and BiC.
It can also be applied to MO3.Next, as a second example, Bi
As with the embodiment applied to CMO3, the process will be explained in order of process numbers with reference to FIG. However, the steps common to the bipolar transistor described above are omitted.

As shown in Figure 3(p).

The process of CMO3 up to this point is shown in Figure 3 (a
) to FIG. 3(j) are basically the same as the bipolar transistor steps.

However, since the following steps are different, the steps will be explained in order with reference to FIG. 3(p).

■The collector formed on the Si substrate 48 is made of Bi
In cMO3, n” buried well 52 in pMO3jl area,
The p-buried well 50 is made of nMO3. The n' buried well 49 is made in the same process as the n0 buried collector layer 28, but the p' buried well 50 is made by adding the following process after step <1>.

<101> The entire surface of the SiO□ film (not shown) is removed using hydrofluoric acid or the like.

<102> A SiO□ film (not shown) is formed by 300 people at 850°C by wet oxidation.

<103> Using a rough resist mask, B'' was buried by ion implantation at an acceleration voltage of 150 keV and a dose of 7×10''/c+a'' (7).
Inject into the 150/150 formation region.

<1(14>>5t(h) Remove the entire surface of the film.

■Formation process of p-well 5 only with nMOs, step <3>
Add after.

Using a <1 (15>) rough resist mask, Be is implanted into the Lt52 formation region by ion implantation at an acceleration voltage of 150 keV and a dose of 5×10 13 /cm.

(2) Forming the channel stopper 53 is added after step <7>. However, this is not particularly necessary for 9MO3.

<1 (16) A Si0g film (not shown) is formed by 300 people at 850°C by wet oxidation.

<107> Using a rough resist mask, channel stop 53 was applied to B by ion implantation at an acceleration voltage of 100 keV and a dose of 2×10"/cm".
Inject into the formation area.

(2) An ion implantation step for source/drain extraction electrodes made of polySt film 55 is added after step <24> in 2MO3. nMO3 is also used in step <24>.

<108> Using a rough resist mask, As'' is implanted into the poly-Si film 55 by ion implantation at an acceleration voltage of 100 keV and a dose of 5×10'5/cm2.

(2) An ion implantation step for source/drain contact electrodes made of poly-Si film 56 is added after step <30> for nMO3. 2MO3 is also used in step <30>.

<109> Using a rough resist mask, As'' was deposited into a poly-Si film 5 by ion implantation under conditions of an acceleration voltage of 100 keV and a dose of 5χ10IS/cI112.
Inject 6 times.

■An ion implantation step for forming LDD (low concentration source/drain regions) is added after step <34>. 2MO
In 3.

<110> Using a rough resist mask, B + was accelerated by ion implantation under conditions of an acceleration voltage of 15 keV and a dose of lXl0"/am", LDD60 (7)
Inject into the formation area.

Note that the nine steps may also be used as step <34>.

In nMO3.

<iii> Using a rough resist mask, P′ was accelerated by ion implantation at an acceleration voltage of 50 keV and a dose of lXl0Iff/cm” (7) Condition 1?, LDD61
(7) Inject into the formation region.

412 >For gate formation, 200 layers of Sto and film 61 are formed by oxidation with hydrochloric acid at 800''C.

<113> By ion implantation, B′ is accelerated at 1
5keV, the dose was changed from O (no implantation) to lXl0”/
C+s'' is implanted into the region where the channel 62 is to be formed in order to control the dark voltage.

<114> A poly-Si film 63 is grown to a thickness of 2,000 wafers at 600° C. using the CVD method.

This step can be omitted if step <42> is performed.

<115> Using a rough resist mask, As'' is implanted into the gate electrode formation region of the poly-Si film 63 under conditions of an acceleration voltage of 100 keV and a dose of 4×10''/cm'' by ion implantation.

This step is omitted if step <43> is performed.

<116> 10-1 at 1,100°C in dry oxygen
00 seconds.

A heat treatment is performed to form sources and drains 64 and 65.

This step is omitted if step <44> is performed.

<117> The thin oxide film on the poly-Si film 63 is removed in pretreatment.

This step is omitted if step <45> is performed.

<118>Af is applied to the entire surface of the Si substrate 48 by sputtering.
The fi film 66 is grown to a thickness of 5,000 nm.

This step is omitted if step <46> is performed.

<119> Using a photomask, pattern the Af film 66 and poly-Si film 63 to form a wiring pattern.

Complete CMO3 on Si-based Vi24.

FIG. 4 is a schematic cross-sectional view when the present invention is applied to BiCMO3.

〔Effect of the invention〕

Due to high integration and miniaturization, the main parts of the device regions such as BiCMO3 bipolar transistors and nMO3, 2MO3, etc., which require alignment accuracy of about 0.1am, are either left unaligned or 1μ using a rough resist mask.
It can be formed by positioning with rough accuracy of m or more.

That is, in a bipolar transistor, the emitter.

Internal base, link base, external base, lower layer insulation film,
A spacer insulating film, an upper insulating film, an emitter electrode, a base contact electrode, and a base extraction electrode can be formed with zero alignment error.

Incidentally, in the bipolar transistor of the embodiment.

If there is no link base, as shown in Figure 5.

The change in impurity concentration from the emitter to the external base (along the * mark) becomes N''-P-N-P, and it no longer operates as a bipolar transistor. On the other hand, in the case of the present invention.

Since it becomes N"-P-P--P" (diode), it exhibits diode characteristics. Therefore, the vertical bipolar transistor N"-P-N- exhibits good transistor characteristics.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are diagrams explaining the principle of the present invention. Figure 3 shows the bipolar transistor and CMO3 of the present invention.
FIG. FIG. 4 is a schematic cross-sectional view when the present invention is applied to B i CMO3. FIG. 5 is an explanatory diagram of a conventional example. In fig. 3 is the lower layer insulating film. 5 is a base contact 6 is an upper layer insulating film. 8 is internal base. 4 is the base extraction electrode. electrode. 7 is a spacer insulating film. 9 is an emitter electrode. lO is an external base, 11 is an emitter. 12 is an emitter extraction electrode. 13 is a semiconductor substrate; 14 is a first oxidation-resistant film; 14^ is the second oxidation-resistant film. 14B is the third oxidation-resistant film. 15 is a lower layer insulating film. 16 is a source/drain extraction electrode. 17 is a source/drain contact electrode. 18 is an upper layer insulating film, and 19 is a spacer insulating film. 20 is a gate insulating film, and 21 is a gate electrode. 22 is the source/drain. 23 is a gate extraction electrode. 24 is an St substrate, and 25 is a buried collector layer. 26 is an epitaxial layer. 27 is a SiO2 film, and 28 is a SiJg film. 29 is a 5lsHa film, 30 is a Sin film. 31 is a Si0g film, and 32 is a channel stopper. 33 is a poly-Si film, and 34 is a 5iQ1 film. 35 is SOG, 36 is poly-Si film. 37 is a resist, and 38 is a polyS iM. 39 is resist, 40 is link base. 41 is Si0g film, 42 is S i Ot Il! +4
3 is an internal base, and 44 is a poly-Si film. 45 is an emitter, and 46 is an external base. 47 is an Al film and 48 is a 5i substrate. 49 is an n0 buried well, and 50 is a p9 buried well. 51 is an epitaxial layer. 52 is a p-well, and 53 is a channel stopper. 54 is a Si0g film, and 55 is a poly 5tll film. 56 is a poly-Si film, and 57 is an LDD. 58 is LDo, 59 is Si0g film. 60 is a SiO□ film, 61 is a Sin film. 62 is a channel, and 63 is a separate poly layer. 64 is the source, and 65 is the drain. 66 hahe 1 membrane] gu 1 company ro 1's t-rioritsu day moon liri figure 1 (thousands/mo・invention 1) principle theory σ month figure 1f! 1 (Lf) 2) A learning 2) /) &, Buried Explanation Diagram No. 22 (f) 2) , lll12 nno principle tl A (Part 1) This υ rib-'1 example / 11 degree tilt 2) Akira Mikoto's plan example n process! ! Figure 3 Annual Salary 2 Time Plan (the

Claims (1)

[Claims] 1) A step of partially forming a first oxidation-resistant film (2) on a semiconductor substrate (1); The lower insulating film (
3) and a base extraction electrode (4) made of a conductive film on it.
a second oxidation-resistant film (2A) formed by reducing the width of the first oxidation-resistant film (2) by etching; A base contact electrode (5) made of a conductive film is formed between the base contact electrode (5) and the lower insulating film (3), and an upper insulating film (6) is formed on the base contact electrode (5).
), and using a third oxidation resistant film (2B) formed by further reducing the width of the second oxidation resistant film (2A) by etching, the third oxidation resistant film (2B) is formed. A step of forming a spacer insulating film (7) between the film (2B) and the base contact electrode (5), and an opening formed by removing the third oxidation-resistant film (2B) by etching. , the internal base of the semiconductor substrate (1) (
Step 8) of implanting an impurity of one conductivity type into the formation region, forming an emitter electrode (9) made of a conductive film in the opening, and implanting an impurity of the opposite conductivity type for forming an emitter into the emitter electrode (9). implantation, and further heat-treating the entire semiconductor substrate (1) to activate the previously implanted impurities to sequentially form an external base (10), an internal base (8), and an emitter (11). A method for manufacturing a featured semiconductor device. 2) First oxidation-resistant film (14) on the semiconductor substrate (13)
using the first oxidation-resistant film (14) to partially form a lower insulating film (15) on the surface of the semiconductor substrate (13) other than the first oxidation-resistant film (14); ) and forming a source/drain extraction electrode (16) made of a conductive film thereon, and a second oxidation resistant film formed by reducing the width of the first oxidation resistant film (14) by etching. Using the membrane (14A),
The second oxidation-resistant film (14A) and the lower insulating film (15)
A source/drain contact electrode (17) made of a conductive film doped with impurities is formed between the source and drain contact electrodes (17), and an upper insulating film (18) is formed on the source/drain contact electrode (17).
), and using a third oxidation resistant film (14B) formed by further reducing the width of the second oxidation resistant film (14A) by etching, the third oxidation resistant film (14B) is formed. A step of forming a spacer insulating film (19) between the film (14B) and the source/drain contact electrode (17), and an opening created by removing the third oxidation-resistant film (14B) by etching. forming a gate insulating film (20) on the spacer insulating film (19); forming a gate electrode (21) made of a conductive film in the opening on the spacer insulating film (19); 1. A method for manufacturing a semiconductor device, comprising the step of heat-treating the impurity to activate previously implanted impurities to form a source/drain (22).