JPS60148142A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to upgrade the element characteristics of a semiconductor device in a simple process by a method wherein, after an etching was performed on the substrate, low-concentration impurities are previously ion-implanted on the whole surface of the substrate and after a masking material was stayed remained in the recessed part of the substrate, high-concentration impurities are separately ion-implanted in the sidewall parts of the recessed part. CONSTITUTION:A thermal oxide film 2 and a polycrystalline silicon film 3 are formed on the whole surface of a semiconductor substrate 1, and after that, masking materials 4 are selectively formed. The substance 1 is performed an etching in such a way as to have a tapered angle using the masking materials 4 respectively as a mask. Impurities of the same conductive type as that of the substrate 1 are selectively ion-implanted in the whole surface using the polycrystalline silicon film 3 as a mask. After an insulating film 6 was deposited, a masking material 4' is formed. An etching is performed on the film 6 using NH4F. Impurities of the same conductive type as that of the substrate 1 are ion- implanted in sidewall parts 8 only using the polycrystalline film 3 as a mask. As a result, the generation of any parasitic channel can be prevented, because high-dose impurities have been already implanted in the corners.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a method for manufacturing a semiconductor device.

[Prior art and its problems]

Recently, semiconductor integrated circuits have become increasingly highly integrated and miniaturized. Therefore, instead of the conventional selective oxidation method (LOCO8), a new element isolation method (BOX method) has been proposed in which the element isolation region of the substrate is etched to form a recess and an insulating film is buried in the recess.

In the conventional BOX method, after etching the substrate using a thermal oxide film as a mask, ions of an impurity (B+ in the case of a P-type substrate) to prevent inversion were implanted using this as a mask. As shown in Figure (a), ions are implanted at the same dose into the bottom and sidewalls of the substrate recess.

This results in a high impurity dose at the bottom of the substrate.

When the device is operated in this way, the depletion layer stretches only a little, which increases the parasitic capacitance, which not only slows down the device's operation speed, but also increases the capacitance between wirings.

At this point, ion implantation could be performed with a reduced dose, but in the conventional method, the dose at the sidewall portion becomes low, resulting in deterioration of device characteristics. In particular, the breakdown voltage between elements deteriorates.

[Purpose of the invention]

This invention improves the problems of the above-mentioned conventional method and aims to improve device characteristics through a simple process.

[Summary of the invention]

In the present invention, after etching the substrate, as shown in FIG. 1(b), impurity ions of a low concentration are implanted into the entire surface in advance, a mask material is left in the recessed part of the substrate, and then a high concentration is etched into the side wall part. This method involves ion implantation of impurities at a high concentration.

〔Effect of the invention〕

According to this invention, low-concentration impurities are ion-implanted into the bottom of the substrate, and high-concentration impurities are implanted into the sidewalls, which reduces parasitic capacitance due to the extension of the depletion layer, and also provides excellent breakdown voltage between elements. There is.

[Embodiments of the invention]

An embodiment of the present invention will be described using FIGS. 2(a) to 2(f).

First, for example, a P-type Si substrate (1
) and apply a thermal oxide film (2) on the entire surface, for example, aoo 7y.
After forming a layer of polysilicon (3), for example, 3 layers of polysilicon (3)
After forming a mask material (4) selectively using photolithography, polysilicon (3) and thermal oxide film (2) are formed using reactive ion etching (RIE). Selective etching.

Next, using the mask material (4) as a mask, the silicon substrate (1
) is etched by RIE to a depth of 0.6 μm at 8 degrees so as to have a taper angle, for example. Next, polysilicon (3)
Using this as a mask, an impurity of the same conductivity type as the substrate, such as boron, is selectively ion-implanted onto the entire surface at a dose of ft 1x 1o12/cI and an acceleration voltage of 35 KeV, as shown in Fig. 2(b).
obtain the shape of Next, an insulating film such as CVD-8i02 (
6) is deposited at about 7000A, and then a mask material (4') is selectively formed thereon by photolithography.

Next K Using NH4F, CVD-8i02 (6)
A mold shape as shown in FIG. 2(d) is obtained by etching. Next, using the polysilicon (3) as a mask, an impurity of the same conductivity type as the substrate (1), such as boron, is added at an acceleration voltage of, for example, 50 KeV.
, ion implantation is performed only into the side wall portion (8) at a dose of lX10'3/-. Next, deposit an insulating film (9) for planarization, for example, CVD-S i02, to about 400m, and then apply a resist (9) for planarization.
02 (8) and resist (9) are etched by RIE at the same etching rate to obtain a shape as shown in FIG. 2(f).

According to this method, when selectively leaving the insulating film (6), the photolithography process is increased by one step compared to the normal BOX process, but mask alignment is easy and strict alignment accuracy is not required.

In addition, the parasitic capacitance due to the extension of the depletion layer at the bottom of the substrate, which has been a problem in the past, is reduced, and the operating speed of the device is not only increased, but also the capacitance between the substrate and wiring is reduced. Furthermore, parasitic channels were generated due to electric field concentration at the corners of the St difference section, resulting in deterioration of device characteristics. However, here, a high dose of boron is implanted into the corners, so the generation of parasitic channels can be prevented. This can prevent deterioration of device characteristics.

Next, as another embodiment of the present invention, a method of leaving a mask material in a recess of a substrate in a self-aligned manner will be described with reference to FIGS. 3(a) to 3(g).

First, a substrate (11) similar to the embodiment shown in FIG. 2 is prepared, and after forming, for example, a thermal oxide film (12) of about 100 (l) on the entire surface, for example, about 300 C1 of AA! (13) is formed.Next, On top of that, a mask material (14) is made using photolithography.
After selectively forming , /u (13) and 5i02 (12) are selectively etched using RIE. Next eight #
Using (13) as a mask, the silicon substrate (11) is etched to a depth of approximately 0.6 μm so as to have a taper angle. Next, using AJI (13) as a mask, an impurity to prevent inversion, such as boron, is added at an acceleration voltage of 50 KeV and a dose of I.
After ion implantation of about
When etching on the 4th floor.

As shown in FIG. 3(d), plasma 5i02 (16
) is slide etched. Next, the plasma 5iOz (16) on Affl (13) is removed at the same time as All (13) by the lift-off method to obtain Figure (e).

Furthermore, in this state, an impurity of the same conductivity type as the substrate, such as boron, is applied to the side wall of the substrate using the thermal oxide film (12) as a mask at a dose of I x 1013/! .

If ions are implanted at an accelerating voltage of 50 KeV, a highly concentrated inversion prevention region (17) is formed only on the side wall of the substrate. next vc
Insulating insulation example Eva CVD-8i02 (18) 700
After forming the OA, planarize it with a resist (19) and etch back the entire surface, as shown in Figure 3 (gl
The shape shown in is obtained.

According to this, whereas in the above embodiment, one mask alignment was required, here, the mask material (here, plasma 5i02) is formed in the substrate recess in a self-aligned manner, which simplifies the process. At the same time, the same effects as in the embodiment described above can also be obtained.

Another implementation is shown in FIG. 4(a). Figure 3 (a) to (g)
The same steps as in the embodiment are carried out until the shape shown in FIG. 3(e) is obtained. Instead of implanting boron ions here, BSG (
After forming silica glass containing boron (26) 9
When heat treatment is performed at 50° C. for 30 minutes, boron in the BSG diffuses into the side wall of the silicon substrate, forming a highly concentrated boron layer (25). As a result, the same effects as in the IIJ embodiment can be obtained.

This BSG may be removed. If removed, a new insulating film is buried. A film containing impurities such as BSG (as opposed to a film containing no impurities) is etched several times faster than N1 (4F, etc.). In a film using this diffusion method, the recesses do not necessarily need to have a taper.

In addition, in FIGS. 2 and 3, for example, the dose of boron is more than i x 10"/ad at the bottom, and I x
It is sufficient if it is above 10”/cac, and the optimal value is 5 to 5 for each.
It is preferable to use a range of 30 x 10"/d and 1 to 30 x 10"/i.

The accelerating voltage may be selected depending on the ion blocking ability of the first film.
A range of ~20011 is good. Also, other impurities, such as
The same applies to P, As, etc.

Here, an insulator was used to selectively form the mask material in the recessed portions of the substrate, but any material may be used as long as it serves as a mask for implanting impurity ions to prevent reversal. For example, sputtering method 8
i02, 8iN, etc. Furthermore, the same effect can be obtained even if the substrate is an n-type substrate, such as MOS transistors, etc.
Paipo 5 Tr, 0MO8.

It can also be applied to SOS boards.

Furthermore, after introducing impurities into the sidewalls, the second film in the recesses is removed, the entire surface of the substrate is thickly covered with a new insulating film, and this insulating film is buried using the above-mentioned embedding method to form an element isolation insulating film. You can do it like this.

[Brief explanation of the drawing]

FIG. 1(a) is a cross-sectional view showing a conventional ion implantation method of anti-inversion impurities, FIG. 1(b) is a cross-sectional view for explaining the present invention, and FIGS. 2(a) to (f) are 3fa) to (g) and FIG. 4 are cross-sectional views of an embodiment of the present invention using the self-alignment method. In the figure, 1.11...Silicon substrate, 2,12...Thermal oxide film, 3...Polysilicon, 4.4', 9,14.19.
・Lugist, 5, 15...Low impurity concentration region, 6, 8
．． 18- cvD-sio2.7... Impurity high concentration region, 16... Plasma 5i02.13...0 Agent Patent attorney Kensuke Norichika (and 1 other person) Figure 1 Figure 3 Figure ↓ (↓JJJ ＃s

Claims (1)

[Claims] a step of selectively forming a first film on a semiconductor substrate; a step of etching the semiconductor substrate using the first film as a mask to form a recess; and a step of etching the semiconductor substrate with the same conductivity type as the substrate using the first film as a mask. ion-implanting an impurity of the same conductivity type as the substrate; a step of selectively providing the second coating in the recessed portion of the substrate, leaving at least the upper part of the sidewall; and using the first and second coatings as masks, 1. A method of manufacturing a semiconductor device, comprising the step of introducing an impurity into a side wall of a recessed portion of a substrate.