JPH0227694B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a microprogram-controlled computer that uses both a high-speed control memory HCS and a medium-speed control memory LCS, each address and address accessing the HCS and LCS are
By setting flag information in a register to indicate whether the address belongs to HCS or LCS, and holding the execution address together with the flag information when execution of a microinstruction is interrupted,
It is now possible to re-access microinstructions that have already been executed.

[Industrial application field]

The present invention provides trapback, retryback processing, and error processing in a microprogram-controlled computer that uses both a high-speed control memory in which microinstructions at the first address are stored and a medium-speed control memory in which microinstructions at other addresses are stored. This invention relates to a control system for re-accessing executed micro-instructions when re-accessing micro-instructions that have been executed up to that point in processing.

In recent years, with the remarkable progress in semiconductor technology, the price of memory has become lower, and the number of machines adopting microprogram-controlled computer architectures has increased due to the ease of design and control changes. are doing.

In microprogram-controlled data processing devices, as the scope of microprogram processing increases and the amount of control memory also increases, it becomes necessary to use high-speed memory to shorten access time. Ta. Additionally, demands for faster data processing have necessitated the use of even faster memories.

However, since high-speed memory is expensive, the cost of a data processing mechanism that uses large amounts of high-speed memory becomes extremely high. For this reason,
A microprogram control method that enables high-speed processing while reducing the use of expensive high-speed memory,
It was requested.

[Conventional technology]

FIG. 3 shows the principle of a microprogram access system (Japanese Patent Application No. 58-212014) proposed by the same applicant to achieve the above-mentioned requirements.

In FIG. 3, 210 is a high-speed control memory (HCS) that can be accessed in one machine cycle.
It is a high-speed, small-capacity control memory that stores only the first address microinstruction in a series of microinstructions for executing one machine language instruction.

Reference numeral 220 denotes a medium-speed control memory (LCS) which cannot be accessed in one machine cycle, and is a medium-speed, large-capacity control memory in which microinstructions for addresses after the first address are stored. LCS
220 includes a memory bank LCS(E) 221 in which microinstructions at even addresses are stored and a memory bank LCS(O) 222 in which microinstructions at odd addresses are stored.

230 is a high speed control memory address register (HCAR) in which an address for accessing HCS 210 is set.

240 is a medium-speed control memory address register (LCAR) section, in which the address for accessing LCS(E) 221 is set, and LCAR(E) 241 and LCS
An LCAR (O) 242 is provided in which an address for accessing (O) 222 is set.

Next, the operation shown in FIG. 3 will be explained with reference to FIG. 4. Figure 4 is an operation timing chart of Figure 3, where 0, 1, 2, etc. in the upper row indicate machine cycles, and A to D in each stage indicate the contents of the address in each address register in each machine cycle. show.

The starting address A for the microinstruction is
It is set in both HCAR230 and LCAR(E)241, and the HCS is set in the machine cycle (O).
210 and LCS(E) 221 are accessed simultaneously. At the same time, LCS (O) to LCAR (O) 242
Address B accessing 222 is set.

Since the HCS 210 is a high-speed memory that can be read in one machine cycle, it reads the microinstruction for address A in machine cycle (1) and stores it in a data register (CSDR, not shown).

On the other hand, LCS(E)221 requires two machines for reading.
Since this is a medium-speed memory that requires cycles, the microinstruction for address A is read out in machine cycle (2) and stored in CSDR. At the same time, the next address C is set in LCAR(E) 241.

When LCS(O) 222 is accessed at address B in machine cycle 1, it
In the machine cycle (3) after the cycle, the microinstruction for address B is read and stored in CSDR. At the same time, the next address D is set in LCAR(O) 242.

Thereafter, LCS(E) 221 and LCS(O) 222 are accessed alternately. As a result, the first microinstruction is read by the HCS 210 in one machine cycle, and from the next machine cycle,
LCS(E) 221 and LCS(O) 222 are accessed alternately, and each microinstruction is read out in one machine cycle.

As described above, by using the small-capacity HCS210 that only stores microinstructions at the start address and the LCS220 that stores microinstructions at other addresses, it is equivalent to configuring the entire control memory with high-speed control memory HCS. High-speed access can be achieved using low-cost control memory.

[Problem that the invention seeks to solve]

The method of the earlier application that combines HCS and LCS mentioned above is
Low-cost control memory eliminates high-cost overall
Although it is possible to access microinstructions in each control memory in one machine cycle in execution, as in the HCS configuration, there are the following problems.

That is, in the above-described system, the microprogram is not stored in a sequential manner but exists across two control memories, HCS 210 and LCS 220. Each memory
The control and configuration of addresses is also different for each control memory. For this reason, when it is necessary to retry a microprogram due to trapback, retryback processing, or error processing after exception processing is completed, the program simply traces the address of the previously executed microinstruction and executes it again. There was a problem in that it was practically impossible to find the address at the time of the original execution.

Especially in the case of error handling, the soft error rate per unit capacity is much higher for high-speed HCS.
No matter how small the capacity, a non-negligible number of errors occurred. However, with conventional methods, it is not possible to re-access the microinstruction in the HCS or LCS where the error occurred, so even if the error is corrected through error handling, the corrected data cannot be rewritten to the original HCS or LCS. There was a problem that I couldn't do it.

E [Means for Solving the Problems] The means taken by the present invention to solve the above-mentioned problems in the conventional microprogram access control system will be explained with reference to FIG. FIG. 1 is a block diagram showing the structure of the present invention.

In FIG. 1, 110 is a high-speed control memory (HCS) that can be accessed in one machine cycle.
Similar to the HCS 210 in FIG. 3, it is a high-speed, small-capacity control memory in which only the microinstructions for the first address in a series of microinstructions are stored.

120 is a medium-speed control memory (LCS) that cannot be accessed in one machine cycle, and is similar to LCS2 in Figure 3.
20, it is a medium-speed, large-capacity control memory in which microinstructions for addresses after the first address are stored.

130 is a high speed control memory address register (HCAR) in which an address for accessing the HCS 110 is set.

Reference numeral 140 denotes a medium speed control memory address register (LCAR) section in which an address for accessing the LCS 120 is set.

A flag section HL is provided in the HCAR 130 and LCAR section 140, and flag information indicating whether the address belongs to the HCS 110 or the LCS 120 is set.

150 is a re-access address register (RAAR) section, which is connected to HCAR 130 or LCAR section 14.
A re-access address register (RAAR) 15 that holds the address for the microinstruction to be re-accessed at 0 along with its flag information.
It has at least one set of 1.

160 is a re-access control means (RACM);
When a RAAR with a re-access address set is selected from the RAAR unit 150 and a re-access signal is input, the RAAR address is input to a predetermined HCAR 130 or LCAR unit 140 according to the instructions of the flag information of the RAAR. Set along with the flag information.

Note that FIG. 1 shows the principle of the configuration of the present invention, and in an actual control system, a part of the configuration may overlap.

[Effect]

HCS by HCAR130 and LCAR part 140
110 and LCS120, execute 1
It is the same as in the conventional system shown in FIGS. 3 and 4 that each control memory microinstruction is called in a machine cycle.

If a situation arises that requires exception handling or error handling, use HCAR130 or
The address of the microinstruction to be accessed again after the completion of the processing in the LCAR unit 140 is held in a predetermined RAAR 151 in the RAAR unit 150 together with its flag information.

When exception processing or error processing is completed, a re-access signal is input to the RACM 160 instructing re-access to the interrupted microinstruction.

The RACM 160 selects the RAAR in which the re-access address is set from the RAAR section 150.
151 and receives a re-access signal,
RAAR 1 is sent to a predetermined HCAR 130 or LCAR section 140 according to the instructions of the flag information of RAAR 151.
51 address along with its flag information.

By doing the above, when an exception handling occurs or an error is detected, regardless of whether the already executed microinstructions are stored in the HCS 110 or the LCS 120, those microinstructions can be easily executed after the exception handling or error handling is completed. The data can be re-accessed and retried or the data corrected by error handling can be rewritten.

〔Example〕

Each embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

(Description of configuration) In Figure 2, HCS110, LCS120,
The RAAR unit 150 and RACM 160 are as described in FIG.

HCAR 130 and LCAR section 140 share a common control memory address register (CSAR) section 170.
contained within. In the CSAR section 170, 17
1 is the current control address register (CCAR), in which the address of the microinstruction currently being executed is set. CCAR171 is equipped with a flag part HL,
The control memory currently being accessed is HCS110.
Flag information indicating which LCS 120 it is is set. 172 is a next control address register (NCAR) in which the address of the next microinstruction to be executed is set. 173 is a further control address register (MCAR) in which the address of the next microinstruction to be executed is set. NCAR172 and MCAR173 include
Like CCAR171, a flag part HL is provided,
Each address register is HCS110 and LCS12
Flag information indicating which of the 0's it is for is set.

As a flag, for example, two bits are provided, one for HCS110 and the other for LCS120,
“00” may indicate that the address is invalid.

The first address of CCAR171 is set at the start of a microinstruction, and it functions as HCAR130.After that, NCAR172 and MCAR
It functions as the LCAR section 140 together with 173. Its configuration is the same as the conventional system shown in Figure 3, so
Detailed explanation will be omitted.

In addition, as shown in Figure 2, HCAR130 and LCAR1
40 is also used, the contents of CCAR 171 are sent to HCS 110 and/or LCS 120 according to the flag part HL. If they are provided separately as shown in FIG. 1, addresses are sent from each to the corresponding control memory.

In the RAAR unit 150, 152 is a first retry address register (R ₁ CAR) in which an address executed before the current one is set together with its flag information. Reference numeral 153 denotes a second retry address register (R ₂ CAR) in which the previously executed address before the current one is set together with its flag information. This operation is performed by sequentially shifting the entire contents of CCAR 171. this
R ₁ CAR 152 and R ₂ CAR 153 are used for retry back operation.

154 is the first trap address register (T ₁ CAR), and the same address as CCAR151 is
It is set together with the flag information. 155 is the second trap address register (T ₂ CAR);
The same address as R ₁ CAR 152 is set along with its flag information. This T ₁ CAR154 and
T ₂ CAR 155 is used during trapback operation.

156 is an error control address register (ECAR) in which an address for data in which an error has occurred is set together with its flag information.

[Explanation of operation] The CSAR unit 170 controls the HCS110 and LCS1.
20 and calling the microinstructions in each control memory 110 and 120 in one machine cycle is the same as in the conventional method described in FIGS. 3 and 4.

During operation, the address currently being executed is set in CCAR 171 and T ₁ CAR 154.
The address to be executed next is set in NCAR 172, and the address to be executed next is set in T ₂ CAR 173.
R ₁ CAR152, T ₂ CAR155 and ECAR156
The previously executed address is set in R ₂ CAR 153, and the previously executed address is set in R 2 CAR 153. Flag information indicating whether the set address belongs to HCS 110 or LCS 120 is set in the flag portion HL of each address register.

The execution microinstruction re-access control operation in this embodiment will be explained using a trapback case as an example.

If the previous microinstruction is interrupted due to some exception handling during the execution of a microinstruction, CCAR171 and NCAR1 for the microinstruction at the time of trapping and the microinstruction to be executed next.
The contents of 72 are T ₂ CAR 155 and T ₁ CAR 154
are saved and maintained respectively.

When the exception processing is completed, a re-access signal instructing trapback is input to the RACM 160.

When the RACM 160 receives this re-access signal, it sequentially selects the T ₂ CAR 155 and the T ₁ CAR 154 and sends the address and flag information to the CSAR section 17.
0, and sets a predetermined HCS 110 or LCS 120 in the address register to be accessed according to the instruction of the flag information.

In that case, in addition to directly setting the specified HCS 110 or LCS 120 in the address register to be accessed, the address and flag information of the selected T ₂ CAR 155 or T ₁ CAR 154 are transferred to the CSAR 170 as is, according to the flag information instructions. ,
The CSAR section 170 may set the flag in a predetermined address register according to the instruction of the flag information. In the latter case, the CSAR section 170
In other words, it will function as part of RACM 160.

The explanation so far has been about the trapback operation, but the retryback operation using the R ₁ CAR 152 and R ₂ CAR 153 and the rewriting operation of error correction data using the ECAR 156 are performed in the same way. In the case of error processing, when the error processing is completed, the microinstruction of the HCS 110 or LCS 120 in which the error occurred is accessed based on the address and flag information of the ECAR 156, and data with the error corrected is rewritten.

In the manner described above, it is possible to carry out trapback and retryback, which were practically impossible in conventional systems, as well as to rewrite error-corrected data.

Although one embodiment of the present invention has been described above,
The present invention is not limited to this example,
This method is applied to other re-access control methods for microinstructions that have already been executed. HCAR130 and
Of course, the LCAR section 140 may be provided separately as shown in FIG.
In addition, the RAAR section 150 and the CSAR section 170 (LCAR
The number of stages of each address register in the section 140 is not limited to twice.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects are produced.

(a) HCAR130 and LCAR section 140 (or
In each address register of CSAR section 170),
By setting flag information that indicates whether the address is for HCS 110 or LCS 120, microinstructions that have already been executed can be transferred to HCS 110 and LCS 120 at the time of trapping, retrying, error detection, etc.
No matter which one is in it, it can be easily called upon re-access.

(b) Even if an error occurs in either the HCS 110 or the LCS 120, data corrected by error processing can be rewritten.

[Brief explanation of drawings]

Fig. 1 - Block explanatory diagram of the configuration of the present invention, Fig. 2
FIG. 3 is an illustration of the principle of a conventional microprogram access method; FIG. 4 is an operational timing chart of FIG. 3. In FIG. 1, 110...high speed control memory (HCS), 120...medium speed control memory (LCS), 13
0...High-speed control memory address register (HCAR), 140...Medium-speed control memory address
Register section (LCAR section), 150... Re-access address register section (RAAR section), 151... Re-access address register (RAAR), 160...
Re-access control means (RACM).

Claims (1)

[Scope of Claims] 1. Re-access to executed microinstructions in a microprogram-controlled computer using both a high-speed control memory 110 in which microinstructions at the top address are stored and a medium-speed control memory 120 in which other address instructions are stored. The control method includes: (a) high-speed control memory 110 and medium-speed control memory 1;
As each address register for 20, an address for the high-speed and medium-speed control memories 110, 120 and flag information indicating whether the address is for the high-speed or medium-speed memory 110, 120 are set. A memory address register 130 and a medium-speed control memory address register section 140 are provided; (b) a high-speed control memory address register 130 or a medium-speed control memory address register section 140;
A re-access address register unit 150 is provided which has at least one set of re-access address registers 151 that hold the address of the microinstruction to be re-accessed in the micro-instruction along with its flag information; A re-access address register in which a predetermined re-access address is set is selected from the access address register section 150, and a predetermined high-speed control memory address register 1 is selected according to the instructions of the flag information.
30 or a medium-speed control memory address register section 140 includes a re-access control means 160 for setting the address of the re-access address register together with its flag information.