JPH0227693B2 - - Google Patents

Description

[Detailed description of the invention] 〔table of contents〕 The present invention will be explained in the following order.

A. Overview B. Field of industrial application C. Conventional technology (Figs. 4 and 5) D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect (Fig. 1) ) G Example G ₁ First example (Fig. 2) G ₁₁ Explanation of configuration (Fig. 2) G ₁₂ Explanation of operation (Fig. 2) G ₂ Second example (Fig. 3) G ₂₁ Explanation of configuration (Fig. 3) G ₂₂ Explanation of operation (Fig. 3) H Effect A [Summary] In the execution microinstruction re-access control method of a microprogram control computer using both high-speed control memory HCS and medium-speed control memory LCS ,HCS
A register HCAR is provided in which the address of the microinstruction is set, and when a microinstruction is interrupted, the execution address is held together with flag information indicating whether the address belongs to the HCS or LCS, and the HCS is executed based on the instruction of the flag information. If you want to access it again,
By accessing HCS using the HCAR address, high-speed re-access is possible.

B [Field of Industrial Application] The present invention relates to a microprogram-controlled computer that uses both a high-speed control memory in which micro-instructions at the first address are stored and a medium-speed control memory in which micro-instructions at other addresses are stored. The present invention relates to an executed microinstruction re-access control system when reaccessing previously executed microinstructions in trapback, retryback processing, error processing, or the like.

In recent years, with the remarkable progress in semiconductor technology, the price of memory has become lower, and the number of machines adopting microprogram-controlled computer architectures has increased due to the ease of design and control changes. are doing.

In microprogram-controlled data processing devices, as the scope of microprogram processing increases and the amount of control memory also increases, it becomes necessary to use high-speed memory to shorten access time. Ta. Additionally, demands for faster data processing have necessitated the use of even faster memories.

However, since high-speed memory is expensive, the cost of a data processing mechanism that uses large amounts of high-speed memory becomes extremely high. For this reason,
A microprogram control method that enables high-speed processing while reducing the use of expensive high-speed memory,
It was requested.

C [Prior Art] FIG. 4 shows the principle of a microprogram access method (Japanese Patent Application No. 1982-212014) proposed by the same applicant to achieve the above-mentioned requirements.

In FIG. 4, 210 is a high-speed control memory (HCS) that can be accessed in one machine cycle.
It is a high-speed, small-capacity control memory that stores only the first address microinstruction in a series of microinstructions for executing one machine language instruction.

Reference numeral 220 denotes a medium-speed control memory (LCS) which cannot be accessed in one machine cycle, and is a medium-speed, large-capacity control memory in which microinstructions for addresses after the first address are stored. LCS
220 includes a memory bank LCS(E) 221 in which microinstructions at even addresses are stored and a memory bank LCS(O) 222 in which microinstructions at odd addresses are stored.

230 is a high speed control memory address register (HCAR) section in which an address for accessing the HCS 210 is set.

240 is a medium speed control memory address register (LCAR), in which the address for accessing LCS(E) 221 is set, LCAR(E) 241 and LCS(O)
The address for accessing 222 is set.
It is equipped with LCAR(O)242.

Next, the operation shown in FIG. 4 will be explained with reference to FIG. 5. Figure 5 is an operation timing chart of Figure 4, where 0, 1, 2, etc. in the upper row indicate machine cycles, and A to D in each stage indicate the contents of the address in each address register in each machine cycle. show.

The starting address for the microinstruction is
HCS is set in both HCAR230 and LCAR(E)241 in machine cycle (0).
210 and LCS(E) 221 are accessed simultaneously. At the same time, LCS (O) to LCAR (O) 242
Address B accessing 222 is set.

Since the HCS 210 is a high-speed memory that can continue reading in one machine cycle, it reads the microinstruction for address A in machine cycle (1) and stores it in a data register (CSDR, not shown).

On the other hand, LCS(E)221 requires two machines for reading.
Since this is a medium-speed memory that requires cycles, the microinstruction for address A is read out in machine cycle (2) and stored in CSDR. At the same time, the next address C is set in LCAR(E) 241.

When LCS(O) 222 is accessed at address B in machine cycle 1, it
In the machine cycle (3) after the cycle, the microinstruction for address B is read and stored in CSDR. At the same time, the next address D is set in LCAR(O).

Thereafter, LCS(E) 221 and LCS(O) 222 are accessed alternately. As a result, the first microinstruction is read by the HCS 210 in one machine cycle, and from the next machine cycle,
LCS(E) 221 and LCS(O) 222 are accessed alternately, and each microinstruction is read out in one machine cycle.

As described above, by using the small-capacity HCS210 that stores the microinstructions at the first address together with the LCS220 that stores the microinstructions at other addresses, it is equivalent to configuring the entire control memory with the high-speed control memory HCS. High-speed access can be achieved using low-cost control memory.

D [Problem to be solved by the invention] The method of the earlier application that uses both HCS and LCS is as follows:
Low-cost control memory eliminates high-cost overall
Although it is possible to access microinstructions in each control memory in one machine cycle in execution, as in the HCS configuration, there are the following problems.

That is, in the above-described system, the microprogram is not stored in a sequential manner but exists across two control memories, HCS 210 and LCS 220. Each memory
The control and configuration of addresses is also different for each control memory. For this reason, when it is necessary to retry a microprogram due to trapback or retryback processing after exception processing or error processing, the address of the microinstruction that has been executed once is simply traced back. There was a problem that it was practically impossible to find the original address at the time of execution again.

Therefore, even if data is modified by error processing, the modified data cannot be rewritten into the original control memory. In particular, trapping interrupts and traps the previous microinstruction for some kind of exception handling, and returns to the original microinstruction after the exception handling is completed, and interrupts the previous microinstruction and retries for some kind of error handling. When executing a retry back to return to the original microinstruction after error handling is completed, if an exception condition occurs in the last microinstruction of the machine instruction or in pipeline processing with a high degree of decoding precedence, Determining the original runtime address was practically impossible.

For this reason, for example, if a trap occurs at the end of a microinstruction, a register is provided that stores a flag indicating the status, and at the end of the exception handling routine, a signal indicating the end of the instruction is issued instead of a trap back or retry back signal. This required some operations.

E [Means for Solving the Problems] The means taken by the present invention to solve the above-mentioned problems in the conventional microprogram access control system will be explained with reference to FIG. FIG. 1 is a block diagram showing the structure of the present invention.

In FIG. 1, 110 is a high-speed control memory (HCS) that can be accessed in one machine cycle.
Similar to the HCS 210 in FIG. 4, it is a high-speed, small-capacity control memory that stores only the microinstructions for the first address in a series of microinstructions.

120 is a medium-speed control memory (LCS) that cannot be accessed in one machine cycle, and is similar to LCS2 in Figure 4.
20, it is a medium-speed, large-capacity control memory in which microinstructions for addresses after the first address are stored.

Reference numeral 130 denotes a high speed control memory address register (HCAR) section which holds at least the start address of the microinstruction currently being executed in the HCS 110.

Reference numeral 140 denotes a medium-speed control memory address register (LCAR) unit, which has an address for the HCS 110 or LCS 120 as well as an address for the HCS 11.
0 or LCS 120 is set.

Reference numeral 150 denotes a re-access address register (RAAR) unit, which includes at least one set of re-access address registers (RAAR) 151 that hold the address of the microinstruction to be re-accessed in the LCAR unit 140 together with its flag information. have.

160 is a re-access control means (RACM);
At the time of re-access, the RAAR 15 to which the re-access address is set from the RAAR section 150
1 is selected and the flag information indicates the HCS 110, the HCAR unit 130 selects the HCS 110.
and sets the address together with the flag information in the LCAR section 140. If the flag information indicates the LCS 120, the address is sent to the LCAR unit 140 along with the flag information.
Set to .

Note that FIG. 1 shows the principle of the configuration of the present invention, and in an actual control system, a part of the configuration may overlap.

F [Function] By HCAR part 130 and LCAR part 140
The fact that the HCS 110 and LCS 120 are accessed and each control memory microinstruction is accessed in one machine cycle is the fourth step.
This is the same as the conventional method shown in FIGS.

If a situation occurs in which some kind of exception handling or error handling is to be performed, the address for the microinstruction that will be accessed again after the processing is completed in the LCAR unit 140 is stored in the RAAR unit 150 along with its flag information. It is held in a predetermined RAAR 151.

When exception processing or error processing is completed, a re-access signal is input to the RACM 160 instructing re-access to the interrupted microinstruction.

The RACM 160 stores the RAAR in which the re-access address is set from the RAAR unit 150.
151 is selected and a re-access signal is input, if the flag information of the RAAR 151 indicates the HCS 110, the HCS is accessed using the start address set in the HCAR section 130. At the same time, it is set in the LCAR section 140 along with the address of the RAAR 151 and its flag information.

If the flag information of the RAAR 151 indicates the LCS 120, the address is set in the LCAR section 140 together with the flag information, and the LCS 120 is accessed.

By doing the above, when an exception handling occurs or an error is detected, regardless of whether the already executed microinstructions are stored in the HCS 110 or the LCS 120, those microinstructions can be easily executed after the exception handling or error handling is completed. The data can be re-accessed and retried or the data corrected by error handling can be rewritten. At this time, these re-accesses can be quickly performed within one machine cycle.

G [Example] Each example of the present invention will be described with reference to the drawings.

G ₁ (First Embodiment) A first embodiment of the present invention will be described with reference to FIG. 2. FIG. 2 is a block diagram showing the configuration of the first embodiment.

G ₁₁ (Explanation of configuration) In Figure 2, HCS110, LCS120,
HCAR section 130, LCAR section 140, RAAR section 1
50 and RACM 160 are as described in FIG.

In the LCAR unit 140, 141 is a current control address register (CCAR) in which the address of the microinstruction currently being executed is set. CCAR14
1 is provided with a flag section HL, in which flag information indicating whether the control memory currently being accessed is HCS 110 or LCS 120 is set. 142 is a next control address register (NCAR) in which the address of the next microinstruction to be executed is set. 143 is a further control address register (MCAR) in which the address of the next microinstruction to be executed is set.
NCAR142 and MCAR143 include CCAR1
Similarly to 41, a flag section HL is provided, and flag information indicating whether each address register is for HCS 110 or LCS 120 is set.

In the RAAR unit 150, 152 is a first retry address register (R ₁ CAR) in which an address executed before the current one is set together with its flag information. Reference numeral 153 denotes a second retry address register (R ₂ CAR) in which the previously executed address before the current one is set together with its flag information. This operation is performed by sequentially shifting the entire contents of CCAR 141. this
R ₁ CAR 152 and R ₂ CAR 153 are used during retry back operation.

154 is the first trap address register (T ₁ CAR), and the same address as CCAR141 is
It is set together with the flag information. 155 is the second trap address register (T ₂ CAR);
The same address as R ₁ CAR 152 is set along with its flag information. This T ₁ CAR154 and
T ₂ CAR 155 is used during trapback operation.

156 is an error control address register (ECAR) in which an address for data in which an error has occurred is set together with its flag information.

In the RACM 160, 161 is a re-access controller (RACT) which selects an address register from among address registers 152 to 156 in which a re-access register is set.
RAAR is detected and the address register RAAR is set to HCS110 and LCS12 based on the flag information.
It is determined which one of 0 it corresponds to.
If HCS110, HCS selection signal HSEL
If the LCS is LCS120, the LCS selection signal LSEL is output. 162 is a selector,
Address register 151~ according to LSEL signal
The address register RAAR from among 155
Select the address and flag information.
It is transferred to the LCAR section 140.

G ₁₂ [Explanation of operation] By HCAR section 130 and LCAR section 140
The fact that the HCS 110 and LCS 120 are accessed and each control memory microinstruction is accessed in one machine cycle is the fourth step.
This is the same as the conventional method shown in FIGS.

The start address of the microinstruction set in the HCAR section 130 is retained thereafter. When a microinstruction starts operating, its start address is also set in the CCAR 141 along with address information instructing the HCS 110. This is to set the address and flag information in the RAAR unit 150 when an exception occurs or an error is detected.

Note that when the microinstruction starts operating, CCAR1
HCS1 by the start address set to 41.
10 (at the time of re-access, the HCAR section 130 re-accesses the HCS 110 in order to quickly perform the re-access operation, as will be explained later), but the HCS 110
Since the LCS 120 and LCS 120 are physically located in separate locations, it is advantageous for high-speed operation to provide each with an address register.

During operation, the start address of the microinstruction is set in the HCAR section 130, and the CCAR 14
1 and T ₁ CAR 154 are set with the address currently being executed. The address to be executed next is set in NCAR142, and MCAR1
43 is set to the next address to be executed. R ₁ CAR152, T ₂ CAR155 and ECAR
The address executed previously is set in 156, and the address executed previously is set in R ₂ CAR 153. Each register has its flag section HL containing the address of that register in HCS.
110 or LCS 120 is set.

The execution microinstruction re-access control operation in this embodiment will be explained using a trapback case as an example.

If the previous microinstruction is interrupted due to some exception handling during the execution of a microinstruction, CCAR141 and NCAR1 for the microinstruction at the time of the trap and the microinstruction to be executed next.
The contents of 42 are T ₂ CAR155 and T ₁ CAR154
are saved and maintained respectively. When the exception processing is completed, a re-access signal instructing trapback is input to the RACM 160.

RACT161 in RACM160 is T ₂ CAR
According to each flag information of 155 and T ₁ CAR154,
It is determined whether the microinstruction to be returned to is the HCS 110 or the LCS 120. When it is determined that the microinstruction to be returned to is HCS 110, it outputs the HCS selection signal HSEL, and when it is determined that it is LCS 120, it outputs the LCS selection signal LSEL.

If the microinstruction to be returned to is HCS110, HCAR1 is set by HCS selection signal HSEL.
The start address of the microinstruction set to 30 is read and the HCS 110 is accessed.

As a result, from the start of trapback operation, 1
HCS 110 can be accessed within a machine cycle. If you read the start address of the microinstruction held in T ₂ CAR155,
When set to HCAR130, in the case of high-speed processing, HCS110 is set within one machine cycle.
is difficult to access.

On the other hand, the selector 162 outputs the LCS selection signal LSEL.
Accordingly, the addresses of T ₂ CAR 155 and T ₁ CAT 154 are sequentially selected and set in MCAR 143,
With these, the LCS 120 is accessed and the microinstruction after the start address is retrieved.
The same applies when the RACT 161 generates the LCS selection signal LSEL from the beginning.

The explanation so far has been about the trapback operation, but the retryback operation using the R ₁ CAR 152 and R ₂ CAR 153 and the rewriting operation of error correction data using the ECAR 156 are performed in the same way. In the case of error processing, when the error processing is completed, the microinstruction of the HCS 110 or LCS 120 in which the error occurred is accessed based on the address and flag information of the ECAR 156, and data with the error corrected is rewritten.

As described above, it is possible to perform trapback and retryback, which were practically impossible with conventional methods, as well as rewrite error-corrected data, and re-access within one machine cycle. This can be done quickly.

G ₂ (Second example) If one machine language instruction is processed by one microinstruction, and such machine language instructions are consecutive, the contents of HCAR 130 will change every cycle each time the machine language instruction changes. . On the other hand, HCAR130
Since the current address of the HCS 110 is held, the RAAR section 150 is
The first address of the microinstruction that is different from the microinstruction for each address set in
There may be cases where the data is held in the HCAR unit 130.

The second embodiment shows an embodiment that is effective in such a case.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention.

G ₂₁ (Explanation of configuration) In Figure 3, HCAR section 30', RACM 16
0' and other configurations excluding the selector 170 are:
The configuration is the same as that of the first embodiment shown in FIG.

In the HCAR section 130', HCAR131 is
A high speed control memory address register that holds the current address of HCS110 and HCAR1
32, 133, etc. are high speed control memory address registers in which the addresses of each previous and previous previous HCS 110 are saved. The address held in each register is the start address of each microinstruction.

In RACM160', RACT161' has:
At the time of re-access, a re-access signal is input which instructs which microinstruction is to be re-accessed for trap-back, re-try-back or re-writing of error correction data.

RACT161' uses this re-access signal and
Based on the flag information of the address register to be re-accessed in the RAAR unit 150, the type of microinstruction to be returned to and whether it is determined by the HCS 110
or LCS120. When the microinstruction to return to is HCS110,
It outputs the HCS selection signal HSEL', and when the LCS is 120, it outputs the LCS selection signal LSEL'.

The selector 170 selects a predetermined HCAR from the HCARs 131, 132, etc. by the HCS selection signal HSEL'.
Select.

G ₂₂ (Description of operations) Operations other than the trapback, retryback, and error correction data rewriting control operations are the same as in the first embodiment described above.

In the case of trapback, when the exception processing that caused the trap is completed, a re-access signal instructing trapback is input to the RACM 160'.

RACM161' is T ₂ CAR 155 and T ₁ CAR
154 flag information and the re-access signal, the microinstruction to be returned to is determined by the HCS 110.
The HCS selection signal HSEL' and the LCS selection signal are determined by determining which one is the LCS120.
Output LSEL′.

If the microinstruction to be returned to is HCS 110, the selector 170 receives the HCS selection signal
According to HSEL', from HCAR130'
Select the HCAR (one of 131, 132, etc.) indicated by HSEL'.

As a result, even if the contents held in each register in the HCAR 130' are changed, the data is stored from the start of the trapback operation, as in the case of the first embodiment.
HCS 110 can be accessed within a machine cycle.

The retry back operation using the R ₁ CAR 152 and R ₂ CAR 153 and the rewriting operation of error correction data using the ECAR 156 are performed in the same manner.

Although each embodiment of the present invention has been described above,
The present invention is not limited to these embodiments, but can be applied to other re-access control methods for microinstructions that have already been executed. Also, LCAR
Each address in section 140 and RAAR section 150
The number of register stages is not limited to two stages.

H [Effects of the Invention] As explained above, according to the present invention, the following effects are produced.

(a) The address is written in each address register of HCAR section 130 and LCAR section 140 as HCS1.
By setting flag information that indicates whether the instruction is for LCS 10 or LCS 120, the already executed microinstruction can be saved at the time of trapping, retrying, error detection, etc.
Regardless of whether it is in the HCS 110 or LCS 120, it can be easily called upon re-access.

(b) By providing an HCAR that holds at least the address currently being executed in the HCS 110, it is possible to quickly re-access within one machine cycle at the time of re-access.

(c) Even if an error occurs in either the HCS 110 or the LCS 120, data corrected by error processing can be rewritten.

[Brief explanation of drawings]

Fig. 1 - Block explanatory diagram of the configuration of the present invention, Fig. 2
Figures - An explanatory diagram of the first embodiment of the present invention, Figure 3 - An explanatory diagram of the second embodiment of the present invention, Figure 4 - Principle diagram of the conventional microprogram access method, Figure 5
Figure - Operation timing chart in Figure 4. In FIG. 1, 110...high speed control memory (HCS), 120...medium speed control memory (LCS), 13
0... High speed control memory address register section (HCAR section), 140... Medium speed control memory address register section (LCAR section), 150... Re-access address register section (RAAR), 160... Re-access control means (RACM) .

Claims (1)

[Scope of Claims] 1. Execution microinstructions in a microprogram-controlled computer that uses both a high-speed control memory 110 in which microinstructions at the first address are stored and a medium-speed control memory 120 in which microinstructions at other addresses are stored. The re-access control method includes: (a) a high-speed control memory address register unit 130 that holds at least the start address of the microinstruction currently being executed in the high-speed control memory 110; and (b) a high-speed or medium-speed control memory 110. , 120 as well as flag information indicating whether the address is for the high-speed or medium-speed control memory 110, 120.
(c) Medium-speed control memory address/register section 140
a re-access address register unit 150 having at least one set of re-access address registers 151 that hold the address for the microinstruction to be re-accessed in the micro-instruction along with its flag information; The re-access address register in which the re-access address is set is selected from the address register section 150, and its flag information is stored in the high-speed control memory 11.
When specifying 0, the high-speed control memory 11 is specified by the high-speed control memory address register section 130.
0 is accessed, and the address of the re-access address register along with its flag information is accessed by the medium-speed control memory address register section 140.
If the flag information indicates the LCS 120, the address is set to the medium-speed control memory address register section 1 along with the flag information.
40. A re-access control method for executing micro-instructions, comprising: re-access control means 160 for setting the execution micro-instruction to 40. 2 High-speed control memory address register section 130
has a high-speed control memory address register 131 that holds the start address of each micro-instruction that is currently being executed or has already been executed, and the re-access control means 160 determines whether the micro-instruction to be re-accessed is in the high-speed control memory 110 or the like. 1, the high-speed control memory address register 131 or the like holding the start address of the microinstruction is selected to access the high-speed control memory 110. Execution microinstruction playback access control method.