JPH02276417A - Control device for switch - Google Patents

Abstract

PURPOSE:To control a switch with precision by finding a corrected value into memory if the frequency of a signal inputted from a test signal generator to a filter in a test slips off at not less than a designated value and by amending it with the corrected value in the actual monitoring. CONSTITUTION:When switches 6 for testing are manually operated, a test signal generation circuit 9 generates signals IO, VO and phi of the quantity of electricity for testing and inputs them into test switching circuits 23 and 33. The signals for testing are filtered 24 and 34, smoothed 25 and 35 to effective values, converted 26 and 36 in levels and inputted into a CPU 4. When the frequency slips off owing to the fluctuation of characteristic of filters 24 and 34, corrected values are operated in comparison with the outputs of a setting circuit 5 and stored into the CPU 4. When zero-phase-sequence current 2 or zero-phase- sequence voltage 3 of a power supply system 1 is monitored, it is decided whether or not the values are at not less than the setting to control the switches. Precise switch control can thereby be performed even if the characteristic of filters are slipped off.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention is directed to a switch control device, especially an SOG (storage
0vercurrent Ground) type switch control device.

(b) Conventional technology - S is connected to a three-phase load, detects excessive current and ground fault current, and when the ground fault current exceeds a predetermined level, current is sent to the trip coil based on the detection, and the switch There is also an SOG type switch side 'a device which is designed to cut off the switch by passing current through a trip coil on the condition that the power is cut off when an overcurrent is detected. In this type of switch control device, a filter circuit is provided before a conventional signal processing circuit in order to accurately process a ground fault signal detected by a zero-phase current detector or a zero-phase voltage detector. Typically, this filter circuit is constructed in such a way that a 50 Hz or 60 Hz signal is passed therethrough.

(c) Problems to be Solved by the Invention The above-mentioned filter circuit is designed to have a frequency characteristic of 50Hz or 60Hz, but due to variations, it may deviate from the expected peak frequency,
Also, changes over time may cause variations in frequency characteristics. If the frequency characteristics change too drastically, the signal level derived from the signal processing circuit will also change drastically, and there is a possibility that the switch cannot be controlled accurately due to the setting value.

This invention was made with attention to the above problem, and even if the frequency characteristics of the filter circuit change, the degree of change is detected through self-diagnosis, and the effect is reduced by performing correction calculations. The purpose of the present invention is to provide a switch control device that can

(d) Means and operation for solving the problem The opening/closing 2ii control device of the present invention includes a zero-sequence current detector that detects the zero-sequence current of a three-phase bus, and a filter circuit for filtering the signal from this zero-sequence current detector. a first signal processing circuit that processes signals received through the three-phase bus, a zero-phase voltage detector that detects the zero-phase voltage of the three-phase bus, and a signal filter circuit from the zero-phase voltage detector.
a second signal processing circuit that receives the signal and processes the signal; and means for determining whether the outputs of the first signal processing circuit and the second signal processing circuit are each greater than or equal to a preset value. and a means for shutting off the bus switch in response to the determination output that the determination result by the determination means is set (direct sales), and the filter circuit is tested at a predetermined frequency during the test. a test signal generation circuit that inputs a signal; and a correction value that receives the test signal derived from each filter circuit to a first signal processing circuit and a second signal processing circuit, and calculates a correction value based on the level of these test signals. A calculation means and a correction value storage means for storing the correction value are generally provided.

In the mode, a correction value storage means is provided for performing a correction calculation using the correction value on the signal levels derived from the first signal processing circuit and the second signal processing circuit.

This switch side? In the ff1l device, first, in the self-diagnosis mode (during testing), a predetermined frequency (for example: 60 Hz signal) is input from the test signal generation circuit to the filter circuit at a constant level, and a corresponding output signal is derived from the signal processing circuit. Ru. On the other hand, for example, a reference level serving as an iM hour reference is stored, and a correction value is calculated by comparison with this level. If the values are substantially the same, there is no need to particularly calculate a correction value. However, if there is a difference between the acquired test signal and the reference level, store that ratio as a correction value.

Next, in the normal mode (measurement mode), the detected zero-sequence current and zero-sequence voltage are passed through the filter circuit and derived from the signal processing circuit. , the captured value is corrected using this correction value, and the result is compared with the set value.

(E) Examples The present invention will be explained in more detail with reference to Examples below.

FIG. 3 is a block diagram of an SOG type switch control device in which the present invention is implemented. In the figure, a 6600V power supply system 1 is connected to a zero-sequence current detector (zero-sequence current transformer) 2 and a zero-sequence voltage detector 3, which detect zero-sequence current and zero-sequence voltage, respectively. It's like that. The zero-sequence current detected by the zero-sequence current detector 2 is converted into a voltage signal, and the zero-sequence current detected by the zero-sequence current detector 2 is converted into a voltage signal, which is sent to an input voltage transformer 21, an over-input protection circuit 22, a test switching circuit 23, a filter circuit 24, an effective value smoothing circuit 25, and a level conversion circuit 26. It is input to the CPU 4 via the CPU 4. Similarly, the zero-phase voltage detected by the zero-phase voltage detector 3 is transmitted to the voltage converter 3a, the input voltage transformer 31, the over-input protection circuit 32, the test switching circuit 33, the filter 34, the effective value smoothing circuit 35, and the level converter 3a. The circuit 36 is input to the CPU 4.

The over-input protection circuits 22 and 32 are circuits that have the function of suppressing the detected zero-sequence current and zero-sequence voltage when they exceed the level, and the test switching circuits 23 and 33 are configured to suppress the detected zero-sequence current and zero-sequence voltage when they exceed the level. A zero-sequence current detection signal and a zero-sequence voltage detection signal from the input protection circuit 22.32 are input to the filter circuit 24.34, and a test signal is input to the filter circuit 24.34 in place of the detection signal during a self-test. Filter circuits 24 and 34 are provided to remove harmonic components, and specifically, for example, a circuit shown in FIG. 4 is used. The frequency characteristics of the filter circuits 24 and 34 are set to have a peak of 55 Hz, as shown in characteristic a in FIG. 5, by setting the constants of the capacitor C6 and the resistors R1 and R2.

Since the peak occurs at 55H2, a level signal higher than a certain level (80% or higher of the 55Hz level) can be derived for both a 50Hz input signal and a 60Hz input signal. The effective value smoothing circuit 25.35 is a circuit for converting the detection signal etc. into a DC component, and the level conversion circuit 26.3
6 is a circuit for converting into a signal suitable for import into the CPU 4, and phase pulse circuits 27 and 37 convert pulse signals corresponding to the zero cross points of the outputs of the filter circuits 24 and 34 into phase pulse signals, respectively. It is inputted to the CPU 4 as a signal and used when detecting a phase difference in each of the zero-phase current detection system and the zero-phase voltage detection system.

The setting circuit 5 is a zero-sequence current■. Setting value, zero-sequence voltage■. This is a circuit for setting the setting value and setting time T of D.
The C test switch 6a is a manual switch for performing a ground fault test, and the SO test switch 6b is a manual switch for performing an overcurrent test. The display section 7 shows ■. Equipped with level display, power display, and forecast display. The output section 8 is equipped with a DG display due to ground fault detection and an SO display due to overcurrent, and also includes a relay for tripping in the event of a ground fault, a relay for tripping in the event of overcurrent, a relay for forecasting, an abnormality relay, etc. It is equipped with

The CPU 4 also includes a test signal generation circuit 9 and a test circuit.
A diagnostic circuit 10 is attached. The test signal generation circuit 9 is
For example, a four-stage self-test current signal To and a self-test voltage signal v0 are generated.

The test signal generation circuit 9 also includes filter circuits 24 and 34.
50Hz for testing the frequency characteristics of.

55Hz, 60] (Z signals are generated at two levels, respectively. These current signals for self-tests, the current signals for frequency characteristic tests are sent to the test switching circuit 23, and the voltage signals for self-tests are The voltage signals for the frequency characteristic test are input to the test switching circuit 23. The current signal ■ is input to the test switching circuit 23, and the voltage signal ■ is input to the test switching circuit 33. Test circuit - The diagnostic circuit 10 has various diagnostic/test functions executed by the CPU 4, such as a constant voltage check function, a contact check function,
This is a general term for the TC check function, inertia function check, filter circuit characteristic test, etc.

In addition, this switch control device includes a filter circuit 11, a constant voltage circuit 12, and constant voltage level conversion circuits 13 and 14 as its own power supply section.

Note that a commercial power supply voltage is applied to the terminals P, , P, and a trip coil is connected between the terminals V, , V, for interrupting the switch of the power supply system 1. TC detection circuit 15
is a circuit for detecting that a trip coil is connected to terminals V, , V,.

In the above embodiment switch control device, the filter circuit 24
Alternatively, if the frequency characteristic of the filter circuit 34 is the characteristic shown in FIG.
For z, a level output within a certain range can be derived. However, a problem arises when the frequency characteristics of the filter circuits 24, 34 become deviated over time, as shown in b or c in FIG. 5. For example, as shown in Figure 6, if the frequency characteristics deviate so that they reach their peak at 60Hz, the difference between using at 60Hz and 5
When used at 0 Hz, there will be a significant level difference, and as a result, settling with correct current values, voltage values, etc. may not be possible. Therefore, in this embodiment control device, a frequency test signal is periodically input into the filter circuit 24, 34 to check the frequency characteristics, and if a deviation of more than a predetermined value has occurred, a correction value is stored. Then, during the operation cycle during monitoring, the frequency characteristics are corrected using this correction value to prevent the influence of deviation.

Hereinafter, the measurement and correction calculation processing of the frequency characteristics of the filter circuit will be explained with reference to the flowchart shown in FIG. 1 and the flowchart shown in FIG.

In the CPU 4, when the operation timing enters the filter test routine of the self test, the determination of the filter test in step STI becomes YES, and the test signal generation circuit 9 first outputs the 50 Hz test signal V l i.
The signal v is sent to the filter circuit 34 through the test switching circuit 33.
Enter 11. Then, the output of the filter circuit 34 when input to this filter circuit 34 is outputted to the effective value smoothing circuit 35.
, is taken into the CPU 4 via the level conversion circuit 36,
At this time, the output level V i (1) is read and stored (step 5T3).Next, the test signal generation circuit 9 outputs the test signal Vl of 55H2 (step 5T4).
, a signal output V outputted through the filter circuit 34 in the same manner as above. and store it (step 5)
T5). Similarly, this time, in step ST6, a 60 Hz test signal Vl+ is inputted, and its output signal ■. read,
Store (step 5T7). Then, from the read values of each frequency 50H2, 551-IZ, and 60 Hz read above, the error with each level at a in Fig. 5 is calculated,
This is stored (step 5TY). Then, it is determined whether this error is greater than or equal to a predetermined value (step 5T9). If the error is within a predetermined value, the process returns as is, but if the error is greater than or equal to a predetermined value, it is set to the high sensitivity side, that is, the level is crystallized. A correction calculation is performed to a level corresponding to the originally low level (step 5TIO).

Here, the high-sensitivity side correction calculation means calculating a correction value for correcting the 60Hz output level in the direction of decreasing, for example, in the case of the frequency characteristic shown in FIG.
This correction value is memorized.

Further, a frequency characteristic test of the filter circuit 24 is also performed using the same process, and the correction values are stored.

In addition, in the calculations from step STI to step 5TIO described above, each human input signal level of 50 Hz, 55 Hz, and 60 Hz was input at a constant level, but this level value was further changed and the signal was input in several stages. Step S
By adding the processes from TI to step 5TIO, it is possible to measure frequency characteristics and calculate their correction values in accordance with each input level. The correction value may be calculated from the average value of the calculated levels at each stage level.

When a correction value is calculated in the case where the frequency characteristics are tested as described above, the CPU 4 stores this and actually outputs the correction value to the zero-sequence current detector and the zero-sequence voltage detector 3. , and its input signal to perform a power system monitoring operation, a correction calculation is performed using this correction value, the level is corrected, and a comparison with a set value is performed.

That is, in the normal mode monitoring cycle, the second
As shown in the figure, the value obtained by reading the actual input voltage ■o from the level conversion circuit 36 is indicated by ■. (Step 5T21)
. Next, it is determined whether or not there is correction, step 5T22).
If a correction value is stored, this correction (ff is taken into account and the level ti!lI is calculated. In other words, a correction calculation is performed (step 5T23). In particular, if there is no correction value,
Step ST23 is skipped. Next, the test switching circuit 23 is switched to the measurement side, and the AC input current manually input from the over-input protection circuit 22 is read as the current value I0 derived from the filter circuit 24, the effective value smoothing circuit 25, and the level conversion circuit 26 (step 5T24), similarly to the above, it is determined whether there is a correction value regarding the current level or not.Step 5T25
), if the correction value is stored, the correction calculation is performed in consideration of the correction value as described above, and if the correction value is not stored,
This step 5T26 is skipped and the process proceeds to the following normal settling operation.

(f) Effects of the Invention According to the present invention, during testing, a test signal of an appropriate frequency is input from the test signal generation circuit to the filter circuit, the output is read, and deviations in frequency characteristics are diagnosed. If is greater than a predetermined value, a correction value is calculated and stored, and during actual monitoring, a correction calculation is performed on the current intake value and voltage intake value using this correction value, and the calculated value is , the switch is controlled by determining whether or not the predetermined setting (jN or more) It has the advantage of being able to perform switch control with the same precision.

[Brief explanation of drawings]

Fig. 1 is a flowchart for explaining the frequency test processing operation of a switch control device according to an embodiment of the present invention, and Fig. 2 shows the correction calculation processing when monitoring the J normal mode in the switch control device. 3 is an overall block diagram of an SoG type switch control device in which the present invention is implemented, and FIG. 4 is a specific circuit example of a filter circuit used in the switch control device. FIG. 5 is a characteristic diagram for explaining the frequency characteristics of the same filter circuit, and FIG. 6 is a frequency characteristic diagram for explaining the peak point when the frequency characteristics of the same filter circuit deviate. It is. 1: Power supply system, 2: Zero-phase current detector, 3: Zero-phase voltage detector, 4: cPU, 9: Test signal generation circuit, 24/34: Filter circuit.

Claims (1)

[Claims] (1) A zero-phase current detector that detects the zero-phase current of the three-phase bus; a first signal processing circuit that receives the signal from the zero-phase current detector through a filter circuit and processes the signal; a zero-sequence voltage detector that detects the zero-sequence voltage of the zero-sequence voltage, a second signal processing circuit that processes the signal received through the signal filter circuit from the zero-sequence voltage detector, and the first signal processing circuit and the second signal processing circuit. means for determining whether the outputs of the signal processing circuits are each greater than or equal to a predetermined value; and opening/closing of the bus bar in response to a determination output that the determination result by the determination means is equal to or greater than the predetermined value. a test signal generating circuit that inputs a test signal of a predetermined frequency to the filter circuit during a test, and a first signal processing circuit and a second signal from each filter circuit, respectively. a correction value calculation means for receiving the test signals derived to the processing circuit and calculating a correction value based on the test signal level; and a correction value storage means for storing the correction value; A switch control device comprising a correction calculation means for performing a correction calculation using the correction value on the signal levels derived from the first signal processing circuit and the second signal processing circuit.