JPH02272365A - Phase detecting circuit for switching device control apparatus - Google Patents

Abstract

PURPOSE:To improve accuracy of an operating time by detecting rise and fall points of rectangular wave pulse signal upon receipt of the rectangular wave pulse signal and detecting phases of the signals inputted in accordance with the time when the above detections are made. CONSTITUTION:In phase detecting circuits 2, 3, when a zero phase current or zero phase voltage is inputted, they are detected for every zero cross point of the AC signal, i.e. every time when positive zero cross points and negative zero cross points are appeared, and the waveforms are reversed in phase pulse generating circuits 27, 37 to output the rectangular wave pulse signal. Then, the phase detection is made by the phase detecting circuits 2, 3 based on the rise and fall points of this rectangular wave pulse, and the phase difference is calculated by a CPU 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention is applicable to, for example, SOG (Storage
The present invention relates to a phase detection circuit for a switch control device such as a 0vercurrent Ground) type switch control device.

(b) Conventional technology Generally, the device is connected to a three-phase load, detects excessive current and ground fault current, and when the ground fault current exceeds a predetermined level, current is applied to the trip coil to disconnect the switch. There is also an sOG type switch control device which, when an overcurrent is detected, causes a current to flow through a trip coil to disconnect the switch on the condition that the power is cut off. This type of switch control device is equipped with a phase detection circuit that detects the phase of the detected zero-sequence voltage and zero-sequence current and determines the phase difference between them, and determines whether or not the phase difference is within the setting range. It also has a distinguishing function. Conventional phase detection circuits detect positive zero-crossing points of current voltage or zero-sequence current, and detect phase and frequency based on these zero-crossing points.

(c) Problems to be Solved by the Invention The above conventional phase detection circuit detects a positive zero crossing point,
Since the phase difference and frequency are detected based on this zero cross point, if we assume that an abnormality occurs at point t, for example, as shown in Figure 5 (a), it is possible to determine this. is the next positive zero cross point (the rising point indicated by the O mark), so it is the section X.

is wasted, and this X is a maximum of 20m5ec at 50Hz.
Therefore, there was a problem that the operating time accuracy could not be improved.

The present invention has been made in view of the above-mentioned problems, and aims to provide a phase detection circuit for a switch control device in which the above-mentioned period X1 is reduced and operating time accuracy is further improved.

(d) Means and operation for solving the problem The phase detection circuit of the switch control device of the present invention includes a zero-sequence current detector that detects the zero-sequence current of the three-phase bus, and a a first signal processing circuit that receives a signal and processes the signal; a zero-phase voltage detector that detects the zero-phase voltage of the three-phase bus; and a second signal processing circuit that receives the signal from the zero-phase voltage detector and processes the signal. The outputs of the signal processing circuit, the phase detection circuit that detects the phase difference between the zero-sequence voltage and the zero-sequence current, the first signal processing circuit, the second signal processing circuit, and the phase detection circuit are each set in advance. means for determining whether or not the set value has been exceeded;
In the switch control device, the switch control device includes means for shutting off the switch of the bus bar in response to a discrimination output indicating that all discrimination results by the discrimination means are equal to or higher than a set value. A phase pulse circuit that outputs a rectangular wave pulse signal whose waveform is inverted every time the pulse signal is inverted, and a phase pulse circuit that receives the rectangular wave pulse signal output from this phase pulse circuit and detects the rising and falling points of the rectangular wave pulse signal. It is characteristically equipped with phase detection means for detecting the phase of the input result based on the detection time point.

In this phase detection circuit, when a zero-phase current, etc. is input, it detects each zero-crossing point of the AC signal, each time a positive zero-crossing point and a negative zero-crossing point arrive, and detects the phase. The pulse generating circuit inverts the waveform and outputs a rectangular wave pulse signal as shown in FIG. 5(b). Then, the phase detection circuit performs phase detection based on the rising point (O mark) and falling point (Δ mark) of this rectangular wave pulse. Therefore, for example, if an abnormality occurs at time t, from the next falling point t2,
In order to enter this detection operation, the period X2 becomes shorter than the period XI, for example, a maximum of 10 m5ec at 50 Hz, and the operating time accuracy can be improved compared to the conventional phase detection circuit.

(E) Examples The present invention will be explained in more detail with reference to Examples below.

FIG. 2 is a block diagram of an SOG type switch control device in which the present invention is implemented. In the figure, a 6600V power supply system 1 is connected to a zero-sequence current detector (zero-sequence current transformer) 2 and a zero-sequence voltage detector 3, which detect zero-sequence current and zero-sequence voltage, respectively. It looks like this. The zero-sequence current detected by the zero-sequence current detector 2 is converted into a voltage signal,
It is manually input to the CPU 4 via an input voltage transformer 21, an over-input protection circuit 22, a test switching circuit 23, a filter circuit 24, an effective value smoothing circuit 25, and a level conversion circuit 26. Similarly, the zero-phase voltage detected by the zero-phase voltage detector 3 is transmitted to the voltage converter 3a, the input voltage transformer 31, the over-input protection circuit 32, the test switching circuit 33, the filter 34, the effective value smoothing circuit 35, and the level converter 3a. The circuit 36 is input to the CPU 4.

The over-input protection circuits 22 and 32 are circuits that have the function of suppressing the detected zero-sequence current and zero-sequence voltage when they exceed the levels, and the test switching circuits 23 and 33 protect against over-input during normal monitoring. The filter circuit 2 filters the zero-sequence current detection signal and zero-sequence voltage detection signal from the protection circuit 22.32.
4.34, and a test signal is input to the filter circuit 24.34 instead of the detection signal during the self-test. Filter circuits 24 and 34 are provided to remove harmonic components. The effective value smoothing circuit 25.35 is a circuit for converting the detection signal etc. into a DC component, and the level conversion circuit 26.3
6 is a circuit that converts the signal into a signal suitable for import into the CPU 4. The phase pulse circuits 27 and 37 each receive the AC signal output from the filter circuits 24 and 34, detect the zero cross of the AC signal, and generate a rectangular wave pulse signal in which the high and low waveform levels are inverted at each detection. is output and input to the CPU 4. The CPU 4 has a function of receiving this rectangular wave pulse signal, calculating the rising point and falling point of the pulse signal, performing phase detection, and detecting the phase difference and frequency.

The setting circuit 5 is a zero-sequence current■. Setting value of, zero-sequence current■. This is a circuit for setting the setting value and setting time T of D.
The G test switch 6a is a manual switch for conducting a ground fault test, and the SO test switch 6b is a manual switch for conducting an overcurrent test. The display section 7 shows ■. Equipped with level display, power display, and forecast display. The output section 8 is equipped with a DG display due to ground fault detection and an SO display due to overcurrent, and also includes a relay for tripping in the event of a ground fault, a relay for tripping in the event of overcurrent, a relay for forecasting, an abnormality relay, etc. It is equipped with

The CPU 4 also includes a test signal generation circuit 9 and a test circuit.
Equipped with diagnostic circuit IO. The test signal generation circuit 9 is
For example, a current signal L for a four-stage self-test, and a voltage signal ■ for a self-test. occurs.

Current signal ■. is input to the test switching circuit 23, and the voltage signal ①o is input to the test switching circuit 33, respectively.

The test circuit/diagnostic circuit 10 is a general term for various diagnostic/test functions executed by the CPU 4, such as a constant voltage check function, a contact check function, a TC check function, and a universal function check.

In addition, this switch control device includes a filter circuit 11, a constant voltage circuit 12, and constant voltage level conversion circuits 13 and 14 as its own power supply section.

Note that a commercial power supply voltage is applied to the terminals P, , and P2, and a trip coil for interrupting the switch of the power supply system 1 is connected between the terminals V, , and V. TC detection circuit 15
is a circuit for detecting that a trip coil is connected to terminals V, , V,.

Next, the phase detection operation of the opening/closing control device of the above embodiment will be explained.

When a zero-sequence current is detected from the zero-sequence current transformer 2 and a zero-sequence voltage is further detected from the zero-sequence voltage detector, the filter circuit 24
．． 34 outputs a current signal 1 and a voltage signal 2 having waveforms shown in FIG. 3, respectively.

In response to this, the phase pulse circuits 27 and 37 detect the zero cross points of the input signals ■ and ■, respectively, and generate a half-cycle rectangular wave pulse signal ( (2, rp) in FIG. 3 are respectively output, and these rectangular wave pulse signals are input to the CPU 4. CPU
4, the rising and falling points of the rectangular wave pulse signals respectively input from the phase pulse circuits 27 and 37 are detected, and, for example, a phase difference is calculated.

Next, this phase difference calculation processing operation will be explained with reference to the flowchart shown in FIG.

The CPU 4 first determines whether there is a rising edge in either of the pulse signals input from the phase pulse circuits 27 and 37 [step ST (hereinafter referred to as ST) 1].
. When any of the rectangular pulse signals rises, the determination of this STI becomes YES, and then it is determined whether this signal is a ■ signal or not (5T2), as illustrated in FIG. If, for example, the voltage signal (2) rises at the point in time, the determination of Sr1 becomes YES, and the counter Cv is started here (Sr1).

Next, check whether the signal ■2 has risen or not (5T4)
, while the rise of the current signal ■2 is not detected, it is also determined whether the current lp has fallen next (5T5),
Sr1, S until a rising or falling edge is detected.
Repeat the determination of r1.

That is, depending on whether the current signal (2) is in a leading phase or a lagging phase with respect to the voltage signal V, it is determined whether the signal corresponds to falling or rising.

As illustrated in FIG. 3, when the current signal I lags behind the voltage signal V (for example, by an angle of φ), the current signal Ip rises after the voltage signal 2 rises. Expect it to go up.

In this case, the determination of Sr4 becomes YES, the content CV3 of the counter Cv at the time when it becomes YES is read, and this Cv3 is read.
The count value of v3 is multiplied by the angle R per count value 1 to calculate the phase angle φ, and the process proceeds to the next process (Sr9). In other words, in this case, if you start counting at the rising point of Vp and then stop counting when the rising point is detected in (2), the count contents are the count value corresponding to the phase difference φ, and the angle signal is applied. Thus, the phase angle φ can be calculated.

Next, for example, if the current signal has a phase advance with respect to the voltage signal, as illustrated in FIG. falls (tz point). Therefore, the determination of Sr4 and Sr1 is repeated until Sr1 determines whether I falls, and eventually, when the 9 signal falls, the determination of Sr1 becomes YES.
At this point, the contents Cvl of the counter Cv are stored in the memory (Sr1). As shown in FIG. 4, this count value corresponds to the period from when 2 rises to when 2 falls. Next, after that, it waits for the voltage signal 2 to fall (Sr7). ■When the signal 2 falls, that is, when it reaches the t1 point, the voltage signal ■
The content Cv□ of the count Cv corresponding to the half period of 2 is read and the calculation of Cv□-Cvl is performed (Sr8). Then, the value obtained by multiplying this calculated value by R is set as the phase angle φ. in this case,
This angle φ means that the current signal 2 is phase advanced by φ with respect to the voltage signal Vp.

The above has been explained based on the voltage signal ■2, taking as an example the case where the current signal is lagging phase and the case where the current signal is phase leading.
When using as a reference, after the rising edge is detected, the judgment of (①) becomes NO in Sr1, and the process moves to 5T11, and the judgment of (③) is made, but in this case, the judgment is YES, and the following is the same as the judgment made using the voltage signal. By performing the processing from Sr1 to Sr9 by reversing 1 and (2), it is possible to calculate the phase difference between the leading phase and the lagging voltage signal of the voltage signal with reference to the current signal (2).

Furthermore, although the above is a case where both the voltage signal and the current signal are based on the rising signal, when the operation starts,
If a falling signal is detected, the determination as to whether the STI has risen is No, and the process moves to 5TIO, where it is determined whether it is falling or not. If it is falling, the process is completely opposite to that of the rising signal. Therefore, the phase angle can also be calculated in the same way.

(f) Effects of the Invention According to the present invention, there is provided a phase pulse circuit that outputs a rectangular wave pulse signal whose waveform is inverted every time a zero cross point of an input AC signal is detected, and a rectangular wave pulse signal output from this phase pulse circuit. The present invention includes phase detection means for receiving a wave pulse signal, detecting the rising point and falling point of the rectangular wave pulse signal, and detecting the phase of the input signal based on these detection times. It is possible to perform at least phase detection for each page of the input AC signal. Therefore, even if an abnormality occurs in the middle cycle of phase detection operation, it is possible to perform stable operation from the arrival of the next half cycle. Since the detection process can be performed, there is an advantage that the operating time accuracy can be further improved compared to the conventional phase detection circuit.

[Brief explanation of drawings]

FIG. 1 is a flow diagram for explaining the phase detection processing operation of a switch control device according to an embodiment of the present invention, and FIG. 2 is a block diagram of an SOG type switch control device in which the present invention is implemented. 3 and 4 are waveform diagrams for explaining the phase detection operation of the SOG type switch control device of the above embodiment, and FIG. 5 is a waveform diagram for comparing and explaining the conventional and the present invention. . 1: Power supply system, 2: Zero-phase current detector, 3: Zero-phase voltage detector, 4: cPU, 20: First signal processing circuit, 30: Second signal processing circuit, 27/37: Phase pulse circuit . Patent Applicant Tateishi Electric Co., Ltd. Agent Patent Attorney Shigeru Nakamura Figure Figure v3

Claims (1)

[Claims] (1) A zero-phase current detector that detects the zero-phase current of the three-phase bus; a first signal processing circuit that receives and processes signals from the zero-phase current detector; and a zero-phase current detector that detects the zero-phase current of the three-phase bus; a zero-sequence voltage detector that detects voltage; a second signal processing circuit that receives a signal from the zero-sequence voltage detector and processes the signal; and a phase detector that detects a phase difference between the zero-sequence voltage and the zero-sequence current. a circuit, a means for determining whether or not the outputs of the first signal processing circuit, the second signal processing circuit and the phase detection circuit each exceed a predetermined value, and a determination result by the determination means; and a means for shutting off the switch of the bus bar in response to a determination output that the voltage is equal to or higher than a set value, the switch control device includes a means for shutting off the switch of the busbar in response to a determination output that the voltage is equal to or higher than a set value. a phase pulse circuit that outputs a pulse signal;
Phase detection means receives the rectangular wave pulse signal output from the phase pulse circuit, detects the rising and falling points of the rectangular wave pulse signal, and detects the phase of the input signal based on these detection points. A phase detection circuit for a switch control device, characterized by comprising: