JPH02271743A - Data communication system - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a transmission line by providing a digital interface device on each station and using an individual line channel in multiplex with a call control signal and a data control signal. CONSTITUTION:A data control signal and a call signal are sent to a controller CTL 6 via a CPU 15 with an exchange main body. The information is stored respectively to a data control signal storage circuit MD 5 and a call control signal storage circuit MC 4. A multiplexing circuit MUX 3 reads a signal in the MC 4, MD 5 to apply time division multiplex to generate an individual signal bit. Moreover, the MUX 2 multiplexes an input signal 13 from an exchange with a signal from the MUX 3 and sends the result to a digital transmission line 14. Moreover, a signal from the transmission line 16 is demultiplexed into a data channel signal and an individual line channel at an expansion circuit DMX. The digital interface device provided on each station is used in time division for the individual channel to effectively use the transmission line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data communication system, and particularly to a data communication system in a digital data communication network.

[Conventional technology]

Conventionally, in this type of data communication system, a data control signal is transmitted using at least one bit within the assigned channel, in addition to the individual call control bit assigned within the data channel for call control. It had become.

[Problem to be solved by the invention]

In the conventional data communication system described above, one bit of the bit string assigned to each channel is used for a call control signal, and at least one other bit is used for a data control signal. Generally, changes in data control signals are much smaller than changes in data signals, and call control signals can similarly be transmitted at low speeds.

Therefore, one bit is assigned to each of these low-speed control signals.
Conventional data communication systems that rely on digital transmission have the drawbacks of low efficiency in the use of digital transmission paths, and a reduction in the data transmission speed that can be handled by control signals.

[Means to solve the problem]

The data communication system of the present invention is a digital data communication network that performs data communication between a plurality of exchanges connected by a digital transmission path, in which each exchange has a data channel for transparently transmitting data and a call control signal for performing call control. The digital interface device includes a multiplexing means for time-division multiplexing a data control signal and the call control signal in data communication, and a The present invention is characterized in that it comprises a sending means for sending out an integrated signal to the individual line channel, and a separating means for separating a data control signal and a call control signal from the signal of the individual line channel.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a digital interface device showing an embodiment of the present invention, and FIG. 2 is a frame configuration diagram showing an example of a frame used in the digital interface device in FIG. 1.

In Fig. 2(a), an l frame has one individual line channel (hereinafter referred to as 5CH) and 30 data channels (hereinafter referred to as DC
HO, ~DCH29). The SCH collects n frames to form one multiframe (first multiframe) in order to transmit and receive call control signals and the like. Further, as shown in FIG. 2(b), three first multiframes 0, 1.2 are combined into a second multiframe. Note that in the second multiframe, the first multiframe 0.1 is allocated to the call control signal, and the first multiframe 2 is allocated to the data control signal. This allocation method can be arbitrarily set by changing the multiframe configuration, and it is also possible to further multiplex other signals.

Next, in FIG. 1, the digital interface device in this embodiment includes a driver (hereinafter referred to as DRV) 1, a multiplexing circuit (hereinafter referred to as MUX) 2, 3, a call control signal storage circuit (hereinafter referred to as MC) 4, and a data control signal A memory circuit (hereinafter referred to as MD) 5, a control device (hereinafter referred to as CTL) '6, a data control signal reception buffer (hereinafter referred to as BD) 7, and a call control signal reception buffer (hereinafter referred to as BD)
BC) 8, expansion circuit (DMX) 9.10,
Receiver (hereinafter referred to as RCV) 11 and timing generation circuit (
It is equipped with CTL6 and TMG
12 controls each circuit.

Next, the operation of this embodiment will be explained.

The operation in the direction from the exchange to the digital transmission line is as follows. Data control signals and call control signals are sent to the CTL 6 via the CPU bus 15 connected to the exchange main body.

CTL6 converts the sent information into MD5 and MC, respectively.
Store in 4. The first MUX 3 is used to create a second multiframe, reads out signals from MC4 and MD5 according to signals from TMG 12, performs time division multiplexing, and creates individual line channels. Second MUX2
multiplexes the input data signal 13 from the exchange and the signal from MUX 3 to create a first multiframe.

The signal from MUX2 is sent to the digital transmission path 14 via DRV1.

On the other hand, the signal from the digital transmission line 16 is converted into a unipolar signal by RCVll, and the signal of each channel is separated into a data channel signal and an individual line channel by the first DMXlo. The separated data channel signal is sent to the exchange as an output data signal 17, and the individual line channel is separated by the second DMX 9 into a data control signal and a call control signal, which are stored in BD7 and BO2, respectively. The CTL 6 reads data control signals and call control signals from the BD 7 and BO 8 and sends them via the CPU bus 15 to a control device (not shown) of the exchange.

The call is set by activating the MC 4 and sending out a call signal 1 selection signal in response to an instruction from the CTL 6. In the called exchange, CTL6 transmits the call control signal from the calling exchange to BO.
Read and receive calls via 8.

Notifies call control information such as selection signals to the exchange main body, and connects to extension data subscribers. Data control information from the extension data subscriber of the exchange is similarly sent to the CTL 6 via the CPU bus 15, and is sent to the CTL 6 through the MD5°MUX3, 2 . DRVI
The signal is sent to the digital transmission line 14 via. R in the game
CVI 1. DMXlo, 9. CTL6 via BD7
, the CTL 6 is sent via the CPU bus 15 to the control unit of the exchange and transmitted to the extension data subscriber at the opposing station.

In this embodiment, the controlled signal and data control signal are controlled and read by the CTL 6, but it is also possible to control this signal by placing it on a predetermined time slot inside the exchange. .

〔Effect of the invention〕

As explained above, the present invention improves the usage efficiency of the digital transmission path by time-division multiplexing the individual line signals of the digital interface device provided in each station with the call control signal and the data control signal. Since all bits within the channel can be used for data signals, this has the advantage of being able to handle data at higher speeds.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital interface device showing an embodiment of the present invention, and FIG. 2 is a frame configuration diagram showing an example of a frame used in the digital interface device in FIG. 1... Driver (DRV), 2.3... Multiplexing circuit (MUX), 4... Call control signal storage circuit <MC),
5... Data control signal storage circuit (MD), 6... Control device (CTL), 7... Data control signal reception buffer (BD), 8... Call control signal reception buffer (BC)
, 9.10... Deployment circuit (DMX), 11... Receiver (RCV) 1:2... Timing generation circuit (
TMG), 1 B...Input data signal, 14.16
...Digital transmission line, 15...CPU bus, 17.
...Output data signal.

Claims (1)

[Claims] In a digital data communication network that performs data communication between multiple exchanges connected by digital transmission paths, each exchange has a data channel for transmitting data transparently and an individual line channel for transmitting call control signals for call control. the digital interface device includes a multiplexing means for time-division multiplexing a data control signal in data communication and the call control signal; 1. A data communication system comprising: a sending unit for sending data; and a separating unit for separating a data control signal and a call control signal from the signal of the individual line channel.