JPS61171243A - Time slot assignment system of multi-channel frame - Google Patents

Abstract

PURPOSE:To realize multiplication of a channel generated intermittently with a good channel utilizing efficiency by describing a time slot and channel assignment information of the next frame to a header having a fixed length having plural split time slots. CONSTITUTION:The frame consists of a frame synchronizing pattern 22, a header 20 and a time slot 21 and the frame header 21 has assignment information of the time slot of the next frame in itself. The time slot and the channel assignment information are written in the frame header. Time slot is assigned for the share of the number of time slots used in each channel at the transmission side and the next frame is transmitted. The frame header is checked at the reception side, a channel used for the next frame is recognized to obtain the relation of time slot assignment of the next frame together with the number of time slots used by each channel known in advance.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an improved time slot allocation scheme for switched time division multiplexed channel frames.

In the case of time-division multiplex transmission, a fixed-length frame is divided into multiple time slots, and a channel is assigned to each of them.9 The assigned channel occupies the time slot of the frame regardless of whether it is used or not, so this method is effective. It would be desirable to provide a time slot allocation method to use.

[Conventional technology]

In the conventional single-line switchable type, a fixed time slot is retained while a call is being set up, and therefore a fixed time slot remains in use even when transmitted data is not being transmitted.

To improve this, a packet switching method was devised.

This method divides data into blocks, adds a destination, number, and other headers, and transfers them as packets at high speed via a storage/switching device. By finding an available line and sending it out, the efficiency of using the line is increased. It is something they are trying to sell.

[Problem that the invention seeks to solve]

For example, when multiplexing and transmitting several channels that occur intermittently, such as computer data or 051 voice, in the conventional eye-switching method, while the call is being set up, the time slot is used regardless of the presence or absence of information. The packet switching method does not improve the shortcomings of the same wire switching method, but because destination address information is added to each packet, the size of the packet is larger than the actual data to be sent. However, this does not necessarily improve the usage efficiency of the transmission line, and there are problems.

C. Means for Solving the Problem The above problem can be solved by the switching multiplex system according to the present invention in which the time slot and channel allocation information in the primary frame are written in the header of a fixed length frame having a plurality of divided time slots. This is solved by a channel frame time slot allocation method.

[Effect]

According to the present invention, by writing the time slot and channel assignment information in the primary frame in the header, the time slot is not fixed to a specific channel but can be dynamically assigned, so that multiplexing of channels that occurs intermittently can be avoided. to achieve efficient line usage.

〔Example〕

The gist of the present invention will be explained in detail according to embodiments shown in the figures.

FIG. 1 is a block diagram showing the configuration of the transmitter. In the figure, 1-3 is a terminal device, 4-6 is a storage circuit included in the terminal ink face and temporarily stores signals from each terminal, 7 is a switch, 8 is a switch control circuit, and 9 is a storage circuit that stores terminal data. Frame buffer A that uses bits
12 is a frame header buffer 8, which stores values related to time slot and channel assignment of contents to the frame header buffer! , 13 is the next frame G created with the previous frame buffer 8, and frame buffer B to be dilated.
, 154. Memo January 2 and 1 with t frame sending buffer
The contents of 3 are copied. Reference numeral 16 denotes a transmission line correspondence unit that sends the contents of the frame transmission buffer to the transmission line 17 over time.

Frame buffer A and 81 frames to Sota Pa Sofa A
, frame transmission buffer, etc., or data storage is performed via the bus line 19 under the control of the CPU.

The operation of constructing a frame by constructing signals from a plurality of terminal devices is as follows. J
Signals from each terminal device 1-3 are temporarily stored in the storage device 4-5, and wait for polling of the switch 7. A predetermined amount of data is stored in the frame buffer A under the control of the Sui-Nona control 101 and path 8. .

The switcher controller path 8 is set by the CPII 18 to determine the amount of data to be retrieved from the storage device 4-5.

The data in the frame buffer is transferred to the memory area 13 of the frame buffer H by the direct memory access controller 14, and the frame header is transferred to the memory area 13 of the frame buffer H by the direct memory access controller 14.
Memory area 1 to frame header buffer by H
2 is written.

Next, the contents of frame header buffer A 12 and frame buffer B 13 are transferred to frame transmission buffer 15 by the action of direct memory access controller 14.
will be forwarded to.

FIG. 2 shows a combined block diagram of the transmitter and receiver.

In the figure, the same parts as in FIG. 1 are designated by the same numbers.

The reception section includes a transmission path correspondence section 116 and a frame reception buffer l.
15, frame header buffer B 112 , frame buffer C 113 , frame buffer allo 109 , terminal interface 104-106 , terminal device 101-10
Has 3.

The operation of the receiving section is the opposite operation of the transmitting section. When the frame is received in the frame reception buffer 115, the frame is transferred to the frame buffer c113.

The reception control unit 118 spends the time corresponding to the next frame checking the contents of the frame header buffer 8112 and prepares to separate the data within the frame for each channel. Then, in the next frame, frame buffer C11
3 is copied to the frame buffer D 109, and by performing this preparation, the data within the frame is separated into each channel.

Next, the frame structure will be explained according to FIGS. 3 to 5. In this example, a transmission line with a transmission speed of 6144 bps is used at 190 bps.
Divide into 190 time slots and dynamically divide these 190 time slots into multiple channels;
An example of transmission will be explained below.

FIG. 3 is a frame configuration diagram. A frame consists of a frame synchronization pattern 22, a header 2o, and a time slot 21, and the frame header 21 contains therein information about the allocation of time slots for the next frame. In this embodiment, the frame length is 8 ms, so the receiver prepares for time slot assignment in the next frame within Hms after receiving the frame header.

Within one frame, there are 256 timeslots for each time slot.

FIG. 4 shows the configuration of the frame header. The allocation relationship between time slots and channels is written in this frame header.

CHI CH2---CHN
If CHnl CHn2 --- CHnk is 1-fixed chip p7M, ) Lt (K≦N) uses the next frame, nl n2-nk is written in the channel number field of the header.

On the transmitting side, as many times as the number of time slots used in each channel of CHTII CHn2---CHnk,
Time slot allocation is performed as shown in FIG. 5, and the next frame is transmitted.

For example, CHn5 has 10 time slots 13th-22nd time slots (TSI) out of 190 time slots.
3-22).

On the receiving side, the frame header is checked and the channel to be used for the next frame is C) InI C) In2-~-C
Hnk, and together with the previously known number of time slots used by each channel, determine the time slot allocation relationship for the next frame.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to multiplex a large number of channels in which information is generated intermittently and to use the transmission path efficiently, and its effects are extremely large.

[Brief explanation of drawings]

Figure 1 is a block diagram of the transmitter, Figure 2 is a block diagram of the transmitter and receiver, Figure 3 is a frame diagram, Figure 4 is a frame header diagram, Figure 5 is a frame diagram. Assignment configuration of time slots in
Figure 1. In the figure, 1-3.101-103 is a terminal device, 4-6.104-106 is a terminal interface, 7 is a switch, 8 is a switch control circuit, 9 is a frame buffer 8, and 10 is from the terminal device 1-3. Data amount designation part, 12 is 7 buffer A to the frame. 13 is a frame buffer B1 14 is a direct memory access controller, 15 is a frame transmission buffer, 16.116 is a transmission path corresponding unit, ]7, ]17 is a transmission path, 18 is a transmission control unit CPU, 19 is a bus, 20 is a header , 21 time slot, TSI)-TSI) i9 is the time slot number, 22 is the frame synchronization pattern, 109 is the frame buffer D1, 112 is the frame ladder buffer 8, l13 is the frame buffer C1, 115 is the frame reception buffer, l18 is the reception control. Department.

Claims (1)

[Claims] A time slot allocation method for a multi-channel frame, characterized in that time slot and channel allocation information for the next frame are written in the header of a fixed length frame having a plurality of divided time slots.