JPH0226814B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention is a large-scale integrated circuit (hereinafter referred to as LSI)
This invention relates to a power-on reset circuit that can be implemented on-chip without any external components.

An example of a conventional power-on reset circuit is shown in FIG.
The output terminal of the inverter 5 is connected to the input terminal of the cascade-connected inverters 4 and 5, and the output signal of the inverter 5 is used as a power-on reset signal to the signal output terminal 7.
It is configured to occur more frequently. As a result, as shown in FIG. 2, even after the power applied to the power supply input terminal 6 reaches a normal potential, the potential of the input of the inverter 4 is maintained at its threshold voltage V _T
The time constant of resistor 1 and capacitor 2 of time constant circuit 3 is set large so that the time constant of resistor 1 and capacitor 2 of time constant circuit 3 becomes lower than that of A power-on reset signal PR is generated. In addition, in FIG. 2, V _DD is the voltage waveform of the power supply applied to the power input terminal 6, V ₁ is the input voltage waveform of the inverter 4 at point a in FIG.
PR represents the power-on reset signal waveform obtained at the signal output terminal 7, and To represents the power-on reset time.

However, in conventional circuits configured in this way, when a relatively long power-on reset signal is required or when it takes a long time for the power supply to reach the normal potential, it is necessary to increase the values of resistor 1 and capacitor 2. The time constant must be increased. As an example
If a time constant of 10 ms or more is required, a 10 KΩ resistor 1 and a 10 μF capacitor 2 are required, which makes it extremely difficult to incorporate these on-chip into an LSI, and they have to be externally connected.

In view of the above points, the present invention was made in order to solve the conventional drawbacks.The purpose of the present invention is to perform stable operation with respect to the power supply, and to be able to incorporate it into an LSI on-chip without external components. The object of the present invention is to provide a power-on reset circuit that can perform a power-on reset circuit.

Another object of the present invention is to provide a power-on reset circuit that can provide a relatively long power-on reset time with a small-scale circuit.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 3 is a circuit diagram showing the basic configuration of a power-on reset circuit according to the present invention, and FIG. 4 is a circuit diagram showing a specific embodiment thereof. In these figures, reference numeral 11 denotes a flip-flop (FF) having reset and preset functions. This flip-flop 11 consists of a D-type flip-flop 31 with one reset terminal, and its D input terminal is connected to the power supply terminal 16, and the clock input terminal is connected to the power supply terminal 16. A count output of a counter described later as C is input. 1
2 is a counter consisting of a plurality of D-type flip-flops 32a to 32n with reset terminals;
A first switch 13b uses a PMOS transistor 33 and its gate serves as a control terminal, and 13b is a PMOS transistor 34 similar to the first switch 13a.
This is a second switch whose gate serves as a control terminal, and the first and second switches 13a, 1
3b, those gates are Low (hereinafter referred to as "L")
It consists of PMOS transistors 33 and 34 that are turned on when the voltage is high and turned off when the voltage is high (hereinafter referred to as "H"). In addition, 14 connects the gate of the PMOS transistor 35 to the ground (GND), and connects the source of the PMOS transistor 35 to ground (GND).
A resistor element 15 that uses on-resistance between drains is an inverter with a large noise margin when the input is "L", and this inverter 15 includes a PMOS transistor 36, a first NMOS transistor 37,
The second NMOS transistors 38 are connected in series in this order, and the second NMOS transistors 38
The gate of is connected to the connection point of the first and second NMOS transistors 37 and 38. and,
The source of the PMOS transistor 36 is connected to the power supply terminal 16 to which power is applied, the source of the second NMOS transistor 38 is connected to the ground (GND),
The gates of the PMOS transistor 36 and the first NMOS transistor 37 are connected and used as an input, and the PMOS transistor 36 and the first NMOS transistor 3
The connection point of the drain of 7 is the output.

In the circuit having such a configuration, the output terminal of the flip-flop 11 having reset and preset functions is connected to the control terminal of the first switch 13a, and one terminal of the first switch 13a is connected to the power supply terminal 1.
6, and the other terminal is connected to one terminal of the resistance element 14, and the other terminal is connected to one terminal of the resistance element 14.
The other terminal of 4 is grounded. Further, a second switch 13b is connected in parallel to the first switch 13a, and the first switch 13b is connected in parallel to the first switch 13a.
A connection point between 3 a and 13 b and a connection point between resistance element 14 are connected to an input terminal of inverter 15 . The output terminal of this inverter 13 is connected to the second switch 1
The control terminal 3b is connected to each reset terminal R of the flip-flop 11 and the counter 12, and the output of the flip-flop 11 is taken out from the signal output terminal 17 as a power-on reset signal. Note that the count output Q of the counter 12 is input to the clock input terminal C of the flip-flop 11. Further, the counter 12 has a clock input to its terminal C via the clock input terminal 10, and this clock may be generated by an external or internal separate circuit.

Next, the operation of the above embodiment will be explained with reference to FIG. FIG. 5 shows changes in voltage at each terminal of the flip-flop 11, with time on the horizontal axis and voltage on the vertical axis, where V _DD is the power supply voltage applied to the power supply terminal 16, and FR is the reset voltage of the flip-flop 11. The signal FS indicates the set signal of the flip-flop 11, and _PR1 indicates the power-on reset signal waveform of the signal output terminal 17, respectively. here,
Let the threshold voltages of the PMOS transistor and NMOS transistor be −V _TP and V _TN, respectively. In a normal CMOS process, V _TP and V _TN are almost equal. Even when power is not applied to the power supply terminal 16, the gate of the PMOS transistor 35 constituting the resistance element 14 is grounded, so the input of the inverter 15 (hereinafter referred to as A
point) is at a potential higher than V _TP .
PMOS transistor 35 turns on and lowers the potential at point A to V _TP .

Next, when power is applied to the power supply terminal 16, the inverter 15 outputs an input voltage as shown in FIG.
Outputs the same voltage as the power supply until it reaches 2V _TN . And when the input voltage becomes more than 2V _TN , V _TN
Outputs a voltage of about On the other hand, flip-flop 11, counter 12 and switches 13a, 13
Internal circuits such as b operate normally when the power supply voltage exceeds the larger value of either V _TP or V _TN (this value is defined as V _nax ). Therefore, from the time when the power supply voltage V _DD reaches V _Tnax until the point A reaches 2 V _TN as shown in FIG. 5, the reset signal FR is output to the flip-flop 11 and the counter 12, and these are reset. , the output Q of the flip-flop 11 becomes "L", and a power-on reset signal _PR1 is generated as shown in FIG.
At this time, the first switch 13a connected to the output terminal of the flip-flop 11 is turned on. (On resistance of each switch 13a and 13b)
If the design is made so that <<(resistance of the resistance element 14), the potential at point A will rise almost to the power supply voltage, and
When the power supply voltage exceeds 2V _TN , inverter 15
The output becomes approximately _VTN , and the reset signal FR is released as shown in FIG. Note that V _TN is within the noise margin of the flip-flop 11 and counter 12 on the "L" side.

When the output of the inverter 15 is V _TN , the second switch 13 connected to its output terminal
b is turned on, and the point A is maintained at the power supply voltage level regardless of whether the first switch 13a connected to the flip-flop side is on or off. Therefore, from now on, the output of the inverter 15 is _VTN until the power is removed, and the flip-flop 11 and counter 12 are not reset.

As shown in FIG. 5, the counter 12 starts counting clocks after the reset signal FR is released, and resets the flip-flop 11 after counting n clocks (determined by the counter configuration). As a result, when the flip-flop 11 is set, the power-on reset signal _PR1 is released. Thereafter, the power-on reset signal _PR1 will not be generated until the power is removed and reapplied. As a result, a power-on reset signal _PR1 having a power-on reset time _T2 shown in FIG. 5 is obtained from the signal output terminal 17 connected to the output terminal of the flip-flop 11. In FIG. 5, _T1 indicates the reset time of the flip-flop 11.

According to the above embodiment, the flip-flop 11, the counter 12, the first and second switches 13a and 13b, the inverter 15, and the resistance element 14 having a low frequency and high resistance make it possible to operate the flip-flop regardless of the rising speed of the power supply voltage. 11 and counter 12, the clock is counted by the counter 12, and the flip-flop 11 is set by the count output, so that the output while the flip-flop 11 is being reset is used as a power-on reset signal, and a long power-on reset is performed. time can be obtained with small-scale circuits. Furthermore, since it can be constructed using only transistors, it can be integrated into an LSI on-chip without any external components, and the circuit size can be reduced.

In the embodiment shown in FIG. 4, the counter 12 is provided, but the counter 12 can be omitted as shown in FIG.

In addition, if the rise speed of the power supply is very fast and the time from when the power supply reaches V _Tnax until the point A reaches 2V _TN becomes short and the flip-flop 11 and counter 12 cannot be reset completely, the resistance element 14 You can connect a capacitor in parallel to delay the time it takes for point A to reach 2V _TN . In this case, the time required for resetting the flip-flop 11 and the counter 12 is several tens of nanoseconds, so the capacitance may be as small as several pF or less.

FIG. 6 is a circuit diagram showing another example of the power-on reset circuit according to the present invention, and FIG. 7 is a circuit diagram of a specific embodiment thereof. In this embodiment, a variable resistance element is used instead of the resistance element 14. 21 constitutes a bootstrap circuit 22, and the other configurations are the same as the circuit shown in FIG. The variable resistance element 21 is composed of a PMOS transistor 40, and its on-resistance is variably controlled by a voltage applied to the gate serving as a control terminal. And the PMOS transistor 4
A voltage applied to the gate of 0 is generated by a bootstrap circuit 22. This bootstrap circuit 22 includes first to third PMOS transistors 4
The first PMOS transistor 41, the capacitor 51, and the second PMOS transistor 42 are connected in series in this order.
The source of the second PMOS transistor 41 is connected to the power supply terminal 16 to which power is applied, and the drain of the second PMOS transistor 42 is connected to the ground (GND). Furthermore, the capacitor 51 and the second PMOS
A third PMOS transistor 43 is connected in parallel with the transistor 42, and the gates of the first to third PMOS transistors 41 to 43 are grounded (GND).
The connection point between the capacitor 51 and the second PMOS transistor 42 is used as the output of the bootstrap circuit. In the figure, the same parts as in FIGS. 3 and 4 are designated by the same reference numerals.

Next, the operation of the above configuration will be explained. however,
The operations of the circuits other than the variable resistance element 21 and the bootstrap circuit 22 are completely the same as in FIG. 4, and will not be described here. A first PMOS transistor 41 and a capacitor 51 that constitute the bootstrap circuit 22
The connection point of
The connection point between 2 and the capacitor 51 is designated as point C. Power terminal 1
When power is applied to 6, point B becomes the power supply voltage, and point C becomes the potential of V _TP . This point C is the PMOS transistor 40 that constitutes the variable resistance element 21.
Since the gate of the PMOS transistor 35 is connected to the gate of the PMOS transistor 35 and V _TP >0, the on-resistance of the PMOS transistor 40 is higher than that of the case shown in FIG. 4 (the gate of the PMOS transistor 35 is grounded). On the other hand, when the power supply is removed, the third PMOS transistor 43 is on, so the potential at point B drops to V _TP (when the potential at point B drops to V _TP , the third PMOS transistor 43
PMOS transistor 43 is cut off).
At this time, when the power supply voltage is V _DD and the capacitance value of the capacitor 51 is Cc, the capacitor 51 has accumulated a charge of (V _DD −V _TP )×Cc, so the potential at point C (−V _DD
+2V _TP ), typically −V _DD +2V _TP <−V _TP
Therefore, the second PMOS transistor 42 is cut off and the on-resistance of the PMOS transistor 40 is lowered. As a result, the inverter 15
can discharge the input (point A) to the GND level.

In this way, when the power source is at a normal voltage, the resistance value of the variable resistance element 21 is increased to reduce the flowing current, and when the power source is removed, the resistance value of the variable resistance element 21 is lowered to ensure a stable and stable power source. On the other hand, it is possible to provide a power-on reset circuit that has improved followability and can operate at low power and high speed.

Note that in the above embodiment, the inverter is PMOS
It can be configured with CMOS transistors, NMOS transistors, switches, and resistive elements.
Although a case has been shown in which the inverter, switch, resistance element, etc. are constructed using PMOS transistors, it goes without saying that these inverters, switches, resistance elements, etc. may be constructed using other transistor elements.

As explained above, since the power-on reset circuit of the present invention can be constructed only from transistors, it can be implemented on-chip in an LSI without any external components, and the circuit size can also be reduced. Furthermore, since the pulse width of the power-on reset signal can be arbitrarily determined by the clock frequency and the counter frequency division number, a long power-on reset time can be easily achieved, and it can be realized with a small-scale circuit. It has excellent effects.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional example, FIG. 2 is a voltage waveform diagram of each part of FIG. 1, and FIG. 3 is a circuit diagram showing the basic configuration of a power-on reset circuit according to the present invention.
FIG. 4 is a circuit diagram showing a specific embodiment of FIG. 3;
5 is an explanatory diagram of the operation of FIG. 4, FIG. 6 is a circuit diagram showing another example of the power-on reset circuit according to the present invention, and FIG. 7 is a circuit diagram showing a specific embodiment of FIG. 6. be. 11...Flip-flop, 12...Counter, 13a...First switch, 13b...Second
switch, 14... resistance element, 15... inverter, 16... power supply terminal, 21... variable resistance element, 22... bootstrap circuit.

Claims (1)

[Scope of Claims] 1. A flip-flop having reset and preset functions; a second switch, a resistive element having one terminal connected to the other terminal of the first switch and the other terminal grounded, and a control terminal connected in parallel to the first switch. and an inverter in which a connection point between the first and second switches and the resistance element is connected to an input terminal, and an output terminal of the inverter is connected to the second switch.
By connecting the control terminal of the switch and the reset terminal of the flip-flop, the output of the flip-flop from the time when power is applied until the set signal for the flip-flop is input is generated as a power-on reset signal. A power-on reset circuit featuring: 2 a flip-flop having reset and preset functions, a first switch having a control terminal and a pair of terminals, the control terminal being connected to the output terminal of the flip-flop, and one terminal of which is connected to a power supply; a resistance element having one terminal connected to the other terminal of the first switch and the other terminal being grounded, and having a resistance value control terminal, the resistance value of which can be varied by the voltage value of this terminal; a second switch having a control terminal connected in parallel to the first switch; an inverter having an input terminal connected to a connection point between the first and second switches and the resistance element; and a control circuit for controlling the resistance value of the resistor element by connecting its output to the resistance value control terminal of the resistor element, and connecting the output terminal of the inverter to the control terminal of the second switch and the flip-flop. By connecting to the reset terminal, the output of the flip-flop is generated as a power-on reset signal after the power is applied until the set signal of the flip-flop is input, and when the power supply is at a normal voltage, the resistance value is The control circuit and the resistor element are characterized in that the resistance value thereof is increased to reduce the current, and when the power source is removed, the resistance value of the resistor element is lowered to increase the flowing current. Power-on reset circuit. 3 a flip-flop having reset and preset functions; a first switch having a control terminal and a pair of terminals, the control terminal being connected to the output terminal of the flip-flop and one terminal connected to a power supply; a second switch having a resistive element having one terminal connected to the other terminal of the first switch and the other terminal being grounded; and a control terminal connected in parallel to the first switch; It consists of an inverter whose input terminal is connected to the connection point between the second switch and the resistance element, and a counter which receives a clock as input and sets the flip-flop by its count output. By connecting the control terminal of the second switch to the reset terminal of the flip-flop and counter, the flip-flop and the counter are reset by applying power until the flip-flop is set by the count output of the counter. A power-on reset circuit characterized in that the output of the flip-flop is generated as a power-on reset signal.