JPH022673A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase an operation speed by reducing impurity concentration of a channel stopper region defining the surrounding of a memory cell compared with that defining the surrounding of a semiconductor element of a peripheral circuit and further reducing operation voltage applied to a data line connected to an operation region of the memory cell compared with that used by the peripheral circuit. CONSTITUTION:In the title semiconductor integrated circuit device wherein the respective surroundings of semiconductor elements forming peripheral circuits such as a memory cell M, in which a memory cell array MA is connected to an extending data line, and a decoder circuit, etc., are defined by a field insulating film 6 and channel stopper regions 4, 5, impurity concentration of the channel stopper region 4 that defines the surrounding of the memory cell M is reduced compared with impurity concentrations of the channel stopper regions 4, 5 that defines the surroundings of the semiconductor elements of the peripheral circuits, and further operation voltage applied to the data line is lower than operation voltages used in the peripheral circuits. Hereby, pn junction capacitor between the operation region of the memory cell and the channel stopper region defining the surrounding of the operation region of the memory cell is reduced to reduce the load capacity of the data line, thereby the operation speed being increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device having a memory circuit.

[Conventional technology]

Vertical mask ROM (ReadOn
ly Memory) has a human figure of 1 or 4 [Mbitl]. 1 of this type of vertical mask ROM [bi
The memory cell that forms the information of [t] is one MISFET.
It was 4t+ drilled. 8, 16 or 32 memory cells are connected in series depending on the number of output bits.

Of the plurality of memory cells connected in series, a data line is connected to the memory cell at one end with a column select MISFET interposed therebetween. A source a (ground potential) is connected to the memory cell on the other end side.

Each of the memory cells arranged in the memory cell array of the vertical mask ROM is an n-channel MISFET. This MI S FET is surrounded by a field insulating film and a channel stopper region, and is electrically isolated from other regions. The field insulating film is formed of, for example, a relatively thick silicon oxide film. The channel stopper region is of the same electrocardiographic type as the p-type semiconductor substrate (or p-type well region), and has a slightly higher impurity concentration than that of the p-type semiconductor substrate (or p-type well region). The channel stopper region is a parasitic MO3 formed by a semiconductor substrate, a field insulating film, and wiring (for example, a word line or a data line) extending above it.
is configured to increase the threshold voltage of.

The field insulating film and channel stopper region that define the periphery of the memory cell are formed in the same manufacturing process as that of an n-channel MISFET that constitutes a peripheral circuit such as a decoder circuit.

In addition, regarding the vertical mask ROM, for example.

National Technical Report Volume 32 No. 1 1986
February 2016 (National Technical Re
portVol.32 No.l Feb. 1986)
It is described in.

[Problem to be solved by the invention]

The inventors of the present invention have discovered that the following problems arise as the capacity of the vertical mask ROM increases.

In the vertical mask ROM, the impurity concentration in the channel stopper region that defines the periphery of each of the memory cell and the MISFET of the peripheral circuit tends to increase due to the increase in the density associated with the increase in capacity. this is.

This is to prevent the ON operation of the parasitic MO3 due to a reduction in the dimensions of the field insulating film, that is, a reduction in the gate length of the parasitic MO8, and a change in the field insulating film to a 1itt film. When the impurity concentration of the channel stopper region increases, the pn junction capacitance between the source region and the train region of the MISFET, which is a memory cell, increases. Since it is added to the data line connected to this pnn junction capacitance memory cell, the load capacitance of the data line increases and the information reading operation speed decreases.

Especially this type of large capacity vertical mask ROM.

In order to prevent the short channel effect, the semiconductor substrate is formed with a high impurity concentration. For this reason, the pn junction capacitance between the source region and drain region of the MISFET, which is a memory cell, and the semiconductor substrate increases, so that the above-mentioned problem occurs significantly.

In addition, the inventor considered setting the impurity concentration of the channel stopper region low in order to solve the above-mentioned problem, but since the parasitic MO8 is likely to turn on and cause DC launch-up, the vertical mask There remains the problem of lowering the electrical reliability of the ROM.

Furthermore, in order to similarly solve the above-mentioned problem, the inventor considered dividing the data line to reduce the load capacity of one divided data line, but since the number of decoders would increase, the vertical The problem remains that the degree of integration of the mask ROM is reduced.

An object of the present invention is to provide a technique that can increase the operating speed of a semiconductor integrated circuit device having a memory circuit.

Another object of the present invention is to provide a technique capable of achieving the above object, improving electrical reliability, and increasing the degree of integration in a semiconductor integrated circuit device having the above memory circuit. be.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

In a semiconductor integrated circuit device having a memory circuit, the impurity concentration of a channel stopper region defining a periphery of a memory cell is lower than that defining a periphery of a semiconductor element of the peripheral circuit, and the channel stopper region is connected to an operating region of the memory cell. The operating voltage applied to the data line is lower than that used in the peripheral circuit.

Further, the operating voltage applied to the word line connected to the memory cell is lower than that used in the surrounding circuit.

[For production]

According to the above-described means, it is possible to reduce the pn junction capacitance between the operating region of the memory cell and the channel stopper region that defines the periphery thereof, and to reduce the load capacitance of the data line, thereby increasing the operating speed. In addition to being able to
Parasitic MO with data a (or word line) as the gate electrode
Since the ON operation of 5 can be prevented, DC latch-up can be prevented and electrical reliability can be improved.

As a result, the load capacitance can be reduced without dividing the data line, so that it is possible to prevent the degree of integration from decreasing due to division of the data line.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a vertical mask ROM.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

The structure of a vertical mask ROM which is an embodiment of the present invention is shown in a second example.
It is shown in the figure (equivalent circuit diagram).

The memory cell M that forms 1 bit information of the vertical mask ROM is an n-channel MISF as shown in FIG.
It is composed of ET. 8, 16 or 32 memory cells M are connected in series depending on the number of output bits.

A plurality of memory cells M are arranged in rows and columns to form a memory cell array (memory cell mat>MA).

The drain region of the memory cell M on one end side among the plurality of memory cells M connected in series is a column select M I
It is connected to the common data 1itcDL through the SFE TQcs and the column switch Qc. MISFETQcs for column selection is
Composed of n channels, enhancement type MIS
It is configured as a set of FET and depletion type MISFET. The column switch Qc is controlled by a Y-8W signal from a column decoder circuit (not shown). Among the plurality of memory cells M connected in series, the source region of the memory cell M on the other end side is connected to a source line, that is, a reference voltage (for example, circuit ground potential 0 [V]).++ff Me common data Line CDL is connected to sense amplifier circuit SA2 via current sense amplifier circuit SAI. Current sense amplifier circuit S
A1 is an enhancement type n-channel MIS F
It is composed of E T Qsa, Qsb and a depletion type n-channel MISFET Qsc. M.I.
A power supply voltage Vcc, for example, a circuit operating voltage 5 [■] is applied to one end of each of S FET Qsa and Qsc. The current sense amplifier circuit SAI is configured to apply a data line potential to the common data line CDL, read the data line potential of the common data line CDL, and output this information to the sense amplifier circuit SA2. This current sense amplifier circuit SAI is M I
The threshold voltages (Vth) of S F E T Qsa, Qsb, and Qsc are controlled, and the common data line C
It is configured to clamp the potential of DL to a low potential. In other words, the current sense amplifier circuit SAI constitutes a low voltage clamp circuit. This current sense amplifier circuit SAI sets the potential of the common data line CDL (node at point d) to 1 to 2 [V] (1.2 [V] in this embodiment).
It is configured to clamp to a low potential of .

The sense amplifier circuit SA2 is configured to amplify the potential of the common data line CDL read by the current sense amplifier circuit SAI using a differential amplifier and output it to an output buffer circuit (not shown).

M I, which is the plurality of memory cells M connected in series;
The gate electrodes of the S FETs are connected to the two word driver MISFETQd via the word line WL, and the 62 word driver MISFETQd are controlled by a row decoder circuit R-Dec. One of the two word driver MISFETQd is connected to a reference voltage circuit that applies a reference voltage to the word line WL.

The other word driver MISFETQd is connected to the word line W.
It is connected to a voltage clamp circuit that applies an operating voltage clamped to a low voltage to L. This voltage clamp circuit is configured to apply a voltage, for example, 3 to 4 [V] lower than the operating voltage Vcc of the peripheral circuits to the word line WL.

Next, the specific 4iI7 structure of the vertical mask ROM will be briefly explained with reference to FIG. 1 (a sectional view of main parts).

As shown in FIG. 1, the vertical mask ROM is composed of a p° type semiconductor substrate 1 made of single crystal silicon. A p-type well region 3 is formed in the n-channel MISFET formation region of semiconductor substrate 1, and an n-type well region 2 is formed in the p-channel MISFET formation region.

Memory cells M arranged in memory cell array MA are formed on the main surface of p-type well region 3 within a region defined by field insulating film 6 and p-type channel stopper region 4 . In other words, memory cell M (MIS
FET) is mainly located in the P-type well region 3. Gate insulating film 7. It is composed of a gate voltage tfi8, a pair of n-type semiconductor regions 9 serving as a source region and a drain region, and a pair of n°-type semiconductor regions 12. The n-type semiconductor region 9 is formed in self-alignment with the gate electrode 8, and the n-type semiconductor region 1
2 is a side wall spacer formed on the side wall of gate pole 8! It is formed by self-alignment with respect to ■. This memory cell M is not limited to this structure, but is an LDD (Lig.
It is composed of a (first opened drain) structure.

Column selection M arranged in memory cell array MA
Like the memory cell M, the I S F E TQcs is formed on the main surface of the p-type well region 3 in a region defined by the field isolation MIIu6 and the p-type channel stopper region 4. In other words, the column selection MISFETQcs is located in the p-type well region 3. It is composed of a gate insulator 1 7, a gate electrode 8, a pair of n-type semiconductor regions 9 serving as a source region and a drain region, and a pair of n°-type semiconductor regions 12.

Memory cells M arranged in these memory cell arrays MA
, the channel stopper region 4 that defines the periphery of each of the column select MISFETQcs is formed in one impurity introduction step, as will be described in detail later.

an n-type semiconductor region (drain region) of a memory cell M on one end side of the plurality of memory cells M connected in series;
12 is connected to a wiring 16, which is a common data line CDL, with a column select MISFET Qcs and a column switch Qc (not shown) interposed therebetween. Wiring 16 is 1
It extends over the interlayer insulating film 14 and is connected to the n-type semiconductor region 12 through a connection hole 15 formed in the interlayer insulating film 14 . In addition, the source 4! in the n-type semiconductor region (source region) 12 of the memory cell M on the other end side A wiring 16 (j) in SL is connected. The wiring 16 is formed of, for example, an aluminum alloy film.

The n-channel MISFETQn of the peripheral circuit is connected to a field insulating film 6. It is formed on the main surface of p-type well region 3 within a region defined by p-type channel stopper regions 4 and 5 . The peripheral circuit is a row decoder circuit R-
Dec, current sense amplifier circuit SAI, sense amplifier circuit SA2, etc.

This circuit is arranged around the memory cell array MA. This n-channel M I S F E T Q n is
Mainly p-type well region 3. Gate insulating film 7, gate electrode 8. A pair of n-type semiconductor regions 9, which are a source region and a drain region. It is composed of a pair of n-type semiconductor regions 12. A wire 116 is connected to the n-type semiconductor region 12 .

The p-channel MISFET Qp of the peripheral circuit is formed on the main surface of the n-type well region 2 in a region surrounded by a field insulating film 6.

In other words, the p-channel MISFET QP mainly consists of the gate insulating film 7. It is composed of a gate electrode 8, a pair of p-type semiconductor regions 1o serving as a source region and a drain region, and a pair of p-type semiconductor regions 13. A wiring 16 is connected to the p' type semiconductor region 13.

n-channel M I S F E T Q of the peripheral circuit
Channel stopper regions 4 and 5 define the periphery of n.

It is formed by two impurity introduction steps, and has a higher impurity concentration than channel stopper region 4 formed in memory cell array MA.

In other words, the channel stopper region 4 formed in the memory cell array MA has a lower impurity concentration than the channel stopper regions 4 and 5 of the peripheral circuit.

II? Passivation films 17 and 18 are sequentially laminated on the wiring 16 connected to each semiconductor element f. The passivation film 17 is formed of, for example, a silicon nitride film deposited by plasma CVD with high moisture resistance. Passivation 1 18 has, for example, an external stress absorbency of a
It is made of a polyimide resin film.

In this way, in the vertical mask ROM, the memory cell M
(MISFET) The impurity concentration of the channel stopper region 4 that defines the periphery of the n-channel M I of the peripheral circuit is
The operation applied to the common data 1cDL connected to the n'-type semiconductor region (operation region) 12 of the memory cell M, which is lower than the channel stopper regions 4 and 5 defining the periphery of the S F E T Q n. By lowering the voltage compared to the operating voltage Vcc used in the peripheral circuit, the memory cell M (column select MISFETQ
The pn junction capacitance between the n-type semiconductor region 12 and the channel stopper region 4 (same for cs) can be reduced compared to that of the peripheral circuit, and the load capacitance of the common data line CDL can be reduced, so the information read operation speed can be reduced. Since it is possible to increase the speed of operation and prevent the ON operation of the parasitic MOS, it is possible to prevent DC latch-up and improve the '61 reliability. The parasitic MOS has a common data line CDL as a gate electrode (M), a field insulating film 6 as a gate insulator v4(0), and a channel stopper region 4 as a gate electrode (M).
are each configured as a semiconductor (S). That is, the vertical mask ROM aims to increase the operating speed by lowering the impurity concentration of the channel stopper region 4 of the memory cell array MA to reduce the parasitic capacitance as much as possible, and the operating speed used in the memory cell array MA is increased. is set low to prevent the parasitic MOS from turning on due to the low impurity concentration of the channel stopper region 4.

This ON operation of the parasitic MO5 can also be prevented by clamping the voltage applied to the word line WL to a low potential.

Therefore, the vertical mask ROM can reduce the load capacitance without dividing the common data line CDL, thereby preventing an increase in the number of decoder circuits due to division of the common data line CDL and improving the degree of integration. be able to.

FIG. 3 shows the relationship between the impurity concentration of the channel stopper region and the access time. As shown in FIG. 3, when the impurity concentration of the channel stopper region of the memory cell array MA is lowered as in this embodiment (A), the access time can be made faster than in the conventional case (B).

Further, FIG. 4 shows the relationship between the waveform of information input to the sense amplifier circuit SA2 and the impurity concentration of the channel stopper region. As shown in FIG. 4, when the impurity concentration of the channel stopper region of the memory cell array MA is lowered as in this embodiment (A), address access is faster than in the conventional case (B), and the waveform is less rounded. few.

The channel stopper regions 4 and 5 that define the periphery of the n-channel MISFET Qn of the peripheral circuit are configured with a higher impurity concentration than that of the memory cell array MA, as described above, so a high power supply voltage Vcc is used as the operating voltage. can do. Peripheral circuit is n channel M
I S F E T Q n and p channel MISFE
This OMO8 is composed of TQP, and the higher the operating voltage of this OMO8, the faster the operating speed can be achieved.

Furthermore, since the vertical mask ROM of this embodiment is configured with TTL specifications and the external power supply voltage Vcc is 5 [V], the peripheral circuit of the vertical mask ROM is required to perform input/output at 5 [V]. 5 [V] is used as the operating voltage.

In addition, in the vertical mask ROM, the memory cells M are connected in series to form a series resistance, so the parasitic MO in the negative part
8 is turned ON, the potential of the common data line CDL is clamped by the series resistor, and the potential of the common data line CDL is extremely reduced.

No DC latch-up occurs. Therefore, the vertical mask ROM can be used with other storage circuits such as horizontal mask ROM.
The impurity concentration of the channel stopper region 4 of the memory cell array MA can be made lower than that of the memory cell array MA, and this configuration has a great effect.

Next, a method for manufacturing the above-mentioned vertical mask ROM will be briefly explained using FIG. 5 (process flow diagram).

First, a p-type semiconductor substrate l made of single crystal silicon is prepared (01).

Next, an n-type well region 2 is formed (02), and this n-type well region 2 is formed.
A p-type well region 3 is formed in self-alignment with the ゛-type well region 2 <03>. The n-type well region 2 is formed by introducing n-type impurities by ion implantation using a mask (not shown) formed on the thin insulating film 19 of the p-type well region 3. (See Figure 6). The p-type well region 3 is formed by introducing p-type impurities by ion implantation using the thick insulating film 20 on the n-type well region 2 as a mask. #! The M film 20 is formed by performing thermal oxidation using a mask (not shown) formed on the above-mentioned insulating film 19 as an oxidation-resistant mask.

Next, a mask 21 having an opening in the region where the field insulating film 6 is to be formed is formed (04) (see FIG. 6).

The mask 21 is used as an impurity introduction mask and an oxidation-resistant mask. The mask 21 is formed of, for example, a silicon nitride film.

Next, as shown in FIG. 6, a mask 21 is used.

A p-type impurity 4p forming a channel stopper region 4 with a low impurity concentration is introduced into the entire surface of the substrate <05>. Since the p-type impurity 4p is not introduced into the formation regions of the mask 21 and the thick insulating film 20, it is introduced only into the main surface of the p-type well region 3. For example, the p-type impurity 4P is 10
” [atoms/ INF about aAko.

The ion implantation method is performed using an ion implantation method with an energy of about 50 to 70 [KeV].

Next, as shown in FIG. 7, the n-channel M of the peripheral circuit
A mask 22 with an opening for the I S F E T Q n formation region is formed, and using this mask 22 and the mask 21, the p-type impurity 5 forming the channel stopper region 5 is formed.
Four people put p on the entire surface of the board〈06〉. The P-type impurity 5p is
It is defined by the mask 22 and the mask 21 and is introduced only into the region defining the periphery of the n-channel MISFETQn in the p-type well region 3. For example, the p-type impurity 5P is 10"
Using BF2 of about [atoms/Cj], 50 to 70
It is introduced by an ion implantation method with an energy of about [KeV].

P-type impurities 4p and 5p are introduced into the main surface of the p-type well region 3 in the region defining the periphery of the n-channel MISFET Qn through two impurity introduction steps, so that a high impurity concentration is added. Concentrated channel stop regions 4 and 5 can be formed.

Next, after removing the mask 22, a field insulating film 6 is formed using the mask 21 (07). The field insulating film 6 is formed by thermal oxidation, and in the same step as this formation, the P-type impurities 4p and 5p are diffused, respectively, to form the channel stopper region 4 and the channel stopper region 5.
is almost completed.

Next, a gate insulating film 7 is formed 08>, and a gate electrode 8 is formed.
After forming 09>, an n-type semiconductor region 9 and a p-type semiconductor region 10 with low impurity concentration are sequentially formed (lO).
.

Next, a sidewall spacer 11 is formed on the side wall of the gate electrode 8. Using this sidewall spacer 11 as a mask, each of the n° type semiconductor region 12 and the p type semiconductor region 13 with high impurity concentration is sequentially formed. form <
12) <13>. By the process of forming this n-type semiconductor region 12, the memory cell M, the n-channel MISFET
Qn etc. are almost completed. For example, the memory cell M has a threshold voltage adjusting impurity introduced before forming the gate insulating film 7, and is formed in a depletion type. Furthermore, a p-channel MISFET QP is formed by the step of forming the p'-type semiconductor region 13.

Next, among the memory cells M, the threshold voltage of a predetermined memory cell M is set to an enhancement type, and information is written (14). This is done by introducing p-type impurities into the channel formation region through the electrode ViA 8 and the gate insulating film 7.

Next, the two-layer insulating film 14. The connection hole 15 and the wiring 16 are sequentially formed <15>(16>(17>). Then,
By sequentially forming the passivation film 17 and the passivation film 18 <18><19>, the vertical mask ROM of this embodiment is completed.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments. However, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention is not limited to the vertical mask ROM, but also horizontal mask ROM, EPROM, EEPROM, DR
It can be applied to memory circuits such as AM and SRAM.

Furthermore, the present invention can be applied to a microprocessor or a gate array equipped with the memory circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having a memory circuit, the operating speed can be increased and electrical reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a vertical mask ROM which is an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the vertical mask ROM. FIG. 3 is a diagram showing the relationship between the impurity concentration of the channel stopper region and the access time. FIG. 4 is a diagram showing the relationship between the waveform of information input to the sense amplifier circuit and the impurity concentration of the channel stopper region, FIG. 5 is a process flow diagram of the vertical mask ROM, and FIGS. FIG. 7 is a sectional view of a main part of the vertical mask ROM in a predetermined manufacturing process. In the figure, 2, 3... Well region, 4, 5... Channel stopper region, 6... Field insulating film, 8... Gate electrode, 16... Wiring, M... Memory cell, Q・
...MISFET, CDL...Common data line, WL
...Word Figure 2 l ``- Figure 3 Inerus) -// Mahiro, Wei 7) Distorted ten Himono concentration Figure 4

Claims (1)

[Claims] 1. The periphery of each semiconductor element forming peripheral circuits such as memory cells and decoder circuits connected to data lines extending in the memory cell array is defined by a field insulating film and a channel stopper region. In semiconductor integrated circuit devices,
The impurity concentration of the channel stopper region defining the periphery of the memory cell is lower than the impurity concentration of the channel stopper region defining the periphery of the semiconductor element of the peripheral circuit, and the operating voltage applied to the data line is A semiconductor integrated circuit device characterized in that the operating voltage is lower than that used in the peripheral circuit. 2. The channel stopper region that defines the periphery of the semiconductor element of the peripheral circuit is formed in two impurity introduction steps, and the channel stopper region that defines the periphery of the memory cell is formed in one of the two impurity introduction steps. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed by a process. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the memory cell constitutes a vertical mask ROM.