JPS5999760A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the soft light of the titled memory device by a method wherein a differential sensing amplifier, in which the variable signal sent from the field effect type nonvolatile memory element having floating and control gates and the signal sent from the FET having no floating gate are inputted, is provided. CONSTITUTION:The group 21 of a field-effect type non-volatile element 8, and the group 24 of FET of enhancement type 22 and depletion type 23, and an FET 26 for reference are provided on a P type Si substrate 1. A P<++> channel 26 is provided on the group 21 by performing a B-ion implantation, and on the group 24 having no floating gate, a P<+> channel 28 is provided on the enhancement type by performing a B-ion implantation and an N<++> channel 29 is provided on the depletion type by performing a P-ion implantation. The reference FET for differential sensing amplifier has no floating gate, the insulating film thickness of which is to be formed approximately twice (500- 1,000Angstrom ) that of the memory element 8, and besides, a channel 31 is formed into P type by implanting a B-ion of 4-6X10<11>/cm<2> or thereabout, and the element 25 is brought to the same IV characteristics of blanking condition of the element 8 by adjusting the threshold voltage. As the element 25 has no floating gate, no soft light is generated, thereby enabling to improve the readout reliability of the titled memory device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention prevents a reference transistor for a differential sense amplifier that detects a memory state of a memory element from floating. It belongs to semiconductor memory devices.

Figure 1 shows a variable threshold field-effect nonvolatile memory element (
This is a cross-sectional view of a memory element (hereinafter referred to as a child).

In the figure, a drain N,
A type impurity diffusion layer (2) (hereinafter referred to as drain) and a source N-type impurity diffusion layer (3) (hereinafter referred to as source) are formed separately.
) is the channel region, and the first insulating film (4), floating gate (5), second insulating film (6), and control gate (7) are formed on this channel region in this order. are laminated on.

FIG. 2 is a block circuit diagram from a memory element to an output related to reading of a semiconductor memory device configured using a conventional reference transistor using a memory element. In FIG. 2, a plurality of memory elements (8) are arranged in a matrix to form a memory area (9),
The control gate (7) of the memory element (8) is connected to be selected by the X decoder αO, and the drain (2)
is connected to be selected by the Y decoder Op, and the source (1) is connected to GND (A). Y decoder α
When selected by η, the drain (2) is connected to the power supply α through a resistor (to) and is also connected to one input of the differential amplifier α6).

Further, the gate (7) of the reference transistor Q6 using a memory element is connected to the power supply α◆, and the drain (
2) is connected to the other input of the differential sense amplifier (15+) and is connected to the power supply α via the resistor α, and the source (3) is connected to GND (2). The output of the amplifier (16) is connected to the input of the output buffer 0→, and the output of the output buffer (the output of the output is output terminal 09)
It is connected to the.

Next, the operation will be explained. First, in the memory element (8) shown in FIG. 1, writing is performed on the P-type semiconductor substrate (1).
The source (3) is grounded and a high voltage is applied to the drain (2) and control gate (7) to cause avalanche breakdown near the drain (2) between the drain (2) and the source (3), and hot electrons are generated. This is done by injecting 70-ting gate (5).

For reading, the threshold voltage of the control gate (7) differs depending on whether or not electrons are injected into the floating gate (5). Therefore, the voltage between the two high and low threshold voltages is applied to the control gate (7). This can be done by detecting this difference since the channel currents differ when .

Next, a method for reading memory information will be explained with reference to FIG. First, the memory transistor (8) in the memory area (9) is selected using the X decoder (10 to select the control gate (7), and the Y decoder α◇ to select the drain (2).
is selected, and only one memory element (8) has a voltage applied to both its control gate (7) and drain (2). If there are no electrons in the floating gate (5),
The drain (2) and source (3) of the memory element are electrically connected, and the differential sense amplifier Q61 is connected to the ground level, that is, "Lo
A voltage of w j level is transmitted. floating game)
When electrons are accumulated in (5), almost no current flows between the drain (2) and source (3) of the memory element, and the current flows from the power supply α→ to the [I-1l-1i level] through the resistor 0. This is transmitted to the differential sense amplifier (16+).On the other hand, the reference transistor O has the same structure and function as a memory element, but instead of being used as a memory element, it is used without injecting electrons into the floating gate (5). Used as a transistor.In this case, the reference transistor α→ is always in a conductive state, and the other inputs of the differential sense amplifier (151 always receive a “Low J” level voltage. Therefore, the reference transistor αQ
A signal of the same level as “Low J” from the memory area (9
) to the differential sense amplifier ([51], it is determined to be "1", and if a signal of "HighJ level", which is higher than the "LOW" level from the reference αQ, is transmitted, it is determined to be "0",
output buffer Q8] and is output to output terminal 09). Here, the structure and function of the reference transistor 0 are the same as those of the memory element (8).As explained above, the ID-VG characteristics of the memory element (8) in the erased state are the same. This is because a transistor with characteristics can be easily obtained.

However, as mentioned above, it is necessary to always apply a voltage between the drain and source of the reference transistor, and if the structure and function of the reference transistor are made the same as that of the memory element, it will not work at 1'ji for a long time. A soft write, which is unique to the floating gate structure, occurs in which electrons are gradually injected into the floating gate at a low voltage between the drain and source, causing charge to be retained.

When in a soft write state, the threshold value of the reference transistor that serves as the standard changes, and if the threshold value change becomes large, an incorrect signal will be read and transmitted, resulting in poor reliability. Ta.

The present invention was made in order to eliminate the drawbacks of the conventional devices as described above, and includes a field effect nonvolatile memory element having a floating gate and a control gate, a field effect transistor having no floating gate, and the memory element. An object of the present invention is to provide a semiconductor memory device which prevents soft writes and improves reliability by providing a differential amplifier having two inputs: a variable signal obtained by the field effect transistor and a signal obtained by the field effect transistor. It is said that

An embodiment of the present invention will be described below with reference to the drawings. 8th
The figure is a side sectional view of a semiconductor memory device.

In FIG. 8, a P-type S1 semiconductor substrate (1) is provided with a memory element (8), that is, a field-effect nonvolatile memory element.

memory element group C21), an enhancement transistor 122 and a depletion transistor (
A transistor group (product) consisting of transistors (product) and a reference transistor (c) are formed. Memory element group @1
), a drain (2) and a source (3) are formed at a predetermined distance apart, and a first insulating film (4), polysilicon, etc., which holds and releases charges, is formed on the source/drain region, that is, the channel region. Possible floating conductor (5), second insulating film (6), control gate (7) of conductor such as poly or silicon lowers the breakdown voltage of the stack, resulting in floating gate) (
In order to increase the electron injection efficiency of 51z, 8xxou ~ 10
,X,10','I have an average value of 6. , X 10
``Cx boron is implanted to form a P-type impurity diffusion layer (261
(hereinafter referred to as r) is formed. In the transistor group H, a first insulating layer M is provided on the channel region.
(4) At the same time as the floating gate (5), the glued gate layer is laminated 1.

The combination of Todo multi-disaster wire is P+1 of memory □ element (8)
Five boron particles of 4 x 10"cIrL are injected with a small average value to form a P-type impurity diffusion layer (c) (referred to as "Shinago"), and in the case of a depletion transistor (2), phosphorus is injected and N Type impurity diffusion layer @ (hereinafter referred to as N++)
is formed. At zero power, the reference transistor's first transistor of the memory element (8) is placed on the channel region.
The insulating film (4) and the gate insulating film formed simultaneously with the second insulating film (6), and the gate insulating film formed simultaneously with the control gate (7) are stacked, A P-type impurity diffusion layer 0υ is formed by implanting boron in an amount equal to that of at least one of the p++ fi of the memory element (8) and the P+□□□ of the enhancement transistor (Inc.).

In the structure described above, the reference transistor does not have a floating gate (5), but the first insulating film (4) and second insulating film (6) used in the memory element (8) are Used as a gate insulating film. Generally, the first insulating film (4) and the second insulating film (
Since the film thickness of 6) is 400 to 700 holes, the thickness of the gate insulating film of the reference transistor is about twice that, and the threshold voltage increases by about 0.1 to 0.8 V. FIG. 4 shows the relationship between threshold voltage and gate film thickness. In FIG. 4, the variation in threshold voltage is about ±0.1v. Furthermore, the P-type impurity diffusion layer SO has an average f 6X1
Since boron is implanted with a value of 0"c7iL", 4X10"l", or 1θxio" (7), which is a combination of both, the reference transistor The threshold voltage of the memory element (8) in the erased state is usually 1.0 to 2.QV, ) by increasing the gate film thickness and adjusting the amount of boron implanted into the P-type impurity diffusion layer 0◇ including the channel region, the threshold voltage of the reference transistor (Inc.) can also be increased from 1.0 to 2. Since the OV K can be set and it can be manufactured in almost the same process as the memory element (8), it can easily have the same current and voltage characteristics as the erased state of the memory element (8). Reference transistor (21it)
When used in place of the reference transistor aQ shown in the figure, the output terminal (from i to the desired "1"
or 0'' output can be taken out, and the 7 array transistor t2a has a floating gate (
5) does not exist, so soft writing does not occur, and therefore read reliability can be improved.

Note that in the above embodiment, the reference transistor (2
Although the phrase has the same characteristics as the ID-■G characteristics when erasing the memory element (8), it is not limited to this, and even if there is a difference in characteristics, it is sufficient that the output is the same as that of the memory element (8). The output may be different from that of the element (8).

In addition, in the above embodiment, the reference transistor (the 2-equal gate gate is the control gate (8) of the memory element (8)).
Although the material is the same as that of 7), it may be a different material, and the gate insulating film is the same as the first insulating film (4) of the memory element (8).
) and the second insulating film (6), for example, other structures including only the first insulating film (4) may be used. The amount of boron implanted was set to be at least one of the amount of boron implanted into P++ (26) of the memory element (8) and the amount of boron implanted into P+e28) of the enhancement transistor in the internal circuit, but other implanted amounts may also be used. Alternatively, other impurities may also be used to achieve the desired purpose as well.

As described above, according to the present invention, there is provided a field effect nonvolatile memory element having a floating gate and a control gate, a field effect transistor having no floating gate, a variable signal obtained by the memory element, and a variable signal obtained by the field effect transistor. Since the field effect transistor is provided with a differential sense amplifier that receives two signals as inputs, it is possible to operate the field effect transistor as a reference transistor for the memory element, and it is also possible to prevent soft write, thereby improving reliability. The effect is that it can be improved.

[Brief explanation of drawings]

FIG. 1 is a side sectional view showing a field-effect nonvolatile memory element, FIG. 2 is a read circuit diagram of a conventional semiconductor memory device, and FIG. 8 is a side sectional view of a semiconductor memory device according to an embodiment of the present invention. FIG. 4 is a threshold voltage vs. gate film thickness characteristic diagram, and FIG. 5 is a threshold voltage vs. boron implantation amount characteristic diagram. In the figure, (1) is a semiconductor substrate, (5) is a floating gate, (7) is a control gate, (8) is a field effect nonvolatile memory element, θ51 is a differential sense amplifier, and 4) C is a field effect transistor. . In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno - Figure 1 Figure 2

Claims (4)

[Claims] (1) Variable threshold field-effect non-volatile device formed in a semiconductor substrate and capable of reading out whether a floating gate is in the erased or written state by applying a voltage to the control gate. 1. A semiconductor memory device comprising a differential sense amplifier having two inputs: a variable signal obtained from the memory element and a signal obtained from the transistor. (2) The semiconductor memory device according to claim 1, wherein the field effect transistor has the same output as the erased state output of the memory element. □ (3) The gate insulating film of a field effect transistor is a memory □
Claim 1 has a structure in which a control gate insulating film is laminated on a floating gate insulating film of an element.
3. The semiconductor memory device according to item 1 or 2. (4) The semiconductor memory device according to any one of claims 1 to 8, wherein the material of the gate of the field effect transistor is the same as that of the roll gate of the memory element (D near 7 ). (The amount of impurity implanted in the channel region of the 5J field effect transistor is the amount of impurity implanted in the channel region of the storage element and the amount of impurity implanted in the transistor channel region of other MOSs in the same semiconductor substrate). A semiconductor memory device according to any one of claims 1 to 4.