JPH0352269A - Ultraviolet ray erasable semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To operate even with a remarkably low power source voltage by forming a first conductivity type first impurity region on first and second channel regions, and a second conductivity type second impurity region on the surface of the first impurity region. CONSTITUTION:A channel region between a source region 3 and a drain region 2 is formed of a first channel region controlled directly by a control gate electrode 8 and a second channel controlled by a floating gate electrode 6. Further, impurity of reverse conductivity type to that of a substrate having small diffusion coefficient is doped to the channel region to raise the threshold voltage of the first channel region higher than that of the second channel region. Thus, even if the threshold voltage of memory is lowered to about 0.5V, the memory having small OFF leakage current can be formed, and can be operated with a very low voltage of about 1V as a power source voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ultraviolet erasable semiconductor nonvolatile memory used in electronic equipment such as computers.

[Summary of the invention]

The present invention provides a floating gate type ultraviolet erasable semiconductor nonvolatile memory in which a channel region between a source 'AM3'J and a drain region is connected to a first channel region controlled by a control gate electrode and a floating gate electrode. A second channel region controlled by This is what made it possible.

[Conventional technology]

Conventionally, as shown in FIG. 2, a floating gate electrode 16, an interlayer insulating film 17, and a control gate electrode 18 are formed on a P-type silicon substrate 11 via a gate insulating film 14, and are self-aligned with respect to the floating gate electrode 16. An N-type source region 13 and drain region 12 are formed on the surface of the substrate 11, and further,
An ultraviolet-erasable floating gate electrode type semiconductor nonvolatile memory in which a P-type impurity region 19 is formed on the surface of a substrate 11 to facilitate the generation of hot electrons has been known. For example, S. TJang “On the I-V Cha
racteristics of Floating
-GateMOS Transistors” IE
EE Tran. on Elec. Dev. ,vo
l. ED-26, No. 9. 1979 pp1
No. 292-1294.

[Problem to be solved by the invention]

However, in the floating gate type semiconductor nonvolatile memory as shown in FIG. 2, the dark value voltage to the control gate electrode after information erasure by ultraviolet irradiation could only be reduced to a threshold voltage of about 1V. That is, when the dark value voltage is lowered, the potential of the floating gate electrode l6 becomes higher due to the potential of the drain region l2, so that current also flows in the non-selected memory cells. Therefore, since the threshold voltage can only be lowered to about 1V, there is a drawback that low voltage operation is difficult.

Therefore, in order to solve these conventional drawbacks, the present invention lowers the dark voltage of the memory to about 0.5V like a normal transistor, and as a result, it can operate even with a power supply voltage of about 1.5V. The target is ultraviolet erasable semiconductor non-volatile memory.

[Means to solve the problem]

In order to solve the above problems, the present invention provides an ultraviolet-erasable floating gate type semiconductor nonvolatile memory in which a channel region between a source region and a drain region is a first channel region controlled by a control gate electrode. , and a second channel region controlled by the floating gate electrode are formed in series, and the dark voltage of the first channel region is formed to be higher than the dark voltage of the second channel region, and the floating gate electrode By preventing leakage current from unselected memory cells regardless of the potential of the memory cell, low-voltage operation and high-speed operation are possible.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a sectional view of a first embodiment of a semiconductor nonvolatile memory according to the present invention. The semiconductor nonvolatile memory of the present invention includes:
It goes without saying that it is limited to a silicon substrate, but can also be formed on a semiconductor region provided within a substrate. Also,
It can also be formed on the surface of a thin film semiconductor. FIG. 1 shows an example in which it is formed on the surface of a P-type semiconductor substrate 1. P type silicon substrate
A floating gate electrode 6 is provided on the surface of the gate via the second gate vA edge film 4, and a control gate electrode 8 is formed via the glabella insulating film 7 and the first gate insulating film 5 on the floating gate electrode 6. N-type source region 3 and drain region 2 are formed on the surface of substrate 1 in self-alignment with respect to floating gate electrode 6 and control gate electrode 8. In general,
The second gate insulating film 4 is a thermal oxide film of about 200 layers, and the floating gate electrode 6 is a N° type polycrystalline H. n4h+swwww+. k7. :Inm++ll
+P+-hza++tbL! L4〒Thermal oxide film of pole 6,
The control gate electrode 8 can be formed of an N'' type polycrystalline silicon film. Further, the N-type source/drain regions can be formed by ion implantation. Further, a P-type first impurity region 9 is formed in the channel region that is the surface of the substrate 1 between the source region 3 and the drain region 2, and further,
An N-type second impurity region 10 is formed on the surface of the P-type first impurity region 9 . Generally, the surface concentration of the first impurity region 9 is higher than that of the second impurity region 10, so that it is electrically P-type. The first and second impurity regions can also be doped by ion implantation.

Figure 3 shows the concentration distribution. That is, AA' in FIG.
It shows the impurity distribution from the surface of the substrate l along the line. 3 is a diagram showing a case where boron is used as an impurity in a first impurity region 9 and arsenic is used as an impurity in a second impurity region 10. FIG. Even if boron and arsenic are introduced in the same process, the diffusion coefficient of arsenic is smaller than that of boron. It will be a low value depending on the distribution of. The first impurity region 9 is provided in order to satisfy the programming characteristics of the semiconductor nonvolatile memory of the present invention, and to increase the dark value voltage of the field between the memory cells by the impurity region 9. This is for electrical isolation. The first impurity region 9 is formed on the surface of the base 1 with a thickness of 10"
By adding a P-type impurity around a tons/ca1, hot electrons are easily generated during programming. Further, the second impurity region 10 is a region for lowering the dark value voltage of the memory. The control gate electrode 8 has strong capacitive coupling with the floating gate electrode 6. Therefore, by applying a voltage to the control gate electrode 8,
The potential of the floating gate electrode 6 can be changed indirectly.

First, a method for reading a semiconductor nonvolatile memory according to the present invention will be explained.

In a memory array in which a plurality of memory cells are integrated, in a cell from which information is to be read, that is, a selected memory cell, the source region 3 and drain Information can be read out depending on the conductance of the channel region between the region 2 and the region 2. That is, if the state is the same as after erasing ultraviolet rays, the channel conductance is large, and conversely, if a large number of electrons are injected into the floating gate electrode 6 due to programming, the channel conductance is small. Channel conductance is determined between a first channel region controlled by a control gate electrode 8 via a first gate insulating film 5 and a second gate insulating l! 4 becomes the series connected value of the second channel region controlled by the potential of the floating gate electrode 6. Since the conductance of the second channel region changes depending on the amount of electrons injected into the floating gate electrode 6, the conductance between the source region 3 and the drain region 2 when a constant voltage is applied to the control gate electrode 8 changes. The channel conductance between the two changes, and information can be read out based on the amount of change.

In the ultraviolet erasable semiconductor nonvolatile memory of the present invention, the channel region has a first channel region directly controlled by the voltage of the control gate electrode 8 and a second channel region controlled by the potential of the floating gate electrode 6. It is formed by a series of

Therefore, even if the dark voltage of the second channel region after ultraviolet erasure is set sufficiently low, if the dark voltage of the first channel region is set to the enhanced level, the leakage current of unselected memory cells will be reduced. It can be made low enough. Furthermore, by applying a voltage to the drain region 2 during readout, the potential of the floating gate electrode 6 increases, and the channel conductance of the second channel region increases, causing the channel conductance of the first channel region to increase. By setting it to a small value, off-leakage current of unselected memory cells can be prevented. Furthermore, in the memory of the present invention, by grounding the drain region 2 and applying a power supply voltage to the source region 3 through a load, a memory with a high Mm capability can be obtained by reading out the channel conductance. realizable. That is, since the floating gate electrode 6 is not structurally connected to the source region 3, erroneous writing (soft writing) during reading does not occur. Therefore, the channel length can be made shorter than that of conventional memory cells, and a high voltage close to the power supply voltage can be applied to the source region 3 during reading.

Therefore, the channel conductance of the memory after erasing with ultraviolet light can be increased, and high-speed reading can be achieved.

Next, a memory programming method according to the present invention will be explained. In the case of a memory that injects electrons into the floating gate electrode 6,
A voltage approximately 5 to 7 V higher than that of the source region 3 and substrate 1 is applied to the drain region 2 .

Further, a high voltage of about 12V is applied to the control gate electrode 8. By applying voltage to the drain region 2 and the control gate electrode 8, a large channel current of about 1 mA flows in the channel region, generating hot electrons near the drain region 2, and a part of them is injected into the floating gate electrode 6. be done. Since no voltage is applied to the control gate electrode 8 of the unselected memory cells, writing is not performed. Furthermore, even in the E-Tatsumi I scale memory cell, in a memory cell in which electrons are not injected into the floating gate electrode 6, even if a high voltage is applied to the control gate electrode 8, the voltage of the drain region 2 cannot be grounded. No writing is performed.

That is, electrons are injected into the floating gate electrode 6 only when a voltage is applied to both the drain region 2 and the control gate electrode 8. The memory of the present invention has a structure in which soft writes are less likely to occur, so the channel length can be shortened. Therefore, even in the write operation, writing can be performed in a very short time. In addition, in the write-unselected memory cell, even if a high voltage is applied to the drain region 2, since the control gate electrode 8 is grounded,
The conductance of the first channel region is sufficiently small, so that off-leakage of unselected memory cells can be prevented.

Further, in the memory of the present invention, a second impurity region IO made of arsenic is formed on the surface of the channel region in order to lower the dark value voltage, but this impurity region 10 does not deteriorate programming efficiency. The surface potential for generating hot electrons near the drain region 2, which is formed during writing, is hardly affected by arsenic doping.

This is because the second impurity region 10 made of arsenic has a small diffusion coefficient and is therefore formed very close to the surface as shown in FIG.

If the concentration of the first impurity region 9 is lowered instead of forming the second impurity region 10 in order to lower the dark value voltage of the channel region, the shape of the surface potential for generating hot electrons becomes gentler. In order to become
Program efficiency will deteriorate. In the memory of the present invention, depending on the shape of the second impurity region 10, the programming efficiency of the memory can be maintained and the dark value voltage of the memory can be lowered.

Next, a memory erasing method according to the present invention will be explained. Erasing is performed by irradiating the memory with ultraviolet light.

The electrons injected into the floating gate electrode 6 are excited by the ultraviolet rays and are erased by returning to the substrate 1.

Figure 4 shows the dark voltage of arsenic (As) of the memory after erasing ultraviolet rays.
) is a diagram showing the dependence of injection amount. As shown in FIG. 4, by implantation of sulfur, it can be divided into region 8 where the dark value decreases significantly at the boundary of the implantation amount of 5×10'' and region B where the dark value decreases small.Memory with the structure of the present invention The dark value voltage of is the larger dark value of either the first channel region or the second channel region.The second impurity region 1 made of arsenic
When 0 is not formed, that is, when the amount of ion implantation is zero, the dark value voltage is equal to the dark value voltage of the second channel region, which is the higher dark value voltage. Second impurity region 10
As the amount of arsenic implanted into the channel increases, the dark voltages of the first and second channel regions become opposite in magnitude. That is, as the injection amount increases, the area shifts from area A to area B. Region A corresponds to the dark value voltage of the second channel region, and region B corresponds to the dark value voltage of the first channel region. In region B, the method of reducing the dependency of the threshold voltage of the first channel region on the arsenic implantation amount is to reduce the capacitance per unit area of the first gate insulating film 5 to the capacitance per unit area of the second gate insulating film 4. This can be done by increasing the capacity compared to the capacity of . By increasing the capacitance per unit area of the gate insulating film, the contribution rate of the implantation amount to the dark value voltage can be reduced. In order to lower the dark voltage of the memory, in the method of lowering the concentration of the first impurity region 9 without forming the second impurity region 10, the dark voltage of the second channel region is always higher than that of the first impurity region. The voltage is higher than the dark voltage of the channel region. The dark voltage of the second channel region is
The capacitive coupling between the control gate electrode 8 and the floating gate electrode 6 is 1
The capacitive coupling is generally about 70%, not 00%, so it becomes high. However, in the memory of the present invention, by forming the second impurity region 10, the dark value voltage of the first channel region can be made higher than the threshold voltage of the second channel region. A method for making the threshold voltage of the first channel region higher than the dark voltage of the second channel region can also be achieved by changing the impurity concentration.

FIG. 5 is a cross-sectional view of a second embodiment of the semiconductor non-volatile memory of the present invention, in which the dark value voltage of the channel of Chiku 1 is increased by increasing the impurity concentration. A P-type third impurity region 21 is formed in the first channel region in a self-aligned manner using the floating gate electrode 6 as a mask.

Since the P-type impurity is formed in a direction that cancels the impurity in the second impurity region 10 containing N-type impurity, the dark value voltage of the first channel region can be made high.

Also in the semiconductor nonvolatile memory shown in FIG. 1, the first gate insulating film 5 is formed by a thermal oxide film after removing the second gate insulating film 11Q4, and if a part of the second impurity region 10 is Because it enters the first gate insulating film 5, the first
The arsenic concentration in the channel region can be low.

As explained above, by implanting arsenic, the dark value voltage after ultraviolet erasure can be lowered to about 0.5V.

Since the dark value voltage of this memory is the threshold voltage of the L-th channel region, it is stable regardless of the voltage of the drain region 2, and off-leakage current can be reduced. Since the dark value voltage can be lowered to about 0.5V, the electric 'a voltage is about 1
It is possible to operate the memory up to about v.

〔Effect of the invention〕

As described above, the present invention provides an ultraviolet erasable floating gate semiconductor nonvolatile memory in which a channel region between a source region and a drain region is directly controlled by a control gate electrode; and a second channel region controlled by an electrode, and further, by doping the channel region with a substrate having a small diffusion coefficient and an impurity of the opposite conductivity type, the dark voltage of the first channel region is controlled by the second channel region. By forming the memory to be higher than the dark value voltage of the channel region, the threshold voltage of the memory can be set to about 0.
．． It is possible to realize a memory with low off-leakage current even when the voltage is lowered to about 5V, and as a result, the power supply voltage is about 1V.
This has the effect of facilitating semiconductor non-volatile memory that operates at a very low voltage of about V.

[Brief explanation of drawings]

FIG. 1 shows a first diagram of a semiconductor nonvolatile memory according to the present invention.
FIG. 2 is a cross-sectional view of a conventional semiconductor nonvolatile memory. FIG. 3 is an impurity distribution diagram of the channel region of the semiconductor nonvolatile memory of the present invention;
The figure shows the dependence of the dark voltage of the semiconductor nonvolatile memory of the present invention on arsenic ion implantation. FIG. 5 is a sectional view of a second embodiment of the semiconductor nonvolatile memory of the present invention. Semiconductor substrate drain region source region floating gate electrode control gate electrode and above

Claims (1)

[Claims] a source region and a drain region of a second conductivity type provided at a distance from each other on the surface of the first semiconductor region of the first conductivity type; and a source region and a drain region of a second conductivity type formed on the surface of the first semiconductor region between the source and drain regions. a first channel region in contact with the source region; a second channel region formed on the surface of the first semiconductor region between the first channel region and the drain region; and the first channel region. a first gate insulating film formed thereon, a second gate insulating film formed on the second channel region, a floating gate electrode provided on the second gate insulating film, and a floating gate electrode provided on the second gate insulating film; A control gate insulating film formed on the floating gate electrode, a control gate electrode provided on the first gate insulating film and the control gate insulating film, and a control gate insulating film formed on the first and second channel regions. An ultraviolet erasable semiconductor nonvolatile memory, characterized in that a first impurity region of one conductivity type is formed, and a second impurity region of a second conductivity type is further formed on a surface of the first impurity region.