JPH02266554A - Integrated circuit package - Google Patents
Integrated circuit packageInfo
- Publication number
- JPH02266554A JPH02266554A JP8697589A JP8697589A JPH02266554A JP H02266554 A JPH02266554 A JP H02266554A JP 8697589 A JP8697589 A JP 8697589A JP 8697589 A JP8697589 A JP 8697589A JP H02266554 A JPH02266554 A JP H02266554A
- Authority
- JP
- Japan
- Prior art keywords
- pins
- substrate
- holder
- pin
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000012212 insulator Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000000919 ceramic Substances 0.000 abstract description 10
- 238000005452 bending Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 238000012993 chemical processing Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、例えばPG八(ビングリッドアレイ)等に使
用して好適な集積回路パッケージに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit package suitable for use in, for example, PG8 (bin grid array).
近年、LSIの高集積化、高速化の進展に伴いアクセス
用の入出力ピン数が増加しており、このためLSIを収
納する集積回路パッケージのビン数も増加している。In recent years, as LSIs have become more highly integrated and faster, the number of input/output pins for access has increased, and as a result, the number of bins of integrated circuit packages that house LSIs has also increased.
従来、この種の集積回路パッケージ止しては第5図に示
すようなものが採用されている。これを同図に基づいて
説明すると、同図において、符号1で示すものはその内
部にLSI(図示せず)を有し一例に多数のI/Oピン
2が突出するセラミック基板である。Conventionally, this type of integrated circuit package has been adopted as shown in FIG. This will be explained based on the same figure. In the same figure, what is indicated by reference numeral 1 is a ceramic substrate having an LSI (not shown) therein and from which a large number of I/O pins 2 protrude, for example.
このように構成されたバフケージは、例えばプリント配
線板(図示せず)に170ビン2を各パッド(図示せず
)に接続することにより表面実装される。The buff cage configured in this way is surface mounted, for example, by connecting 170 bins 2 to each pad (not shown) on a printed wiring board (not shown).
ところで、従来の集積回路パッケージにおいては、セラ
ミック基板lから下方に突出するI/Oピン2の数が多
くなる(100ピン以上のI/Oピン2をもつ場合)と
、表面実装時に第5図に示すようにI/Oピン2が曲が
り易くなり、各1/Oピン2の先端位置精度にばらつき
が発生していた。このことは、特にパッケージ外形が大
型化(縦横寸法が30m■以上のパッケージサイズをも
つ場合)した場合には、反り変形によって無視すること
はできなかった。この結果、表面実装時にはI/Oピン
2とプリント配線板(図示せず)の接続が確実に行われ
ず、パッケージ実装上の信頼性が低下するという問題が
あった。By the way, in conventional integrated circuit packages, when the number of I/O pins 2 protruding downward from the ceramic substrate 1 increases (in the case of having 100 or more I/O pins 2), the problem of surface mounting as shown in FIG. As shown in FIG. 2, the I/O pins 2 became easily bent, and variations occurred in the accuracy of the tip position of each 1/O pin 2. This cannot be ignored due to warpage, especially when the package size is increased (in the case of a package size with vertical and horizontal dimensions of 30 m or more). As a result, during surface mounting, the connection between the I/O pins 2 and the printed wiring board (not shown) cannot be reliably established, resulting in a problem that reliability in package mounting is reduced.
因に、ビン数が少なくかつパッケージ外形が小さい集積
回路用パッケージにあっては、プリント配線板の設計マ
ージンを大きくすること等により表面実装が可能となる
。Incidentally, in the case of an integrated circuit package having a small number of bins and a small package external shape, surface mounting becomes possible by increasing the design margin of the printed wiring board.
本発明はこのような事情に鑑みてなされたもので、表面
実装時のビン接続を確実に行うことができ、もってパン
ケージ実装上の信頼性を向上させることができる集積回
路パッケージを提供するものである。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an integrated circuit package that can reliably connect bins during surface mounting, thereby improving the reliability of package mounting. be.
本発明に係る集積回路パフケージは、半導体素子をその
内部に有し一側に多数のI/Oピンが突出する基板と、
この基板に設けられI/Oピンの基端部を保護する絶縁
体からなるホルダーとを備えたものである。An integrated circuit puff cage according to the present invention includes a substrate having a semiconductor element therein and a large number of I/O pins protruding from one side;
The device is provided with a holder made of an insulator that is provided on the substrate and protects the base end portion of the I/O pin.
本発明においては、ホルダーによって表面実装時のI/
Oピンの曲がり発生を防止することができる。In the present invention, the holder allows I/O during surface mounting.
It is possible to prevent the O pin from bending.
〔実施例)
以下、本発明の構成等を図に示す実施例によって詳細に
説明する。[Example] Hereinafter, the configuration of the present invention will be explained in detail by referring to an example shown in the drawings.
第1図は本発明に係る集積回路パッケージを示す斜視図
、第2図および第3図は同じ(本発明における集積回路
パッケージの要部を示す正面図である。同図において、
符号11で示すものは例えばLSI等の半導体素子(図
示せず)をその内部に有するセラミック基板で、全体が
平面視矩形状に形成されており、−側(裏側)には下方
に突出する多数の170ビン12が設けられている。1
3は平板状のホルダーで、前記セラミック基板11のビ
ン突出側に設けられており、全体が例えばセラミックス
からなる絶縁体によって形成されている。このホルダー
13によって、前記I10ピン12の各基端部を保護し
、かつ各外部先端部を長さlの等寸法に設定し得る。FIG. 1 is a perspective view showing an integrated circuit package according to the present invention, and FIGS. 2 and 3 are the same (front views showing main parts of the integrated circuit package according to the present invention).
The reference numeral 11 is a ceramic substrate having a semiconductor element (not shown) such as an LSI inside it, and the whole is formed into a rectangular shape in a plan view, and the negative side (back side) has a large number of holes projecting downward. 170 bins 12 are provided. 1
Reference numeral 3 denotes a flat plate-shaped holder, which is provided on the bottle protruding side of the ceramic substrate 11, and is entirely formed of an insulator made of ceramic, for example. This holder 13 protects each proximal end of the I10 pin 12 and allows each external tip to be set to the same size of length l.
このように構成された集積回路パンケージにおいては、
ホルダー13によって第4図に示すようにプリント配線
板14のバッド15に対して表面実装する場合にI/O
ピン12の曲がり発生を防止することができる。In the integrated circuit pancase configured in this way,
When surface mounting the pad 15 of the printed wiring board 14 using the holder 13 as shown in FIG.
This can prevent the pin 12 from bending.
したがって、本実施例においては、各1/Oピン2の先
端位置を揃えることができるから、表面実装時のビン接
続を確実に行うことができる。Therefore, in this embodiment, since the tip positions of the 1/O pins 2 can be aligned, it is possible to reliably connect the pins during surface mounting.
この場合、パフケージ製造時に予めホルダー13に対し
てI10ピン12を挿入しておけば、I/Oピン12の
外部露呈端部長さや先端位置精度を調整することができ
る。In this case, if the I10 pin 12 is inserted into the holder 13 in advance during puff cage manufacture, the externally exposed end length and tip position accuracy of the I/O pin 12 can be adjusted.
また、本実施例においては、I/Oピン2の曲がり、外
部露呈端部長さおよび先端位置精度を管理できることは
、プリント配!’1lFi14に対するI/Oピン12
の半田付は性が良好になる。Furthermore, in this embodiment, the ability to control the bending of the I/O pin 2, the length of the externally exposed end portion, and the accuracy of the tip position is achieved by using printed wiring! I/O pin 12 for '1lFi14
The soldering properties of this material are improved.
なお、本実施例においては、ホルダー13の材料として
セラミックである場合を示したが、本発明はこれに限定
されるものではなく、例えばテフロンあるいはポリイミ
ド等の有機樹脂を使用してもよく、この場合パッケージ
表面実装時の半田付は温度に耐久性があること2機械的
強度が比較的高いこと、物理的・化学的加工が簡単であ
ることおよびプリント配線板との熱膨張係数差を吸収す
ることができる等の利点がある。In this embodiment, ceramic is used as the material for the holder 13, but the present invention is not limited to this. For example, organic resins such as Teflon or polyimide may be used. In the case of package surface mounting, soldering is temperature resistant.2 It has relatively high mechanical strength, easy physical and chemical processing, and it absorbs the difference in thermal expansion coefficient with the printed wiring board. There are advantages such as being able to
また、本考案においては、ホルダー13として例えば溶
剤等によって溶解、エツチング可能な材料で形成すれば
、プリント配線板(図示せず)に対するパンケージの表
面実装後に除去することができる。Furthermore, in the present invention, if the holder 13 is made of a material that can be dissolved and etched with a solvent or the like, it can be removed after the pancage is surface-mounted on a printed wiring board (not shown).
因に、本発明におけるI/OピンI2の長さは、セラミ
ック基板11とプリント配線板14との熱膨張係数差に
起因して生じる熱ストレスを緩和するような寸法に設計
されている。Incidentally, the length of the I/O pin I2 in the present invention is designed to alleviate the thermal stress caused by the difference in coefficient of thermal expansion between the ceramic substrate 11 and the printed wiring board 14.
以上説明したように本発明によれば、半導体素子をその
内部に有し一側に多数のI/Oピンが突出する基板と、
この基板に設けられ■/Oピンの基端部を保護する絶縁
体からなるホルダーとを備えたので、ホルダーによって
表面実装時におけるI/Oピンの曲がり発生を防止する
ことができる。したかって、各110ピンの先端位置を
揃えることができるから、表面実装時のビン接続を確実
に行うことができ、パッケージ実装上の信頌性を向上さ
せることができる。As explained above, according to the present invention, there is provided a substrate having a semiconductor element therein and a large number of I/O pins protruding from one side;
Since the substrate is provided with a holder made of an insulator that protects the base end of the I/O pin, the holder can prevent the I/O pin from bending during surface mounting. Therefore, since the positions of the tips of each of the 110 pins can be aligned, it is possible to reliably connect the pins during surface mounting, and to improve reliability in package mounting.
第1図は本発明に係る集積回路パッケージを示す斜視図
、第2図および第3図は同じく本発明における集積回路
パッケージの要部を示す正面図、第4図はプリント配線
板に対する集積回路パッケージの実装例を示す断面図、
第5図は従来の集積回路パッケージの不良例を示す正面
図である。
11・・・・セラミック基板、12・・・司10ピン、
13・・・・ホルダー、14・・・・プリント配線板。
特許出願人 日本電気株式会社FIG. 1 is a perspective view showing an integrated circuit package according to the invention, FIGS. 2 and 3 are front views showing main parts of the integrated circuit package according to the invention, and FIG. 4 is an integrated circuit package on a printed wiring board. A cross-sectional view showing an example of implementation of
FIG. 5 is a front view showing an example of a defective conventional integrated circuit package. 11... Ceramic board, 12... Tsukasa 10 pin,
13...Holder, 14...Printed wiring board. Patent applicant: NEC Corporation
Claims (1)
突出する基板と、この基板に設けられ前記I/Oピンの
基端部を保護する絶縁体からなるホルダーとを備えたこ
とを特徴とする集積回路パッケージ。A substrate having a semiconductor element therein and a large number of I/O pins protruding from one side, and a holder made of an insulator provided on the substrate and protecting the base ends of the I/O pins. An integrated circuit package featuring:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1086975A JP2722639B2 (en) | 1989-04-07 | 1989-04-07 | Integrated circuit package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1086975A JP2722639B2 (en) | 1989-04-07 | 1989-04-07 | Integrated circuit package |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02266554A true JPH02266554A (en) | 1990-10-31 |
JP2722639B2 JP2722639B2 (en) | 1998-03-04 |
Family
ID=13901874
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1086975A Expired - Lifetime JP2722639B2 (en) | 1989-04-07 | 1989-04-07 | Integrated circuit package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2722639B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11060859B2 (en) * | 2016-04-04 | 2021-07-13 | Tetechs Inc. | Methods and systems for thickness measurement of multi-layer structures |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6344457U (en) * | 1986-09-10 | 1988-03-25 | ||
JPS6471158A (en) * | 1987-09-11 | 1989-03-16 | Nec Corp | Case for integrated circuit chip |
-
1989
- 1989-04-07 JP JP1086975A patent/JP2722639B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6344457U (en) * | 1986-09-10 | 1988-03-25 | ||
JPS6471158A (en) * | 1987-09-11 | 1989-03-16 | Nec Corp | Case for integrated circuit chip |
Also Published As
Publication number | Publication date |
---|---|
JP2722639B2 (en) | 1998-03-04 |
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