JPH0226080A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0226080A JPH0226080A JP63175675A JP17567588A JPH0226080A JP H0226080 A JPH0226080 A JP H0226080A JP 63175675 A JP63175675 A JP 63175675A JP 17567588 A JP17567588 A JP 17567588A JP H0226080 A JPH0226080 A JP H0226080A
- Authority
- JP
- Japan
- Prior art keywords
- solid
- state image
- transparent substrate
- control
- image sensor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 239000011521 glass Substances 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 238000005549 size reduction Methods 0.000 abstract 2
- 239000007787 solid Substances 0.000 abstract 1
- 239000011347 resin Substances 0.000 description 12
- 229920005989 resin Polymers 0.000 description 12
- 238000007789 sealing Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、光学的な画像情報を電気的な信号に変換する
固体撮像素子を組み込んだ半導体素子に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device incorporating a solid-state image sensor that converts optical image information into electrical signals.
［従来の技術］
近年、撮像管に代わる電子の眼として光学的な画像情報
を電気的な信号に変換する固体撮像素子が注目されてい
る。[Prior Art] In recent years, solid-state image sensors that convert optical image information into electrical signals have been attracting attention as electronic eyes that can replace image pickup tubes.
この固体撮像素子を構成する光電変換デバイスとして自
己走査フォトダイオード、ＣＯＤフォトセンサ、ＣＯＤ
とフォトダイオードアレイ。Photoelectric conversion devices that make up this solid-state image sensor include self-scanning photodiodes, COD photosensors, and COD
and photodiode array.
ＢＢＤ、ＭＯＳフォトトランジスタ等があり、これをラ
イン状またはマトリックス状に配列し受光部を形成して
いる。この受光部に走査回路や各画素を選択切換するス
イッチング回路等の受光部ＩＣを組み込んで固定撮像素
子が構成されている。There are BBDs, MOS phototransistors, etc., which are arranged in a line or matrix to form a light receiving section. A fixed image sensor is constructed by incorporating a light receiving part IC such as a scanning circuit and a switching circuit for selectively switching each pixel into this light receiving part.
従来、この固体撮像素子を組み込んだ半導体素子として
第１１図に示すように、基板１０１上に受光部１０２ａ
を透明基板１・０３で保護した固体撮像素子１０２と、
制御用ＩＣ１０４を隣接させてタイボンドし、基板１０
１の配線パターン１０５に固体撮像素子１０２の電極バ
ッド１０６および制御用ＩＣ１０４の電極パッド１０７
をワイヤー１０８，１０９で接続し、固体撮像素子１０
２と制御用ＩＣ１０４を樹脂１１０，１１１で封止した
ものがある。Conventionally, as shown in FIG. 11, a semiconductor device incorporating this solid-state image sensor includes a light receiving section 102a on a substrate 101.
a solid-state image sensor 102 protected by a transparent substrate 1.03;
The control ICs 104 are tied and bonded adjacent to each other, and the substrate 10
The electrode pad 106 of the solid-state image sensor 102 and the electrode pad 107 of the control IC 104 are connected to the wiring pattern 105 of 1.
are connected with wires 108 and 109, and the solid-state image sensor 10
2 and the control IC 104 are sealed with resins 110 and 111.
上記制御用ＩＣ１０４には、インターフェイス回路や信
号処理回路、さらにマイコンの制御回路、マイコン基準
電圧発生回路等が含まれる。The control IC 104 includes an interface circuit, a signal processing circuit, a microcomputer control circuit, a microcomputer reference voltage generation circuit, and the like.
［発明が解決しようとする課題］
ところが、上述の従来技術にあっては、基板１０１上に
固定撮像素子１０２と制御用ｌＣｌＯ４を平面的に実装
するため、実装スペースが大きくなり半導体素子の小形
化を図ることができなかった。[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, since the fixed image sensor 102 and the control lClO4 are mounted on the substrate 101 in a two-dimensional manner, the mounting space becomes large and the size of the semiconductor element is reduced. I was unable to aim for this.
本発明は、上記の問題点に着目してなされたもので、固
体撮像素子と制御用ＩＣの実装スペースを小さくし容易
に小形化を図り得る半導体素子を提供することを目的と
する。The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor device that can be easily miniaturized by reducing the mounting space for a solid-state image sensor and a control IC.
［課題を解決するための手段および作用］本発明は、固
体撮像素子の受光部に対応する透明基板の透孔窓の周囲
に制御用ＩＣを形成したことを特徴とする。また、透明
基板に一体に形成された裏面照射型固体撮像素子の下方
に制御用ＩＣを配設したことを特徴とする。このような
構成によれば、固体撮像素子と同一の場所に制御用ＩＣ
を実装することができる。[Means for Solving the Problems and Effects] The present invention is characterized in that a control IC is formed around a transparent window of a transparent substrate corresponding to a light receiving section of a solid-state image sensor. Further, the present invention is characterized in that a control IC is disposed below a back-illuminated solid-state image sensor that is integrally formed on a transparent substrate. According to such a configuration, the control IC is located at the same location as the solid-state image sensor.
can be implemented.
［実施例］
以下、本発明の一実施例を図面に従い説明する。第１図
、第２図において１は、光電変換デバイスをライン状ま
たはマトリックス状に配列して受光部を形成した固体撮
像素子で、この固体撮像素子１には走査回路や各画素を
選択切換するスイッチング回路等の受光部ＩＣが組み込
まれている。この固体撮像素子１を基板２の凹部２ａに
グイボンドし、固体撮像素子１の電極パッド３と基板２
の配線パターン４をワイヤー５で接続する。[Example] An example of the present invention will be described below with reference to the drawings. In FIGS. 1 and 2, 1 is a solid-state image sensor in which a light-receiving section is formed by arranging photoelectric conversion devices in a line or matrix. A light receiving IC such as a switching circuit is incorporated. This solid-state image sensor 1 is bonded to the recess 2a of the substrate 2, and the electrode pad 3 of the solid-state image sensor 1 and the substrate 2 are bonded.
Connect the wiring pattern 4 with the wire 5.
このワイヤーボンドは後述する樹脂封止の前に行なうこ
ともできる。上記固体撮像素子１の受光面上に制御用Ｉ
Ｃ付き透明基板６を配設する。This wire bonding can also be performed before resin sealing, which will be described later. A control I is provided on the light receiving surface of the solid-state image sensor 1.
A transparent substrate 6 with C is arranged.
制御用ＩＣ付き透明基板６は、例えばサファイア基板や
ガラス板等の透明基板７にエピタキシャル成長装置でＳ
ｉ層を形成し、固体撮像素子１の受光部と対応する領域
の周囲に酸化、拡散。The transparent substrate 6 with a control IC is formed on a transparent substrate 7 such as a sapphire substrate or a glass plate using an epitaxial growth apparatus.
An i-layer is formed and oxidized and diffused around the area corresponding to the light receiving part of the solid-state image sensor 1.
フォトリソ等を繰返し行なって制御用ＩＣ８を作り込む
。制御用ＩＣ８は上記ｌ！！ｌ！造方法に限られるもの
ではなく、他の製造方法により作ることもできる。肢漫
に、第３図に示すように固体撮像素子１の受光部と対応
する領域内のＳｉ層をエツチングして透孔窓９を形成し
である。この制御用ＩＣ８には、例えばインターフェイ
ス回路や信号処理回路、さらにマイコンの制御回路、マ
イコン基準電圧発生回路が含まれる。The control IC 8 is fabricated by repeatedly performing photolithography and the like. The control IC8 is the above l! ! l! The manufacturing method is not limited to this, and it can also be manufactured using other manufacturing methods. As shown in FIG. 3, a through-hole window 9 is formed by etching the Si layer in a region corresponding to the light-receiving portion of the solid-state image sensor 1. This control IC 8 includes, for example, an interface circuit, a signal processing circuit, a microcomputer control circuit, and a microcomputer reference voltage generation circuit.
上記、制御用ＩＣ８側に形成されたＡＩ配線１０に、固
体撮像素子１と電気的に接続する接続用バッド１１が設
けられ、湿気等の影響を受けないように例えば酸化シリ
コン被膜、窒化シリコン被膜等のパシベーション１２が
施されている。The AI wiring 10 formed on the control IC 8 side is provided with a connection pad 11 that electrically connects to the solid-state image sensor 1, and is coated with a silicon oxide film, a silicon nitride film, etc. to prevent it from being affected by moisture, etc. A passivation 12 such as the above is applied.
この接続用バッド１１もしくは固体撮像素子１の電極パ
ッド１３に予めバンプ１４を形成しておき、固体撮像素
子１の上に制御用ＩＣ付き透明基板６をバンブ１４を介
して接続する０ＭＬ後に、透明樹脂１５で封止し、さら
に制御用ＩＣ付き透明基板６の周囲を遮光用樹脂１６で
封止する。この場合、全体を透明樹脂で封止してもく、
また封止方法は樹脂封止に限らずキャップ等による気密
封止であってもよい。Bumps 14 are formed in advance on the connection pads 11 or the electrode pads 13 of the solid-state image sensor 1, and after OML in which the transparent substrate 6 with control IC is connected on the solid-state image sensor 1 via the bumps 14, the transparent It is sealed with a resin 15, and further the periphery of the transparent substrate 6 with a control IC is sealed with a light shielding resin 16. In this case, the entire body may be sealed with transparent resin.
Further, the sealing method is not limited to resin sealing, but may be airtight sealing using a cap or the like.
したがって、このような構成によれば、固体撮像素子１
と同一の場所に制御用ＩＣ８を実装することができるた
め、従来技術に述べたように固体撮像素子と制御用ＩＣ
を平面的に実装したものに比べて実装スペースを著しく
小さくでき、半導体素子の小形化を容易に図り得る。Therefore, according to such a configuration, the solid-state image sensor 1
Since the control IC 8 can be mounted in the same place as the solid-state image sensor and the control IC 8, as described in the prior art,
The mounting space can be significantly reduced compared to a planar mounting, and the size of the semiconductor element can be easily miniaturized.
次に、本発明の他の実施例を説明する。Next, another embodiment of the present invention will be described.
第４図は、本発明の第２実施例を示すものである。この
第２実施例では、基板２の開口部に制御用ＩＣ付き透明
基板６をダイボンドし、制御用ＩＣ８側に形成された接
続用パッド１１と基板２の配線パターン４をワイヤー５
で接続し、制御用ＩＣ付き透明基板６にバンプ１４を介
して固体撮１象素子１を接続している。ｆ＆後に、透明
樹脂１５、Ｍ光用樹脂１６で封止することにより、第４
図に示す半導体素子が完成する。FIG. 4 shows a second embodiment of the invention. In this second embodiment, the transparent substrate 6 with a control IC is die-bonded to the opening of the substrate 2, and the connection pad 11 formed on the control IC 8 side and the wiring pattern 4 of the substrate 2 are connected to the wire 5.
The solid-state sensor element 1 is connected to the transparent substrate 6 with a control IC via bumps 14. After f &, by sealing with transparent resin 15 and M light resin 16, the fourth
The semiconductor device shown in the figure is completed.
このような構成によれば、第１実施例と同様に実装スペ
ースを小さくでき、半導体素子の小形化を図ることがで
きる。しかも、基板２の配線パターン４との接続用パッ
ド１１を制御用ＩＣ側に形成することにより、固体撮像
素子１のＡ１配線を少なくできるので、固体撮１象素子
の製造を簡略化することができる。According to such a configuration, the mounting space can be reduced as in the first embodiment, and the semiconductor element can be miniaturized. Moreover, by forming the pad 11 for connection with the wiring pattern 4 of the substrate 2 on the control IC side, the A1 wiring of the solid-state image sensor 1 can be reduced, so that the manufacturing of the solid-state image sensor can be simplified. can.
第５図は、本発明の第３実施例を示すものである。この
第３実施例では、基板２に第１の凹部２ｂを形成し、そ
の中央部に第２の凹部２ｃを形成する。この第２の凹部
２ｃに固体撮像素子１をダイボンドし、固体撮像素子１
の電極パッド１３と第１の凹部２ｂの底面に形成した配
線パターン４をワイヤー５で接続する。固体撮像素子１
の上方には制御用ＩＣ付き透明基板６を配設し、上記配
線パターン４にバンプ１４を介して制御用ＩＣ付き透明
基板６を接続する。最後に、制御用ＩＣ付き基板６の周
囲を遮光用樹脂１６で封止することにより、第５図に示
す半導体素子が完成する。FIG. 5 shows a third embodiment of the invention. In this third embodiment, a first recess 2b is formed in the substrate 2, and a second recess 2c is formed in the center thereof. The solid-state image sensor 1 is die-bonded to this second recess 2c, and the solid-state image sensor 1 is
The electrode pad 13 and the wiring pattern 4 formed on the bottom surface of the first recess 2b are connected by a wire 5. Solid-state image sensor 1
A transparent substrate 6 with a control IC is disposed above the control IC, and the transparent substrate 6 with a control IC is connected to the wiring pattern 4 via bumps 14. Finally, the periphery of the control IC-attached substrate 6 is sealed with a light-shielding resin 16, thereby completing the semiconductor element shown in FIG. 5.
このような構成によれば、第１実施例と同様に実装スペ
ースを小さくでき、半導体素子の小形化を容易に図るこ
とができる。しかも、配線パターン４に固体撮像素子１
と制御用ＩＣ付き透明基板６を間接的に接続でき、かつ
必要な箇所だけを導通させることにより、固体撮像素子
１および制御用ＩＣ付き透明基板６の実装を簡略化でき
る。According to such a configuration, the mounting space can be reduced similarly to the first embodiment, and the semiconductor element can be easily miniaturized. Moreover, the solid-state image sensor 1 is connected to the wiring pattern 4.
Since the transparent substrate 6 with the control IC can be indirectly connected to the transparent substrate 6 with the control IC, and only the necessary parts are electrically connected, the mounting of the solid-state image sensor 1 and the transparent substrate 6 with the control IC can be simplified.
第６図は、本発明の第４実施例を示ずらのである。この
第４実施例は、制御用ＩＣ付き透明基板６に裏面照射型
固体撮像素子２１をダイボンドし、裏面照射型固体撮像
素子２１の電極バッド２３、制御用ＩＣ付き透明基板６
の接続用パッド１１および基板２の配線パターン４の接
続を全てワイヤーボンド５で接続したもので、他の構成
は第２実施例と同様であるので説明を省略する。FIG. 6 shows a fourth embodiment of the present invention. In this fourth embodiment, a back-illuminated solid-state image sensor 21 is die-bonded to a transparent substrate 6 with a control IC, and an electrode pad 23 of the back-illuminated solid-state image sensor 21 is connected to a transparent substrate 6 with a control IC.
The connection pads 11 and the wiring patterns 4 of the substrate 2 are all connected by wire bonds 5, and the other configurations are the same as those of the second embodiment, so the explanation will be omitted.
このような構成によれば、第１実論例と同様に実装スペ
ースを小さくでき、半導体素子の小形化を容易に図るこ
とができる。しかも、バンプを用いずに全ての接続をワ
イヤ二ボンドで行なうことができるため、固体撮像素子
２１および制御用ＩＣ付き透明基板６の実装を簡略化す
ることができる。According to such a configuration, the mounting space can be reduced as in the first practical example, and the semiconductor element can be easily miniaturized. Moreover, since all connections can be made by wire bonding without using bumps, mounting of the solid-state image sensor 21 and the transparent substrate 6 with control IC can be simplified.
第７図は、本発明の第５実施例を示すものである。この
第５実施例は、制御用ＩＣ付き透明基板 を構成する透
明基板７をレンズ状に形成したもので、他の構成は上記
第１実施例と同様であるので説明を省略する。FIG. 7 shows a fifth embodiment of the present invention. In this fifth embodiment, the transparent substrate 7 constituting the transparent substrate with a control IC is formed into a lens shape, and the other configurations are the same as those of the first embodiment, so a description thereof will be omitted.
このような構成によれば、第１実施例と同様に実装スペ
ースを小さくでき、半導体素子の小形化を容易に図るこ
とができる。しかも、透明基板７をレンズとして兼用す
ることにより、ビデオカメラや内視鏡（電子スコープ）
等に組み込まれる光学系のレンズを削減し、もしくは不
要になるため、ビデオカメラや内視鏡の小形化を図るこ
とができる。According to such a configuration, the mounting space can be reduced similarly to the first embodiment, and the semiconductor element can be easily miniaturized. Moreover, by using the transparent substrate 7 as a lens, it can be used for video cameras and endoscopes (electronic scopes).
The number of lenses in the optical system incorporated in the camera or the like can be reduced or eliminated, making it possible to downsize video cameras and endoscopes.
第８図は、本発明の第６実施例を示すものである。この
第６実施例は、第３図に示す制御用ＩＣ付き基板６の透
孔窓９内に、例えばカラーフィルター（無機、有機どち
らでもよい）、赤外線カットフィルター等のフィルター
３１を形成したもので、池の構成は第３図に示す制御用
ＩＣ付き透明基板６と同じであるので説明を省略する。FIG. 8 shows a sixth embodiment of the present invention. In this sixth embodiment, a filter 31, such as a color filter (either inorganic or organic) or an infrared cut filter, is formed in the through-hole window 9 of the control IC-equipped substrate 6 shown in FIG. , the structure of the pond is the same as that of the transparent substrate 6 with control IC shown in FIG. 3, so the explanation will be omitted.
なお、上記フィルター３１に代えて一層もしくは多層か
らなる反射防止膜を形成することができる。Note that instead of the filter 31 described above, an antireflection film consisting of a single layer or multiple layers can be formed.
かつ、上述のフィルター、反射防止膜は透明基板７の両
面に設けることができるとともに、両者を組合わせるこ
ともできる。Moreover, the above-mentioned filter and antireflection film can be provided on both sides of the transparent substrate 7, and they can also be combined.
このような構成によれば、透明基板７にフィルター、反
射防止膜を一体に形成することにより、フィルターまた
は反射防止膜を形成した透明基板を別に設ける必要がな
く、ビデオカメラ等の光学系を簡略化することができる
。According to this configuration, by integrally forming the filter and the antireflection film on the transparent substrate 7, there is no need to separately provide a transparent substrate on which the filter or antireflection film is formed, and the optical system of a video camera or the like can be simplified. can be converted into
第９図は、本発明の第７実施例を示すものである。この
第７実施例は、第３図に示す制御用ＩＣ付き透明基板６
の透孔窓９の周囲に遮光膜４１を形成したもので、池の
構成は第３図に示す制御用ＩＣ付き透明基板６と同じで
あるので説明を省略する。FIG. 9 shows a seventh embodiment of the present invention. This seventh embodiment is based on a transparent substrate 6 with a control IC shown in FIG.
A light-shielding film 41 is formed around a transparent window 9, and the structure of the pond is the same as that of the transparent substrate 6 with a control IC shown in FIG. 3, so a description thereof will be omitted.
このような構成によれば、制御用ＩＣ８に入射する光を
遮光膜４１で遮光することができるため、光の影響によ
るご動作を防止することができる。According to such a configuration, the light that enters the control IC 8 can be blocked by the light shielding film 41, so that operation due to the influence of light can be prevented.
第１０図は、本発明の第８実施例を示すものである。こ
の第８実施例は、基板２の凹部２ａに制御用ＩＣ５１を
ダイホントし、その上に透明基板７の一方の面に一体に
形成した裏面照射型固体撮１象素子５２をバンプ１４を
介して接続し、制御用ＩＣ５１の接続用パッド１１と基
板２の配線パターン４をワイヤー５で接続し、透明基板
７の周囲を遮光用樹脂１６で封止したものである。FIG. 10 shows an eighth embodiment of the present invention. In this eighth embodiment, a control IC 51 is die-bonded in a recess 2a of a substrate 2, and a back-illuminated solid-state sensor 52 integrally formed on one surface of a transparent substrate 7 is mounted on the control IC 51 via a bump 14. The connection pad 11 of the control IC 51 and the wiring pattern 4 of the substrate 2 are connected by a wire 5, and the periphery of the transparent substrate 7 is sealed with a light-shielding resin 16.
このような構成によれば、裏面照射型固体撮像素子５２
と同一の場所に制御用ＩＣ５１を立体的に実装すること
ができるため、従来のものに比べて実装スペースを著し
く小さくでき、半導体素子の小形化を容易に図ることが
できる。また、制御用ＴＣ５１を大きくできるため、第
１実施例で述べた回路以外の回路を容易に組み込むこと
ができる。さらに、普通の裏面照射型固体機ｆ象素子に
おいては、裏面から光が入り易くするなめに薄く削って
いたが、本実施例のように透明基板７に裏面照射型固体
撮１象素子５２を形成することにより、裏面に透明基板
７が形成されるので裏面照射型固体撮像素子５２を薄く
削る工程か不要になり製造を簡略化するこことができる
。According to such a configuration, the back-illuminated solid-state image sensor 52
Since the control IC 51 can be three-dimensionally mounted in the same location as the control IC 51, the mounting space can be significantly reduced compared to the conventional one, and the semiconductor element can be easily miniaturized. Furthermore, since the control TC 51 can be made larger, circuits other than those described in the first embodiment can be easily incorporated. Furthermore, in an ordinary back-illuminated solid-state image sensor, the element is shaved thinly to allow light to easily enter from the back surface, but in this embodiment, a back-illuminated solid-state image element 52 is formed on the transparent substrate 7. By forming the transparent substrate 7 on the back surface, the step of shaving the back-illuminated solid-state image sensor 52 into a thin layer is not necessary, and the manufacturing process can be simplified.
なお、本発明は上記実施例に限定されるものではなく、
要旨を変更しない範囲において種々変形して実施するこ
とがでる。Note that the present invention is not limited to the above embodiments,
Various modifications can be made without changing the gist.
［発明の効果コ
本発明によれは、固体撮像素子と同一の場所に制御用Ｉ
Ｃを実装し固体撮像素子と制御用ＩＣの実装スペースを
小さくすることで、半導体素子の小形化を容易に図り得
る。[Effects of the Invention] According to the present invention, a control I is installed at the same location as the solid-state image sensor.
By mounting C and reducing the mounting space for the solid-state image sensor and control IC, it is possible to easily downsize the semiconductor element.
第１図は本発明を適用した半導体素子の第１実施例を示
す平面図、第２図は第１図のＡ−Ａ線部分で切断した断
面図、第３図は同実施例の要部である制御用ＩＣ付き透
明基板の概略的構成を示す断面図、第４図ないし第１０
図は本発明のそれぞれ異なる他の実施例を示す断面図、
第１１図は従来の半導体素子の概略的構成を示す断面図
である。
■・・・固体撮像素子 ２・・・基板２ａ・・・凹
部 ２ｂ・・・第１の四部２ｃ・・・第２の
凹部 ３・・・電極パッド４・・・配線パターン
５・・・ワイヤー６・・・制御用ＩＣ付き透明基板
７・・・透明基板 ８・・・制御用ＩＣ９・・
・透孔窓 １０・・・Ａ１配線１１・・・接
続用パッド １２・・・パシベーション１３・・・Ｚ
［ｉバッド １４・・・バンプ１５・・・透明樹
脂 １６・・・遮光用樹脂２１・・・裏面照射型
固体撮像素子
２３・・・電極パッド ３１・・・フィルター４１
・・・遮光膜 ５１・・・制御用ＩＣ５２・・
・裏面照射型固体撮像素子
互
第１図
第２図
第４
図
／ １
第
ア
図FIG. 1 is a plan view showing a first embodiment of a semiconductor device to which the present invention is applied, FIG. 2 is a sectional view taken along line A-A in FIG. 1, and FIG. 3 is a main part of the same embodiment. 4 to 10 are cross-sectional views showing the schematic structure of a transparent substrate with a control IC.
The figures are cross-sectional views showing other different embodiments of the present invention,
FIG. 11 is a sectional view showing the schematic structure of a conventional semiconductor element. ■...Solid-state image sensor 2...Substrate 2a...Recess 2b...First four parts 2c...Second recess 3...Electrode pad 4...Wiring pattern
5...Wire 6...Transparent substrate with control IC 7...Transparent substrate 8...Control IC9...
・Through-hole window 10...A1 wiring 11...Connection pad 12...Passivation 13...Z
[i-bad 14...Bump 15...Transparent resin 16...Light-shielding resin 21...Back-illuminated solid-state image sensor 23...Electrode pad 31...Filter 41
... Light shielding film 51 ... Control IC52 ...
・Back-illuminated solid-state image sensor Figure 1 Figure 2 Figure 4 Figure 1 Figure A
Claims (6)
の透明基板の上記固体撮像素子の受光部に対応する透孔
窓の周囲に制御用ＩＣを形成したことを特徴とする半導
体素子。(1) A semiconductor characterized in that a transparent substrate is disposed on the light-receiving surface of the solid-state image sensor, and a control IC is formed around a through-hole window of the transparent substrate corresponding to the light-receiving portion of the solid-state image sensor. element.
止膜を形成したことを特徴とする請求項１記載の半導体
素子。(2) The semiconductor device according to claim 1, characterized in that a filter or an antireflection film is formed on the through-hole window of the transparent substrate.
とを特徴とする請求項１記載の半導体素子。(3) The semiconductor device according to claim 1, further comprising a light shielding member provided around the through-hole window of the transparent substrate.
一体に形成し、この固体撮像素子の下方に制御用ＩＣを
配設したことを特徴とする半導体素子。(4) A semiconductor device characterized in that a back-illuminated solid-state image sensor is integrally formed on one surface of a transparent substrate, and a control IC is disposed below the solid-state image sensor.
を用いたことを特徴とする請求項１〜４記載の半導体素
子。(5) The semiconductor device according to any one of claims 1 to 4, wherein a sapphire substrate, a glass plate, or the like is used as the transparent substrate.
する請求項１〜５記載の半導体素子。(6) The semiconductor device according to any one of claims 1 to 5, wherein the transparent substrate is formed into a lens shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63175675A JPH0226080A (en) | 1988-07-14 | 1988-07-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63175675A JPH0226080A (en) | 1988-07-14 | 1988-07-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0226080A true JPH0226080A (en) | 1990-01-29 |
Family
ID=16000271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63175675A Pending JPH0226080A (en) | 1988-07-14 | 1988-07-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0226080A (en) |
Cited By (10)
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| US6172417B1 (en) * | 1993-06-25 | 2001-01-09 | Lucent Technologies Inc. | Integrated semiconductor devices |
| JP2004241752A (en) * | 2002-05-14 | 2004-08-26 | Canon Inc | Fingerprint input device and its manufacturing method |
| US6890798B2 (en) * | 1999-06-08 | 2005-05-10 | Intel Corporation | Stacked chip packaging |
| WO2007135897A1 (en) * | 2006-05-18 | 2007-11-29 | Hamamatsu Photonics K.K. | Light transmitting/receiving device |
| JP2007311386A (en) * | 2006-05-16 | 2007-11-29 | Nec Electronics Corp | Solid state imaging apparatus |
| JP2009111090A (en) * | 2007-10-29 | 2009-05-21 | Hamamatsu Photonics Kk | Photodetector |
| JP2009111089A (en) * | 2007-10-29 | 2009-05-21 | Hamamatsu Photonics Kk | Photodetector |
| JP2010283380A (en) * | 2003-10-01 | 2010-12-16 | Optopac Inc | Electronic package of photo-sensing semiconductor device, and packaging method thereof |
| WO2021111715A1 (en) * | 2019-12-04 | 2021-06-10 | ソニーセミコンダクタソリューションズ株式会社 | Imaging device and method for manufacturing imaging device |
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| WO2021111715A1 (en) * | 2019-12-04 | 2021-06-10 | ソニーセミコンダクタソリューションズ株式会社 | Imaging device and method for manufacturing imaging device |
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