JPH0226056A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0226056A JPH0226056A JP63176624A JP17662488A JPH0226056A JP H0226056 A JPH0226056 A JP H0226056A JP 63176624 A JP63176624 A JP 63176624A JP 17662488 A JP17662488 A JP 17662488A JP H0226056 A JPH0226056 A JP H0226056A
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- insulating substrate
- metal wire
- transistor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000004020 conductor Substances 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 21
- 238000009413 insulation Methods 0.000 abstract 4
- 230000003321 amplification Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に高周波・高利得増幅用
の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device for high frequency/high gain amplification.
周知の様に、トランジスタの接地インダクタンスとトラ
ンジスタの利得には、関係があり、接地インダクタンス
が少ない回路構成はど高い利得が得られる。従って、高
利得を得ようとする回路構成では、トランジスタの接地
インダクタンスを極力少なくする必要がある。As is well known, there is a relationship between the ground inductance of a transistor and the gain of the transistor, and a circuit configuration with a small ground inductance can provide a high gain. Therefore, in a circuit configuration in which high gain is to be obtained, it is necessary to reduce the ground inductance of the transistor as much as possible.
第２図（ａ）〜（Ｃ）は従来の半導体装置を説明するた
めの半導体チップの平面図と切欠側面図及びＢ−Ｂ’線
断面図である。FIGS. 2A to 2C are a plan view, a cutaway side view, and a sectional view taken along the line BB' of a semiconductor chip for explaining a conventional semiconductor device.
第２図（ａ）〜（Ｃ）に示すように、絶縁基板１の上面
に設けた導体層２の上にトランジスタチップ３のコレク
タを接続するようにマウントし、導体層２の三方を取囲
むようにして絶縁基板１の上面に導体層５を設け、トラ
ンジスタチップ３のエミッタと金属線４で接続する。次
に、導体層２の上に空間を有してまたいだ状態で導体層
５と接続したブリッジ１２を設け、金属線１３によりト
ランジスタチップ３のエミッタと接続する。導体層５を
挟んで導体層２と反対側の絶縁基板１の上面に導体層７
を設け、金属線６でトランジスタチップのベースと接続
する。次に、絶縁基板１の下面に導体層１０を設け、絶
縁基板１を貫通して設けたスルーホール１１により導体
層５と導体層１０を電気的に接続する。As shown in FIGS. 2(a) to (C), the collector of the transistor chip 3 is mounted on the conductor layer 2 provided on the upper surface of the insulating substrate 1 so as to be connected, and the conductor layer 2 is surrounded on three sides. A conductor layer 5 is provided on the upper surface of the insulating substrate 1 so as to be connected to the emitter of the transistor chip 3 by a metal wire 4. Next, a bridge 12 connected to the conductor layer 5 is provided so as to straddle the conductor layer 2 with a space therebetween, and is connected to the emitter of the transistor chip 3 by a metal wire 13 . A conductor layer 7 is formed on the upper surface of the insulating substrate 1 on the opposite side of the conductor layer 2 with the conductor layer 5 in between.
is provided and connected to the base of the transistor chip with a metal line 6. Next, a conductor layer 10 is provided on the lower surface of the insulating substrate 1, and the conductor layer 5 and the conductor layer 10 are electrically connected through a through hole 11 provided through the insulating substrate 1.
上述した従来の半導体装置は、トラジスタチップをマウ
ントした導体層の上をまたいでブリッジをマウントし、
ブリッジとトランジスタのエミッタを金属線で接続し、
絶縁基板の下面に設けた導体層とスルーホールを介して
接続し、接地していた。このため、トランジスタのエミ
ッタの接地インダクタンスが大きくなり、半導体装置の
利得が低下するという問題点があった。In the conventional semiconductor device described above, a bridge is mounted across a conductor layer on which a transistor chip is mounted.
Connect the bridge and the emitter of the transistor with a metal wire,
It was connected to the conductor layer provided on the bottom surface of the insulating substrate via a through hole and grounded. For this reason, there is a problem in that the grounded inductance of the emitter of the transistor increases, and the gain of the semiconductor device decreases.
本発明の半導体装置は、絶縁基板の上面に設けた素子載
置用の第１の導体層と、前記第１の導体層にコレクタを
接続してマウントされたトランジスタチップと、前記第
１の導体層の周囲を取囲んで前記絶縁基板の上面に設け
且つ前記トランジスタチップのエミッタと金属線で接続
した第２の導体層と、前記第２の導体層の一方の外側の
前記絶縁基板の上面に設け且つ前記トランジスタチップ
のベースと金属線で接続した第３の導体層と、前記第２
の導体層の他方の外側の前記絶縁基板の上面に設け且つ
前記第１の導体層と金属線で接続した第４の導体層と、
前記絶縁基板の下面に設けた第５の導体層と、前記絶縁
基板を貫通して設け前記第２の導体層と前記第５の導体
層とを電気的に接続するスルーホールとを備えている。The semiconductor device of the present invention includes: a first conductor layer for mounting an element provided on an upper surface of an insulating substrate; a transistor chip mounted with a collector connected to the first conductor layer; a second conductor layer surrounding the periphery of the layer and provided on the upper surface of the insulating substrate and connected to the emitter of the transistor chip with a metal wire; and on the upper surface of the insulating substrate outside one of the second conductor layers. a third conductor layer provided and connected to the base of the transistor chip by a metal wire;
a fourth conductor layer provided on the upper surface of the insulating substrate outside the other conductor layer and connected to the first conductor layer with a metal wire;
A fifth conductor layer provided on the lower surface of the insulating substrate, and a through hole provided through the insulating substrate to electrically connect the second conductor layer and the fifth conductor layer. .
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（Ｃ）は本発明の一実施例を説明するた
めの半導体チップの平面図と切欠側面図及びＡ−Ａ’線
断面図である。FIGS. 1A to 1C are a plan view, a cutaway side view, and a cross-sectional view taken along the line AA' of a semiconductor chip for explaining an embodiment of the present invention.
第１図（ａ）−、−（Ｃ）に示すように、絶縁基板１の
上面に設けた素子載置用の第１の導体層２と、導体層２
にコレクタを接続してマウントされたトランジスタチッ
プ３と、導体層２の周囲を取囲んで絶縁基板１の上面に
設け且つトランジスタチップ３のエミッタと金属線４で
接続した第２の導体層５と、導体層５の一方の外側の絶
縁基板１の上面に設け且つトランジスタチップ３のベー
スと金属線６で接続した第３の導体Ｍ７と、導体層５の
他方の外側の絶縁基板１の上面に設け且つ導体層２と金
属線８で接続した第４の導体層９と、絶縁基板１の下面
に設けた第５の導体層１０と、絶縁基板１を貫通して設
け導体層５と導体層１０とを電気的に接続するスルーホ
ール１１とを備えて半導体装置を構成する。As shown in FIGS. 1(a)- and 1-(C), a first conductor layer 2 for mounting an element provided on the upper surface of an insulating substrate 1, and a conductor layer 2 provided on the upper surface of an insulating substrate 1.
a transistor chip 3 mounted with the collector connected to the transistor chip 3; and a second conductor layer 5 surrounding the conductor layer 2, provided on the upper surface of the insulating substrate 1, and connected to the emitter of the transistor chip 3 by a metal wire 4. , a third conductor M7 provided on the top surface of the insulating substrate 1 on one outside of the conductor layer 5 and connected to the base of the transistor chip 3 with a metal wire 6; A fourth conductor layer 9 provided and connected to the conductor layer 2 by a metal wire 8, a fifth conductor layer 10 provided on the lower surface of the insulating substrate 1, a conductor layer 5 provided through the insulating substrate 1, and a conductor layer A semiconductor device includes a through hole 11 that electrically connects the semiconductor device 10 and the semiconductor device 10 .
以上説明した様に本発明は、トランジスタチップをマウ
ントした第１の導体層と第１の導体層の周囲を取囲む第
２の導体層を設けてトランジスタチップのエミッタと第
２の導体層とを金属線で接続することにより、エミッタ
の接地インダクタンスを低減させ、半導体装置の利得を
向上させるという効果を有する。As explained above, the present invention provides a first conductor layer on which a transistor chip is mounted and a second conductor layer surrounding the first conductor layer to connect the emitter of the transistor chip and the second conductor layer. Connecting with a metal wire has the effect of reducing the grounding inductance of the emitter and improving the gain of the semiconductor device.
第１図（ａ）〜（Ｃ）は本発明の一実施例を説明するた
めの半導体チップの平面図と切欠側面図及びＡ−Ａ’線
断面図、第２図（ａ）〜（Ｃ）は従来の半導体装置を説
明するための半導体チップの平面図と切欠側面図及びＢ
−Ｂ’線断面図である。
１・・・絶縁基板、２・・・導体層、３・・・トランジ
スタチップ、４・・・金属線、５・・・導体層、６・・
・金属線、７・・・導体層、８・・・金属線、９．１０
・・・導体層、１１・・・スルーホール、１２・・・ブ
リッジ、１３・・・金属線。FIGS. 1(a) to (C) are a plan view, a cutaway side view, and a sectional view taken along line A-A' of a semiconductor chip for explaining one embodiment of the present invention, and FIGS. 2(a) to (C) are B is a plan view and a cutaway side view of a semiconductor chip for explaining a conventional semiconductor device.
-B' line sectional view. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Conductor layer, 3... Transistor chip, 4... Metal wire, 5... Conductor layer, 6...
・Metal wire, 7... Conductor layer, 8... Metal wire, 9.10
...Conductor layer, 11...Through hole, 12...Bridge, 13...Metal wire.
Claims (1)
前記第１の導体層にコレクタを接続してマウントされた
トランジスタチップと、前記第１の導体層の周囲を取囲
んで前記絶縁基板の上面に設け且つ前記トランジスタチ
ップのエミッタと金属線で接続した第２の導体層と、前
記第２の導体層の一方の外側の前記絶縁基板の上面に設
け且つ前記トランジスタチップのベースと金属線で接続
した第３の導体層と、前記第２の導体層の他方の外側の
前記絶縁基板の上面に設け且つ前記第１の導体層と金属
線で接続した第４の導体層と、前記絶縁基板の下面に設
けた第５の導体層と、前記絶縁基板を貫通して設け前記
第２の導体層と前記第５の導体層とを電気的に接続する
スルーホールとを備えたことを特徴とする半導体装置。A first conductor layer for mounting an element provided on the upper surface of the insulating substrate;
a transistor chip mounted with the collector connected to the first conductor layer; and a transistor chip mounted on the upper surface of the insulating substrate surrounding the first conductor layer and connected to the emitter of the transistor chip with a metal wire. a second conductor layer; a third conductor layer provided on the upper surface of the insulating substrate outside one of the second conductor layers and connected to the base of the transistor chip with a metal wire; and the second conductor layer. a fourth conductor layer provided on the top surface of the other outside of the insulating substrate and connected to the first conductor layer with a metal wire; a fifth conductor layer provided on the bottom surface of the insulating substrate; 1. A semiconductor device comprising: a through hole that is provided to penetrate through and electrically connect the second conductor layer and the fifth conductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63176624A JPH0226056A (en) | 1988-07-14 | 1988-07-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63176624A JPH0226056A (en) | 1988-07-14 | 1988-07-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0226056A true JPH0226056A (en) | 1990-01-29 |
Family
ID=16016833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63176624A Pending JPH0226056A (en) | 1988-07-14 | 1988-07-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0226056A (en) |
-
1988
- 1988-07-14 JP JP63176624A patent/JPH0226056A/en active Pending
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