JPH02260540A - Mis type semiconductor device - Google Patents
Mis type semiconductor deviceInfo
- Publication number
- JPH02260540A JPH02260540A JP8106789A JP8106789A JPH02260540A JP H02260540 A JPH02260540 A JP H02260540A JP 8106789 A JP8106789 A JP 8106789A JP 8106789 A JP8106789 A JP 8106789A JP H02260540 A JPH02260540 A JP H02260540A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- diffusion layer
- silicide
- point metal
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 238000002844 melting Methods 0.000 claims description 7
- 230000008018 melting Effects 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＭＩＳ型半導体装置の構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of a MIS type semiconductor device.
半導体装置の微細化、高集積化にともないＭＯ８型トラ
ンジスタも微細化されてきている。しかし、素子寸法を
微細化することによりホットキャリアによる特性劣化と
いう問題が生じてきている。As semiconductor devices become smaller and more highly integrated, MO8 type transistors are also becoming smaller. However, miniaturization of element dimensions has led to the problem of deterioration of characteristics due to hot carriers.
この問題を解決するためＬＤＤ （Ｌｉｇｈｔ １ｙＰ
ｏｐｅｄ Ｄｒａｉｎ）という構造が提案されている
が、このＬＤＤをさらに改良した構造が次の文献に掲載
されても−する。、（Ｒ，ＩＺＡＷＡ。To solve this problem, LDD (Light 1yP
A structure called "opened drain" has been proposed, but a structure that is a further improvement of this LDD is published in the following literature. ,(R,IZAWA.
Ｔ、ＫＵＲＥ、Ｅ、ＴＡＫＥＤＡ、 ’ＴＨＥ Ｉ
ＭＰＡＣＴ ＯＦ ＧＡＴＥ−ＤＲＡＩＮ ０Ｖ
ＥＲＬＡＰＰＥＤ ＬＤＤ （ＧＯＬＤ） ＦＯＲ
ＤＥＥＰ ＳＵＢ ＭＩＣＲＯＮ ＶＬＳＩ’Ｓ
’、ＩＥＤＭ Ｔｅｃｈ、Ｄｉｉ Ｄｐ３８−ｐｐ
４１ １９８７）
〔発明が解決しようとする課題〕
しかし、前述の従来技術では、製造プロセスがかなり複
雑であり、低濃度不純物拡散層の寸法制御性が悪く、ゲ
ート電極の段差が大きいために、平坦性が悪いという課
題を有する。T,KURE,E,TAKEDA,'THE I
MPACT OF GATE-DRAIN 0V
ERLAPPED LDD (GOLD) FOR
DEEP SUB MICRON VLSI'S
', IEDM Tech, Dii Dp38-pp
41 1987) [Problems to be Solved by the Invention] However, with the above-mentioned conventional technology, the manufacturing process is quite complicated, the dimensional control of the low concentration impurity diffusion layer is poor, and the step of the gate electrode is large, so it is difficult to achieve a flat surface. It has the problem of poor sex.
そこで本発明はこのような課題を解決するもので、その
目的とするところは、製造プロセスが容易であり、寸法
制御性、平坦性が良好な半導体装置を提供するところに
ある。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a semiconductor device that is easy to manufacture and has good dimensional controllability and flatness.
本発明のＭＩＳ型半導体装置は、ゲート電極が、多結晶
ＳＬと、少くともその側壁に設けられた高融点金属シリ
サイドからなり、第１導電型半導体基板に設けられた第
２導電型紙濃度不純物拡散層が、ゲート絶縁膜をはさみ
、前記高融点金属シリサイドの直下に位置することを特
徴とする。In the MIS type semiconductor device of the present invention, the gate electrode is made of a polycrystalline SL and a high melting point metal silicide provided at least on the sidewall thereof, and a second conductivity type paper provided in the first conductivity type semiconductor substrate is impurity-diffused. The semiconductor device is characterized in that the layers sandwich a gate insulating film and are located directly below the high melting point metal silicide.
以下図面を用いて、本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図は本発明による半導体装置を表わす断面図であり
、１０１はＰ型Ｓｔ基板、１０２は素子分離用酸化膜、
１０３はゲート酸化膜、１０４はゲート電極であり、多
結晶シリコン１０４′と、その上部及び側壁を覆ったＴ
ｉシリサイド１０４′により形成されている。１０５は
低濃度Ｎ型不純物拡散層、１０６は高濃度不純物拡散層
であり、図で示したように前記低濃度不純物拡散層１０
５はゲート酸化膜１０３をはさんで前記ゲート電極１０
４側壁部の前記Ｔｉシリサイド１０４′の下部に配置さ
れている。この構造はゲート電極とドレイン部がオーバ
ラップした、いわゆるＧＯＬＤ構造であり、この構造を
用いることにより、ホットキャリアによるコンダクタン
スの劣化が避けられることは言うまでもない。FIG. 1 is a cross-sectional view showing a semiconductor device according to the present invention, in which 101 is a P-type St substrate, 102 is an oxide film for element isolation,
103 is a gate oxide film, 104 is a gate electrode, which includes polycrystalline silicon 104' and a T layer covering the upper and side walls thereof.
It is formed of i-silicide 104'. 105 is a low concentration N-type impurity diffusion layer, 106 is a high concentration impurity diffusion layer, and as shown in the figure, the low concentration impurity diffusion layer 10
5 is the gate electrode 10 with the gate oxide film 103 in between.
The Ti silicide 104' is disposed under the Ti silicide 104' of the fourth side wall portion. This structure is a so-called GOLD structure in which the gate electrode and the drain portion overlap, and it goes without saying that by using this structure, conductance deterioration due to hot carriers can be avoided.
次に本発明の製造方法を簡単に示す。Next, the manufacturing method of the present invention will be briefly described.
１）Ｐ型Ｓｔ基板１０１上にＬＯＣＯ３法で素子分離用
酸化膜１０２を２０００〜７０００Ａ形成するした後に
、ゲート酸化膜１０３を熱酸化法により１００〜３００
人形成する。1) After forming the element isolation oxide film 102 with a thickness of 2000 to 7000A on the P-type St substrate 101 using the LOCO3 method, a gate oxide film 103 with a thickness of 100 to 300A is formed using the thermal oxidation method.
Form people.
２）多結晶Ｓｔを全面にＣＶＤ法で１０００〜５０００
人形成し、Ｎ型不純物を拡散法で注入した後フォトエツ
チングすることで、ゲート電極の１部１０４′を形成す
る。2) Polycrystalline St is coated with 1000 to 5000 by CVD method on the entire surface.
A portion 104' of the gate electrode is formed by forming a gate electrode, injecting an N-type impurity by a diffusion method, and then photoetching.
３）前記ゲート電極の１部（多結晶Ｓｉパターン）１０
４′をマスクにＡｓ５Ｐ等をＤＯ３Ｅ量１０日〜１０Ｉ
４の範囲でイオン注入し、低濃度不純物拡散層１０５を
形成する。3) Part of the gate electrode (polycrystalline Si pattern) 10
Using 4′ as a mask, apply As5P etc. to DO3E amount for 10 days to 10 I.
Ions are implanted in a range of 4 to form a low concentration impurity diffusion layer 105.
４）全面にスパッタ法でＴｉを２００〜１０００人形成
し、ハロゲンランプを用い、８００℃前後の温度で３０
ｓｅｃ程度アニールを行うことにより、前記多結晶５１
１０４’の上面及び側面にＴｉシリサイド１０４′が形
成される。未反応Ｔｉは、この後に選択エッチ液（アン
モニアと過酸化水素の混合水溶液）を用いて除去する。4) Form 200 to 1,000 layers of Ti on the entire surface by sputtering, and heat for 30 minutes at a temperature of around 800°C using a halogen lamp.
By performing annealing for about sec, the polycrystalline 51
Ti silicide 104' is formed on the top and side surfaces of 104'. Unreacted Ti is then removed using a selective etchant (mixed aqueous solution of ammonia and hydrogen peroxide).
この工程により多結晶５Ｌ１０４’の上部及び側壁をＴ
ｉシリサイド１０４′が覆った形のゲート電極１０４が
完成する。Through this process, the upper and side walls of the polycrystalline 5L104' are
A gate electrode 104 covered with i-silicide 104' is completed.
５）前記ゲート電極１０４をマスクにＡｓ、Ｐ等をＤＯ
ＳＥ量１０１５〜１０Ｉ６の範囲でイオン注入し、熱ア
ニールすることで、高濃度不純物拡散層１０６を形成し
、本発明の半導体装置は完成する。5) Do As, P, etc. using the gate electrode 104 as a mask
By implanting ions with an SE amount in the range of 1015 to 10I6 and thermal annealing, a high concentration impurity diffusion layer 106 is formed, and the semiconductor device of the present invention is completed.
以上実施例を用いて、本発明の半導体装置を説明してき
たが、本発明の主旨を逸脱しない範囲で種々変更可能な
ことは言うまでもない。Although the semiconductor device of the present invention has been described above using embodiments, it goes without saying that various changes can be made without departing from the gist of the present invention.
例えば本実施例ではゲート電極の上部、側壁にＴｉシリ
サイドが設けられているが側壁だけでもかまわない。ま
たシリサイドに用いる高融点金属は、Ｔｉ以外に、Ｃｏ
ｓ Ｎ ｔ ＳＰ ｔ ｓ Ｗ−、Ｔ ａ ｓＭｏ等
でもよい。また本実施例ではＮｃｈＴｒを用いたが、Ｐ
ｃｈＴｒにも適用しうる。For example, in this embodiment, Ti silicide is provided on the top and side walls of the gate electrode, but it is also possible to use only the side walls. In addition to Ti, the high melting point metal used for silicide is Co.
s N t SP t s W-, Ta sMo, etc. may be used. In addition, although NchTr was used in this example, P
It can also be applied to chTr.
本発明によれば、実施例で示したように製造プロセスが
非常に容易であり、低濃度不純物拡散層の寸法は高融点
金属の膜厚により容易に制御しうる。また、ゲート電極
は初期の多結晶Ｓｔの膜厚に比較し問題になるほどの膜
厚増加はないため、平桿性は良い。さらに高融点金属シ
リサイドによりゲート配線の低抵抗もはかられた、すぐ
れたＧＯＬＤ構造の半導体装置を提供できるという効果
を有する。According to the present invention, as shown in the examples, the manufacturing process is very easy, and the dimensions of the low concentration impurity diffusion layer can be easily controlled by controlling the film thickness of the high melting point metal. Further, since the thickness of the gate electrode does not increase so much as to cause a problem compared to the initial film thickness of polycrystalline St, the flatness of the gate electrode is good. Furthermore, it is possible to provide a semiconductor device with an excellent GOLD structure in which the gate wiring has low resistance due to the high melting point metal silicide.
【図面の簡単な説明】 第１図は本発明の半導体装置を表わす主要断面図。 １０１ ・ １０２・ １０３・ １０４ Φ Ｐ型Ｓｔ基板 素子分離用酸化膜 ゲート酸化膜 ゲート電極 １０４′ １０４′ １０５・ １０６・ 多結晶５ｔ Ｔｉシリサイド 低濃度Ｎ型不純物拡散層 高濃度Ｎ型不純物拡散層 以 出願人 セイコーエプソン株式会社[Brief explanation of drawings] FIG. 1 is a main sectional view showing a semiconductor device of the present invention. 101・ 102・ 103・ 104Φ P type St substrate Oxide film for element isolation gate oxide film gate electrode 104' 104' 105・ 106・ polycrystalline 5t Ti silicide Low concentration N-type impurity diffusion layer High concentration N type impurity diffusion layer Below Applicant: Seiko Epson Corporation
Claims (1)
れた高融点金属シリサイドからなり、第１導電型半導体
基板に設けられた第２導電型紙濃度不純物拡散層が、ゲ
ート絶縁膜をはさみ、前記高融点金属シリサイドのほぼ
直下に位置することを特徴とするＭＩＳ型半導体装置。The gate electrode is made of polycrystalline Si and high melting point metal silicide provided at least on the side walls thereof, and a second conductivity type paper concentration impurity diffusion layer provided on the first conductivity type semiconductor substrate sandwiches the gate insulating film. An MIS type semiconductor device characterized by being located almost directly under a high melting point metal silicide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8106789A JPH02260540A (en) | 1989-03-31 | 1989-03-31 | Mis type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8106789A JPH02260540A (en) | 1989-03-31 | 1989-03-31 | Mis type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02260540A true JPH02260540A (en) | 1990-10-23 |
Family
ID=13736049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8106789A Pending JPH02260540A (en) | 1989-03-31 | 1989-03-31 | Mis type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02260540A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596207A (en) * | 1994-04-08 | 1997-01-21 | Texas Instruments Incorporated | Apparatus and method for detecting defects in insulative layers of MOS active devices |
| US6004831A (en) * | 1991-09-25 | 1999-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating a thin film semiconductor device |
-
1989
- 1989-03-31 JP JP8106789A patent/JPH02260540A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6004831A (en) * | 1991-09-25 | 1999-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating a thin film semiconductor device |
| US6979840B1 (en) * | 1991-09-25 | 2005-12-27 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistors having anodized metal film between the gate wiring and drain wiring |
| US5596207A (en) * | 1994-04-08 | 1997-01-21 | Texas Instruments Incorporated | Apparatus and method for detecting defects in insulative layers of MOS active devices |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH02260540A (en) | Mis type semiconductor device | |
| JPH02271674A (en) | Semiconductor device | |
| JPH0368133A (en) | Solid phase diffusion | |
| JPS62266829A (en) | Formation of shallow junction layer | |
| JPH02298074A (en) | Mos transistor and manufacture thereof | |
| JP2001036078A5 (en) | ||
| JPH05110005A (en) | Mos type transistor semiconductor device and manufacture thereof | |
| JPH02288341A (en) | Mis-type semiconductor device | |
| JP2926897B2 (en) | Method for manufacturing semiconductor device | |
| JPH0319370A (en) | Semiconductor device | |
| JPH0227769A (en) | Semiconductor device | |
| JPH1074848A (en) | Manufacture of semiconductor storage device | |
| JPH04303944A (en) | Manufacture of semiconductor device | |
| JPH04112579A (en) | Mos type semiconductor device | |
| JP2623711B2 (en) | Semiconductor device | |
| JPS61251163A (en) | Manufacture of bi-mis integrated circuit | |
| JPS613461A (en) | Manufacture of semiconductor device | |
| JPS6379377A (en) | Manufacture of mis-fet | |
| JPH021943A (en) | Manufacture of semiconductor device | |
| JPH11145425A (en) | Manufacture of semiconductor element and semiconductor device | |
| JP2601209B2 (en) | Method for manufacturing semiconductor device | |
| JP3108927B2 (en) | Method for manufacturing semiconductor device | |
| JPS61251164A (en) | Manufacture of bi-mis integrated circuit | |
| JPS616867A (en) | Manufacture of semiconductor device | |
| JPH08204192A (en) | Mos semiconductor device and its manufacture |