JPH0226029A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0226029A JPH0226029A JP17597188A JP17597188A JPH0226029A JP H0226029 A JPH0226029 A JP H0226029A JP 17597188 A JP17597188 A JP 17597188A JP 17597188 A JP17597188 A JP 17597188A JP H0226029 A JPH0226029 A JP H0226029A
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive layer
- wiring
- semiconductor device
- organic molecule
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 9
- 230000001681 protective effect Effects 0.000 claims abstract description 6
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims abstract description 3
- 208000028659 discharge Diseases 0.000 claims abstract description 3
- 239000011737 fluorine Substances 0.000 claims abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000007797 corrosion Effects 0.000 abstract description 4
- 238000005260 corrosion Methods 0.000 abstract description 4
- 238000009832 plasma treatment Methods 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 239000002120 nanofilm Substances 0.000 description 7
- 238000002161 passivation Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 102100034523 Histone H4 Human genes 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法、特に配線の形成方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming wiring.
従来の技術
半導体装置の配線材料としてはA2合金が一般に用いら
れる。そして、へβ合金上には素子を保護するためのパ
ッシベーション膜が形成される。2. Description of the Related Art A2 alloy is generally used as a wiring material for semiconductor devices. Then, a passivation film is formed on the β alloy to protect the element.
従来の半導体装@製造方法の一例として、MO8型半導
体装置の製造工程を第2図(a)〜(C)を参照して説
明する。なお、第2図はAρ配線形成工程からパッシベ
ーション膜形成工程までを示しており、簡明化のため、
トランジスタ領域は示していない。As an example of a conventional semiconductor device manufacturing method, the manufacturing process of an MO8 type semiconductor device will be described with reference to FIGS. 2(a) to 2(C). Note that FIG. 2 shows the steps from the Aρ wiring formation process to the passivation film formation process, and for the sake of simplicity,
Transistor regions are not shown.
第2図(a)に示すように、まず、シリコン基板1の上
の回路素子(図示せず)上に形成された酸化ケイ素膜2
をさらに覆うようにAρ膜を形成し、この/l膜をホト
レジスト4をマスクとしてドライエツチングすることに
よりへλ配[13が形成される。このドライエツチング
に、たとえば、8Cflx 、Cj22などのガスが用
いられる。引き続き、第2図(b)に示すように、o2
プラズマによってホトレジスト4を除去した後、たとえ
ば450℃のN2 /H2混合ガス雰囲気下でへρシン
ター処理をほどこす。次に、第2図(C)に示すように
、パッシベーション膜としての窒化ケイ素膜6をS i
H4/N)+3混合ガスを用いたプラズマ放電処理に
よって形成する。この後ボンデ゛イングパッド上の窒化
ケイ素膜6を開孔して完成する。As shown in FIG. 2(a), first, a silicon oxide film 2 is formed on a circuit element (not shown) on a silicon substrate 1.
An Aρ film is further formed to cover the Aρ film, and this /l film is dry-etched using the photoresist 4 as a mask, thereby forming a λ pattern [13]. For example, a gas such as 8Cflx or Cj22 is used for this dry etching. Subsequently, as shown in FIG. 2(b), o2
After the photoresist 4 is removed by plasma, a ρ sintering process is performed, for example, in an N2/H2 mixed gas atmosphere at 450°C. Next, as shown in FIG. 2(C), a silicon nitride film 6 as a passivation film is formed by Si
It is formed by plasma discharge treatment using H4/N)+3 mixed gas. After this, the silicon nitride film 6 on the bonding pad is opened and completed.
発明が解決しようとする課題
しかしながら、このようにして行われる半導体装置の製
造方法におい、では、AA配線3間の間隔が狭い個所で
は、窒化ケイ素膜6の段差被覆性が悪くなり、クラック
7が生じやすい。窒化ケイ素模6にクラック7が発生す
ると、半導体装置を使用中に外部から水分や不純物が装
置内に浸入し、へΩ配線3が腐食し断線するという重大
な問題が生じる。Problems to be Solved by the Invention However, in the semiconductor device manufacturing method performed in this manner, the step coverage of the silicon nitride film 6 deteriorates in areas where the distance between the AA wirings 3 is narrow, and cracks 7 occur. Easy to occur. If a crack 7 occurs in the silicon nitride pattern 6, a serious problem arises in that moisture and impurities enter the semiconductor device from the outside during use, corroding the ohm wiring 3 and causing disconnection.
本発明は上記問題を解決するもので、窒化ケイ素膜6に
クラックが生じてもへρ配83が腐食して断線すること
のない半導体装置の製造方法を提供することを目的とす
るものである。The present invention solves the above-mentioned problem, and aims to provide a method for manufacturing a semiconductor device in which even if cracks occur in the silicon nitride film 6, the ρ wiring 83 will not corrode and disconnect. .
課題を解決するための手段
上記問題を解決するために本発明は、導電層形成後、C
およびFを含むガス、たとえば、CF4もしくはCHF
Iガスを用いたプラズマ処理をほどこすことにより、′
4電層を有機分子膜で被覆し、その上に保護被膜をほど
こすように構成したものである。Means for Solving the Problems In order to solve the above problems, the present invention provides that after forming a conductive layer, C
and F-containing gases such as CF4 or CHF
By applying plasma treatment using I gas,
The structure is such that a four-electrode layer is covered with an organic molecular film, and a protective film is applied on top of the organic molecular film.
作用
上記構成により、水分や不純物が保護被膜であるパッシ
ベーション膜を透過して浸入しても、導電層であるへρ
配線が有機分子被膜で覆われているため、導電層腐食を
防止でき、半導体装置の信頼性を向上することができる
。Effect With the above configuration, even if moisture or impurities penetrate through the passivation film, which is a protective film, they will not penetrate into the conductive layer.
Since the wiring is covered with the organic molecule film, corrosion of the conductive layer can be prevented and the reliability of the semiconductor device can be improved.
実施例 以下本発明の一実施例を図面に基づいて説明する。Example An embodiment of the present invention will be described below based on the drawings.
第1図は本発明の一実施例を示す半導体装置の製造方法
の工程順断面図であり、これを用いて説明する。なお、
簡明化のためあえてトランジスター領域は示していない
。FIG. 1 is a step-by-step sectional view of a method for manufacturing a semiconductor device showing an embodiment of the present invention, and will be explained using this. In addition,
For the sake of simplicity, the transistor region is intentionally not shown.
第1図(a)に示すように、まず、シリコン基板1の上
の回路素子(図示せず)上に形成された酸化ケイ素膜2
をさらに覆うようにへρ模を形成し、このAAHをホト
レジスト4をマスクとしてドライエツチングすることに
よりAρ配線3が形成される。このドライエツチングに
、たとえば゛、8CΩ3/CΩ2/N2の混合ガスを用
いる。引き続いて、第1図(b)に示すように、02プ
ラズマ処理によってホトレジスト4を除去した後、たと
えば450℃のN2/1−12混合ガス雰囲気下でAρ
レシンーを実施する。次に、第1図(C)に示すように
たとえばCF4ガスを用いたプラズマ処理をほどこし、
Aρ配線3の上面および側壁に有機分子膜5を成長させ
る。この後第1図(d)に示すように、パッシベーショ
ン膜として、5in4/NH3混合ガスを用いたプラズ
マCVD法によって窒化ケイ素腰6を形成する。このと
きの熱処理温度は約300℃であるが、上記有機分子W
!5は分解しない。引き続き、ポンディングパッド上の
窒化ケイ素膜6を開孔して完成する。As shown in FIG. 1(a), first, a silicon oxide film 2 is formed on a circuit element (not shown) on a silicon substrate 1.
A ρ pattern is formed to further cover the AAH, and the AAH is dry-etched using the photoresist 4 as a mask, thereby forming the Aρ wiring 3. For this dry etching, for example, a mixed gas of 8 CΩ3/CΩ2/N2 is used. Subsequently, as shown in FIG. 1(b), after removing the photoresist 4 by 02 plasma treatment, Aρ
Perform training. Next, as shown in FIG. 1(C), plasma treatment using, for example, CF4 gas is performed,
An organic molecular film 5 is grown on the top surface and sidewalls of the Aρ wiring 3. Thereafter, as shown in FIG. 1(d), a silicon nitride film 6 is formed as a passivation film by plasma CVD using a 5in4/NH3 mixed gas. The heat treatment temperature at this time is about 300°C, but the organic molecule W
! 5 does not disassemble. Subsequently, the silicon nitride film 6 on the bonding pad is completed.
なお、有機分子膜5は分析の結果、炭素(C)とフッ素
(F)が主な構成元素であることが判明した。本実施例
で有機分子膜の形成にCF4ガスを用いたが、Cおよび
Fを含むその他のガスを用いても同様の効果を期待でき
る。As a result of analysis, it was found that the main constituent elements of the organic molecular film 5 were carbon (C) and fluorine (F). Although CF4 gas was used to form the organic molecular film in this example, similar effects can be expected by using other gases containing C and F.
次に、その実施例を説明する。模厚0.8μm。Next, an example thereof will be explained. Model thickness 0.8 μm.
線幅1.8μm、配線間隔1.8μm、長さ6x101
μmのAj2−1wt%S i −0,5wt%Cu配
線パターンを用いて、加速野命試験(温度85℃、相対
湿度85%、テスト時間1000時間)を行ったところ
、本実施例の場合のへΩ断線不良率は従来例の場合の2
0%であった。なお、どちらの場合も、パッシベーショ
ン膜として厚さ0.5μmの窒化ケイ素膜を用いた。Line width 1.8μm, line spacing 1.8μm, length 6x101
When an accelerated field test (temperature 85°C, relative humidity 85%, test time 1000 hours) was conducted using μm Aj2-1wt%S i -0.5wt%Cu wiring pattern, it was found that in the case of this example The Ω disconnection defect rate is 2 compared to the conventional example.
It was 0%. Note that in both cases, a silicon nitride film with a thickness of 0.5 μm was used as the passivation film.
発明の効果
以上のように、本発明によれば、有機分子膜が導’RM
と浸入した水との反応のバリアとなるため、導電層の腐
食が防止できる。Effects of the Invention As described above, according to the present invention, the organic molecular film
It acts as a barrier to the reaction between the metal and the infiltrated water, thus preventing corrosion of the conductive layer.
第1図(a)〜(d)は本発明の一実施例の製造工程を
示す断面図、第2図(a)〜(C)は従来の製造工程を
示す断面図である。
1・・・シリコン基板、2・・・酸化ケイ素膜、3・・
・AI2配線(導電層)、5・・・有機分子膜、6・・
・窒化ケイ素l1l(パッシベーション膜、保護被膜)
。
代理人 森 本 鶴 弘
第
図
第2図FIGS. 1(a) to (d) are cross-sectional views showing the manufacturing process of an embodiment of the present invention, and FIGS. 2(a) to (C) are cross-sectional views showing the conventional manufacturing process. 1... Silicon substrate, 2... Silicon oxide film, 3...
・AI2 wiring (conductive layer), 5... organic molecular film, 6...
・Silicon nitride l1l (passivation film, protective film)
. Agent Hiroshi Tsuru Morimoto Figure 2
Claims (1)
形成した後、前記導電層に炭素およびフッ素を含むガス
を用いてプラズマ放電処理をほどこし、前記導電層の上
部表面および側面に有機分子膜を形成し、その上に保護
被膜をほどこす半導体装置の製造方法。1. After forming a conductive layer on a semiconductor substrate directly or via an intermediate layer, the conductive layer is subjected to plasma discharge treatment using a gas containing carbon and fluorine, and organic molecules are formed on the upper surface and side surfaces of the conductive layer. A method for manufacturing semiconductor devices that involves forming a film and applying a protective film on top of it.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17597188A JPH0226029A (en) | 1988-07-14 | 1988-07-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17597188A JPH0226029A (en) | 1988-07-14 | 1988-07-14 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0226029A true JPH0226029A (en) | 1990-01-29 |
Family
ID=16005449
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17597188A Pending JPH0226029A (en) | 1988-07-14 | 1988-07-14 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0226029A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5863834A (en) * | 1996-03-06 | 1999-01-26 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
-
1988
- 1988-07-14 JP JP17597188A patent/JPH0226029A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5863834A (en) * | 1996-03-06 | 1999-01-26 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
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