JPH02257719A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To eliminate waste time and to utilize the conversion speed of each A/D converter by providing an exclusive sample-hold circuit in a 2nd A/D converter in a serial-parallel A/D converter. CONSTITUTION:An exclusive sample-hold circuit 5 is provided in an input analog voltage input section to a 2nd A/D converter 7 in the serial-parallel A/D converter (A/D converter) and the sample-hold circuit 5 samples a voltage with a high level similarly to the case with the sample-hold circuit 1 and the sampled voltage is kept during the low level. Before the output digital data is produced, the 1st A/D converter 2 applies the succeeding A/D conversion and the time of the A/D conversion of the 2nd A/D converter 7 is quickened. Thus, the entire A/D conversion speed is improved without increasing the conversion speed of the 1st and 2nd A/D converters 2, 7.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a series-parallel type analog-to-digital converter (hereinafter referred to as r
(referred to as AD converter J).

[Conventional technology]

Figure 8 is a block diagram of a conventional serial-parallel AD converter, Figure 9
The figure is a timing chart.

In FIG. 8, 1 is a sample and hold circuit that samples and holds an input analog voltage; 2 is a first AD converter that roughly converts the analog voltage sampled and held in circuit 1 into analog-to-digital conversion (hereinafter referred to as rAD conversion);
3 is a latch circuit that latches the 11 power of AD converter 2,
4 is a digital-to-analog converter (hereinafter referred to as "rDA converter") that returns the conversion result of the first AD converter 2 to an analog voltage; 6 is a DA converter 4 that converts the voltage held in the sample and hold circuit 5; 7 is a second AD converter that finely AD converts the output of the calculation circuit 6; 8 is a latch circuit that latches the output of the AD converter 7;
9 is the latched output of the first AD converter 2 and the second A
a register 10 that combines the latched outputs of the D converter 7 and generates high-precision (multi-bit) output digital data;
A D fIjl! This is a synchronous clock generation circuit for operating the entire W.

The sample and hold circuit 1 is configured to carry out high level sampling and hold the sampled voltage during the low level.
．． The second AD converter 7 and its latch circuits 3 and 8 are configured to operate on the rising edge of a pulse from the synchronous clock generation circuit IO.

With the above configuration, the first AD converter operates at the timing shown in FIG. 9 to roughly AD convert the 5 input analog voltages, and the conversion result is digital-to-analog converted (hereinafter referred to as rDAD conversion) by the DA converter 4. Then, the arithmetic circuit 6 performs an operation to subtract the conversion result from the output of the sample and hold circuit 1,
The output of the arithmetic circuit 6 is converted into fine <AD by the second AD conversion PJ7.
Convert. Then, the conversion result of the first AD converter 2 and the conversion result of the second ADfD device 7 are combined in a register 9 to obtain output digital data.

[Problem to be solved by the invention]

However, in the conventional example, the first AD converter 2
After the AD converter completes its AD conversion operation and encodes and latches the upper bits, it cannot immediately start the next AD conversion operation, so the conversion speed of each AD converter cannot be fully utilized.

That is, until the DA conversion operation of the DA converter 4, the AD conversion operation of the second AD converter 7, and the encoding and latching of the lower bits are completed, the analog voltage held in the sample and hold circuit l is the same as the previous one. Since the value at the time of AD conversion remains the same, the AD conversion operation of the first AD converter 2 is meaningless. Further, the analog voltage cannot be sampled again until the AD conversion operation of the second AD converter 7 is completed. This corresponds to each AD converter 2, 7 performing a conversion operation at a rate of about % of the conversion rate capable of i+. That is, while the one AD converter is performing the conversion operation, the other AD converter is not performing the conversion operation.

The object of the present invention is to eliminate this waste and obtain a series/parallel type AD converter that can utilize the conversion speed of each AD converter.

(Means for Solving the Problems) In order to achieve the above object, in the present invention, a dedicated sample and hold circuit is provided at the input section of the input analog voltage to the second AD converter. The converter is configured as shown in (1) and (2) below.

(1) The first analog-to-digital converter roughly converts the input analog voltage into a digital-to-analog converter, and the second analog-to-digital converter finely converts the difference between the analog conversion result and the input analog voltage. An analog-to-digital converter that performs analog-to-digital conversion and generates output digital data from the conversion result of the first analog-to-digital converter and the conversion result of the second analog-to-digital converter, the converter converting the data to the second analog-to-digital converter. An analog-to-digital converter with a dedicated sample-and-hold circuit at the input analog voltage input section.

(2) In (1) above, the input analog voltage is directly supplied to the sample hold circuit dedicated to the second analog-to-digital converter, and the conversion result of the first analog-to-digital converter is converted to the digital-to-digital converter. An analog-to-digital converter in which a level shifter is connected to the output side of the digital-to-analog converter for conversion, which lowers the output level by 58% of that of the first analog-to-digital converter.

(Function) With the configurations (1) and (2) above, before generating output digital data, the first ADfD device performs the next AD conversion operation, and accordingly, the second AD converter performs the AD conversion operation. The operation time is also faster.

According to the configuration (2) above, further, output digital data including a change in the input analog voltage during conversion by the first AD converter is output.

(Example) The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram of an AD converter according to a first embodiment of the present invention, and FIG. 2 is a timing chart of the same embodiment.

In this embodiment, as shown in FIG.
The present invention differs from the conventional example shown in FIG. 8 in that a dedicated sample-and-hold circuit 5 is provided at the input section of the input analog voltage. Similar to the sample and hold circuit 1, this sample and hold circuit 5 also samples at a high level, and samples at a low level.
It is configured to hold the sampled voltage during the OW level.

The other configurations on the block diagram are the same as those of the conventional example, and the description thereof will be omitted here.

Next, the configuration and operation of this embodiment will be explained with reference to FIG.

The sample hold circuit 1 operates at time t. -th between tl!
The input analog voltage is sampled with the positive pulse of S/H, and the voltage is held between times t and t5. Time t2
Then, the held voltage is AD converted by the first AD converter 2.
The converted digital data is latched by latch 3 at time t3. In addition, in parallel with these operations, a positive pulse is supplied from the latch (t3) of the first AD converter for one clock period (up to 14) to supply a positive pulse to the second sample and hold circuit 5. The first sample-and-hold circuit 1 can perform a sample-and-hold operation for the next analog data. 1st AD
When the digital data latch of the converter 2 and the sample and hold operation of the second sample and hold circuit 5 are completed, the first sample and hold circuit 1 and the first AD converter 2
DA conversion P! ! 4 and the second AD converter 7, it is possible to take in the next data and move on to AD conversion (however, the output data of the first AD converter P!!2 is cannot be latched until the read is completed).

Next, since the analog voltage corresponding to the conversion result of the first AD converter 2 is outputted from the DA converter 4 almost simultaneously (t4) with the completion of the sampling operation of the second sample and hold circuit 5, the next At timing t6, the second AD change ti
AD conversion of the lower bits is performed by the device 7. Note that the delay time of the analog arithmetic circuit 6 and the conversion time (settling time) of the DA converter 4 are totaled from t4 to t6.
Configure it so that it fits within the time. The conversion result of the second AD converter 7 is latched into the latch 8 at time 0, and all the data combined with the upper bits are read out from the output register 9 at time t7.

Next, the operation of the first sample and hold circuit 1 and the first AD converter 2 during the period (t4 to t17) during which processing around the second AD converter 7 is being performed will be described.

Time t5-1. Now, the first sample and hold circuit 1 is performing the following sampling operation. Next, at time t7, the first AD conversion PJ2 conversion operation is performed.

The operations thereafter are the same as those after time t3.

Note that in the second sample-and-hold circuit 5, the sample-to-hold offset is
p4 L S B (least 51gn1fica
nt bit: Of course, it is necessary to configure the least significant bit L or less.

Next, an AD converter according to a second embodiment of the present invention will be explained.

FIG. 3 is a block diagram of this embodiment, and FIG. 4 is a timing chart of this embodiment.

In this embodiment, only the parts different from the first embodiment will be explained. The configuration is that a sample and hold circuit 11 is added to the output side of the DA converter W4, and the latch of the first AD converter 2 is a two-stage configuration (however, the second stage is only used for reading digital data). The difference is that it is .

First, the reason for providing two latch circuits 3 and 12 (sample and hold circuits are considered to be analog latches) will be explained. 1st
In the embodiment, the output latch 3 of the first AD converter 2
Since it is necessary to hold the data of the song in the latch 3 until the data of the first song is read out to the read register 9,
The next AD conversion and latch start timing of the AD converter 2 is limited. That is, the upper limit of the sampling rate is limited by something other than the speed of the AD converter. The purpose is to improve this and utilize the conversion speeds of the first AD converter 2, DA converter 4, and second AD converter 7 to the upper limit.

The operation of the second embodiment will be explained with reference to FIG. The first sample-and-hold circuit 1 samples and holds the voltage from time t0 to t1, then AD converts the sample-and-hold voltage in the first AD converter 2 at time t2, and latches it in the first latch 3 at time t3. do. Next, the DA converter 4
Conversion is performed (t4), and the conversion result is sampled and held in the third sample and hold circuit 11 (14~ts)
. Similar to the first embodiment, the input analog voltage π pressure is further sampled and held by the second sample and hold circuit 5 in parallel during this period (in this example, from t2 to t3). These two voltages (the output voltage of the DA converter 4 held in the third sample and hold circuit 11, and the input held in the first sample and hold circuit l and further held in the second sample and hold circuit 5) The second AD converter 7 performs AD conversion on the difference between the two voltages (voltages) (t6). This conversion result is latched in latch 8 (t7), combined with the upper bit in register 9, and its value is read out (ta).

In this way, the result of AD conversion by the first AD converter 2 is latched by the first latch 3, and then relatched by the second latch 12 as digital data (ts), and as analog data, the result is latched by the first latch 3. The input analog voltage is stored (ts) in the sample hold circuit 11 of No. 3.
Since the data is stored in the first sample and hold circuit 5 (t3), after time t6, the first sample and hold circuit 1
The AD converter 2 and the first latch circuit 3 can be operated independently of other circuits.

In the first embodiment, since the second latch 12 was not provided, new data could not be taken into the first latch 3 until after the entire data had been read. The first AD converter 2 until the data is read out.
Since the AD-converted data is stored in the second latch 12, the entire data can be read out regardless of the timing (after the AD conversion and data latching of the second AD converter 7). The AD-converted data of the first AD converter 2 can be taken into the first latch 3.

In this embodiment, new input analog data is sampled at times t4 to t6, AD converted at time fill ta, and digital data (upper bits) is stored in the first latch 3 at time t.

As a result, the time interval for the first sample and hold, which was 5 clocks in the first embodiment, can be reduced to 4 clocks in the second embodiment.

Furthermore, if the configuration is such that the sample-to-hold offsets of the second sample-hold circuit 5 and the third sample-hold circuit 11 are the same, the sample-to-hold offset of the sample-hold circuit will be lower than that of the first embodiment. The impact of this can be reduced.

Next, a DA converter according to a third embodiment of the present invention will be described.

FIG. 5 is a block diagram of this example, and FIG. 6 is a timing chart of this example. In this embodiment as well, only the parts that are different from the first embodiment will be explained. The composition is 7
The sample-and-hold circuit 5 of JJ2 does not latch the voltage latched by the first sample-and-hold circuit 1, but directly latches the input analog voltage, and the first AD LS of converter 2
The difference is that a level shifter 13 that lowers the analog voltage by the amount indicated by B is connected, and the output of the level shifter 13 is input to the arithmetic circuit 6.

Next, the operation of this embodiment will be explained with reference to FIG. First, time t. ~t, the first sample and hold circuit 1
Sample and hold the input analog voltage at level A)
Then, at time 61 t 2, the first AD converter 2 performs AD conversion. At time t3, the data is latched by the latch circuit 3, and the data is DA-converted by the A converter 4 (t4).

The upper bit data latched by the latch circuit 3 is held in the latch 3 until it is read out as the entire data after the lower bit data is AD converted.

The input analog voltage that is changing during this period is sampled and held by the second sample and hold circuit 5 during the period t3 to t4 (level B). From this sampled and held voltage, 4L of AD converter 2 is output from DA converter 4.
Output lowered by SB (shifted DA output in Figure 6)
The voltage from which is subtracted is AD-converted by the second AD converter 7 (
t5). The result of this AD conversion is latched by the latch 8, combined with the upper bit data by the register 9, and read out as the entire data (t7).

The feature of this embodiment is that the change in the input analog voltage until the second AD converter 7 AD converts the lower bits is (
Although not completely), it is possible to extract it. In FIG. 6, the hatched range is the dynamic range (convertible range) of the AD converter 7 for lower bits, so
from the first sample hold to the second sample hold as described here.
If the amount of change in the input analog voltage up to the sample hold exceeds the dynamic range of the second AD converter 7, only the value with all lower bits set can be taken; , the change in the input analog voltage up to the second sample-and-hold time can be detected and converted.

Note that the AD conversion ja2 converts the LSB of the input analog voltage (level A) held in the sample hold circuit 1.
Since voltages below cannot be AD converted, the output of the DA converter 4 is lower than level A by the voltage that cannot be converted. Therefore, the lowest level of the hatched portion is lower than level A by 1/2 LSB to 11/2 LSB.

Moreover, if the input analog voltage is only directly supplied to the second sample and hold circuit 5, the 5 input analog voltage will not be the same as the first A.
When the voltage decreases during operation of the D converter 2, the input to the second AD converter 7 becomes negative, and the converter 7 often becomes unable to perform conversion. Therefore, lower the reference level using the level shifter 13,
Even if the input analog voltage drops as described above, it is possible to convert as much as possible.

For a deeper understanding, let's compare FIG. 6 with FIG. 7, which is a timing chart of the first embodiment in which the same wave JFg as the analog voltage in FIG. 6 is added.

In FIG. 7, the output of the second sample and hold circuit 5 only continues to hold the output of the first sample and hold circuit 1, so the final result of AD conversion is held in the first sample and hold circuit 1. In contrast, in FIG. 6, the value is a value that includes the change in analog voltage after being sampled and held by the first sample and hold circuit l. Furthermore, since the sample and hold circuits are not cascaded in two stages as in the first embodiment, the influence of sag during hold in the sample and hold circuit is also reduced.

〔Effect of the invention〕

As described below, according to the present invention, in a series/parallel type AD converter, a dedicated sample and hold circuit is provided in the second AD converter to reduce wasted time. The overall AD conversion speed can be increased without increasing the conversion speed of the second AD converter.

In the invention of claim 2, the input analog voltage is further directly supplied to a sample hold circuit dedicated to the second AD converter, and a level shifter is connected after the DA converter, so that the conversion of the first AD converter is performed. Changes in input analog voltage during operation can also be extracted and AD converted.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a timing chart of the same embodiment, FIG. 3 is a block diagram of a second embodiment of the present invention, and FIG. 4 is a timing chart of the same embodiment. Chart 5 Figure 5 is a block diagram of the third embodiment of the present invention, and Figure 6 is a block diagram of the third embodiment of the present invention.
7 is an explanatory diagram of the operation of the first embodiment, FIG. 8 is a block diagram of the conventional example, and FIG. 9 is a timing chart of the conventional example. 1.----Sample hold circuit 2...First ADf: Converter 4----OA converter 5----Sample hold dedicated to the second AD converter Circuit 7...Second AD converter 13---Level shifter,/

Claims (2)

[Claims] (1) Roughly analog-to-digital converting the input analog voltage with a first analog-to-digital converter, converting the conversion result into digital-to-analog, and converting the difference between the analog conversion result and the input analog voltage into the second analog-to-digital converter. An analog-to-digital converter that performs fine analog-to-digital conversion to generate output digital data from the conversion result of the first analog-to-digital converter and the conversion result of the second analog-to-digital converter, the second analog-to-digital converter An analog-to-digital converter characterized by having a dedicated sample-and-hold circuit provided at the input section for inputting analog voltage to the converter. (2) A digital-to-analog converter configured to directly supply the input analog voltage to a sample hold circuit dedicated to the second analog-to-digital converter, and converting the conversion result of the first analog-to-digital converter into digital-to-analog. 2. The analog-to-digital converter according to claim 1, further comprising a level shifter connected to the output side of the converter for lowering the output level by 1/2 LSB of the first analog-to-digital converter.