JPH02256279A - Semiconductor device having avalanche breakdown type junction - Google Patents

Abstract

PURPOSE:To obtain an avalanche diode which is hard to receive the effect of ions in an insulating film by providing a constitution wherein an N<+> type region has impurity concentration that is decreased from one main surface side of a semiconductor substrate toward the side of an N-type region, and the side end surface of the region is surrounded with a P<+> region. CONSTITUTION:A semiconductor substrate 11 is provided with the following regions: an N-type region (first semiconductor region) 15; an N<++> type region 16 for ohmic connection which is formed at the lower surface of the region 15; a planar ring-shaped P<+> type region (second semiconductor region) 17 whose upper surface is exposed to one main surface of the semiconductor substrate 11 and which is surrounded with the N-type region at the neighboring part; and an N<+> type region (third semiconductor region) 18 whose upper surface is exposed to one main surface of the semiconductor substrate 1 and which is surrounded with the P<+> type region 17. The impurity concentration of the N<+> type region 18 is higher than that of the N-type region 15. The impurity concentration at the surface side is higher than that in the inside. Even if the depletion layer at the surface of the N-type region 15 is changed by the ions in an insulating film 12, the fluctuation of a breakdown voltage can be made less in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having an avalanche breakdown type junction.

[Prior art and problems to be solved by the invention] A constant voltage diode that utilizes the avalanche breakdown phenomenon is generally called an avalanche diode, and is widely used in various electronic circuits such as reference voltage circuits and protection circuits. has been done.

By the way, in order to set the breakdown voltage to a predetermined value in an avalanche diode and a Zener diode, it is desirable to cause the breakdown to occur inside the semiconductor substrate as much as possible, as disclosed in Japanese Patent Laid-Open No. 5
7-71186, as shown in FIG. 13, in order to cause breakdown inside the semiconductor substrate, N
A P+ shaped area 2 is formed inside the shadow area 1, and a P+ shaped area 2 is formed inside the shadow area 1.
An N+ type area 3 was formed so as to be embedded under the type area 2, and a cathode electrode 5 was connected to the N+ type area 3 via an N++ type area 4, and an anode electrode 6 was connected to the P+ type area 2. A Zener diode is disclosed. Forming an avalanche diode in the same shape as the Zener diode shown in FIG. 13 has the advantage of allowing breakdown to occur in an unaffected region of the surface of the semiconductor substrate.
The disadvantage is that it is difficult to reduce the breakdown voltage (change in breakdown voltage due to temperature change).

The temperature dependence of the breakdown voltage can be improved by forming a narrow portion in the depletion layer generated based on the PN junction and causing breakdown in this narrow portion. For this purpose, as shown in FIG. 14, an avalanche diode in which an N+ type region 3 is arranged so as to surround the side surface of a P+ type region 2 has already been manufactured. Note that in FIG. 14, parts common to those in FIG. 13 are given the same reference numerals. According to the avalanche diode shown in FIG. 14, since the anode ring i6 extends above the N+ type region 3 via the insulating film 7, a depletion layer is generated due to the electric field effect in addition to all six layers formed by the PN junction. , a depletion layer 8 as shown by the broken line is obtained.

Further, the spread of the depletion layer 8 is related to the impurity concentration, and becomes wider in the N shadow region 1 with a lower impurity concentration and narrower in the N+ type region 3 with a higher impurity concentration. Also, N+ shape area 3
Since the impurity concentration is high on the surface side and low on the inside side, the depletion layer based on the PN junction of the N+ type region 3P+ type region 2 becomes narrow on the surface side. As a result, as shown in principle in FIG. 14, the depletion layer based on the PN junction between the P1 type region 2 and the N+ type region 3 becomes narrower slightly below the surface of the semiconductor substrate 1. A breakdown occurs. Note that since the depth of the N+ type region 3 is shallower than that of the P+ type region 2, the depletion layer based on the PN junction between the lower part of the P+ type region 2 (Pl end face and the N shadow region 1) is smaller than the N" shadow region 3. The depletion layer is wider than the depletion layer based on the PN junction in the P+ type region 2, and a narrow portion of the depletion layer in the N+ type region 3 is reliably created.By adopting the structure shown in FIG. It becomes possible to cause breakdown in a narrow depletion layer of N, and the temperature dependence of the breakdown voltage becomes better. The depletion layer generated on the surface of the N shadow region 1 based on the voltage changes under the influence of ions contained in the insulating film 7 and the protective resin (not shown) coated thereon, and the depletion layer changes to a predetermined breakdown voltage. was difficult to obtain.

In particular, when a test is performed in which a reverse voltage is applied to an avalanche diode in a high temperature state, the breakdown voltage varies significantly.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an avalanche diode that is hardly affected by ions in an insulating film.

[Means for Solving the Problems] The present invention for achieving the above object includes a first semiconductor region having a first conductivity type of N type or P type, and a first semiconductor region having a first conductivity type opposite to the first conductivity type. a second conductivity type of the conductivity type;
a second semiconductor region adjacent to the semiconductor region; a third semiconductor region having the first conductivity type and adjacent to the first semiconductor region; a first electrically connected directly or via another semiconductor region;
and a second main electrode electrically connected to the first semiconductor region directly or through another semiconductor region, the second semiconductor region and the third semiconductor region are respectively exposed on the surface of the semiconductor substrate, and the third
The semiconductor region is adjacent to and surrounded by the second semiconductor region, and the surface of the semiconductor body includes an upper part of the boundary between the second semiconductor region and the third semiconductor region, An insulating film is formed extending over substantially the entire upper surface of the exposed surface of the semiconductor region, and the first main electrode extends over substantially the entire upper surface of the third semiconductor region via the insulating film. , the third semiconductor region in a portion adjacent to the second semiconductor region
The present invention relates to a semiconductor device having an avalanche breakdown junction, wherein the impurity concentration of the semiconductor region is higher than the impurity concentration of the first semiconductor region in a portion adjacent to the second semiconductor region.

Note that the third semiconductor region has a first portion shallower than the second semiconductor region and a second portion deeper than this with respect to the surface of the semiconductor substrate, and the first portion is shallower than the second semiconductor region. It is desirable that the semiconductor region is located adjacent to the semiconductor region of
Further, it is desirable that the second portion has a higher impurity concentration than the first portion.

[Function] Breakdown in the avalanche diode of the present invention occurs between the second semiconductor region and the third semiconductor region, similar to the conventional one shown in FIG. Since the width of the depletion layer based on the PN junction between the second semiconductor region and the third semiconductor region is narrow, the temperature dependence of the breakdown voltage is relatively small.

Since the side end face of the third semiconductor region is surrounded by the second semiconductor region, the depletion layer generated by the field effect on the surface portion of the third semiconductor region is the same as the depletion layer on the surface portion of the first semiconductor region. In other words, the depletion layer is not influenced by the field effect effect based on the first semiconductor region, the insulating film, and the second electrode, or the width of the depletion layer generated due to the relationship between the first semiconductor region and the insulating film is insulating. 2. Even if it changes due to the ions of the membrane or the ions of the protective resin provided on it. The spread state of the depletion layer between the second semiconductor region and the third semiconductor region does not change.

According to the second aspect, the resistance of the path of the reverse current flowing due to breakdown can be reduced.

[First Embodiment] Hereinafter, an avalanche diode according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 3.

As shown in FIG. 1, the avalanche diode of this embodiment includes a semiconductor substrate 11 made of a silicon semiconductor, an insulating film 12 made of a silicon oxide film formed on one main surface of the semiconductor substrate 11, and Semiconductor substrate 11
An anode electrode (first main electrode) 13 made of AI (aluminum) formed on one main surface side of the semiconductor substrate 11, and a cathode ′rjh made of Ni (nickel) formed on the other main surface side of the semiconductor substrate 11. % (second main electrode) 14. The semiconductor substrate 11 has an N shadow region (first semiconductor region) 15 which is a starting base material, an N++ type region 16 for ohmic connection formed on the lower surface thereof, and the upper surface thereof is exposed on one main surface of the semiconductor substrate 11. A planar annular P" shadow region (second semiconductor region) 17 adjacent to and surrounded by the N shadow region 15
and an N+ type region (third semiconductor region) 18 surrounded by the P+ type region 17 with its upper surface exposed on one main surface of the semiconductor substrate 11. In addition, N shadow area 15 and N++
The shaped region 16 can also be collectively referred to as a first semiconductor region. The side surface of the N+ shape region 18 is adjacent to the P+ shape region 17, and the lower surface is adjacent to the upper surface of the N shadow region 15. As a result, as shown in FIG. 2, the N+ shape region 18 is P+ in plan view. The shape region 17 is formed in an island shape. N+ shape area 1
8 Impurity ion implantation (pre-deposition) and thermal diffusion (
The impurity concentration is higher than that of the N shadow region 15, and the impurity concentration on the surface side is higher than on the inside side. The depth of the N+ type area 18 is shallower than the P+ type area 17. For convenience of illustration, there is not much difference in depth, but the depth of the N+ type area 18 is the depth of the P+ type area 17. Preferably 172
Below, it is more desirably set to 173 or less. In addition, N++
type region 16 and P+ type region 17 are formed by normal impurity diffusion. Insulation Jli of the upper part of the P+ type area 17
An opening 12a is formed in the anode electrode 12.
3 is adjacent to the P+ cross-shaped region 17 through the opening 12a. N
+An insulating film 12 is formed over the entire upper surface of the 18-shaped region 18.
is formed. Insulation v412 is P + 17N
It extends beyond the boundary of the + ten-shaped region 18 to the upper surface of the P+ ten-shaped region 17 . Further, the anode electrode 13 includes the upper part of the N+ 10-shaped region 18 and the outside of the P+ 10-shaped region 17! It extends to I.

Note that the portion of the anode electrode 13 extending outward from the P+ cross-shaped region 17 acts as a well-known field plate to increase the withstand voltage on the outer peripheral side of the P+ cross-shaped region 17.

When a reverse voltage is applied between the anode electrode 13 and the cathode electrode 14 of the avalanche diode shown in FIG.
A first depletion layer 20 expands from the first PN junction 19 formed by the N shadow region 15 as shown by the dotted line, and a second P depletion layer 20 spreads out from the first PN junction 19 formed by the P+ decagonal region 17N" shadow region 18.
A second depletion layer 22 expands from the N junction 21. Also, N+
An anode voltage is provided on the surface side of the ten-shaped region 18! The third depletion layer 23 expands due to the field effect of f113. In addition, the first
The second and third depletion layers 20, 22, and 23 extend continuously from each other and are therefore not strictly distinguishable. Here, since the impurity concentration is higher than that of the N+ decagonal region 18N shadow region 15, the second depletion layer 22 is formed narrower than the first depletion layer 20.

In addition, since the N+ decadal region 18 has an impurity O1 concentration that decreases from one main surface side of the semiconductor substrate 11 toward the N shadow region 15 side, the second depletion layer 22 is a semiconductor substrate, as shown in FIG. The width becomes narrower on one main surface side of the base body 11. However, N
Since the third depletion layer 23 is present in the surface portion of the + 18-shaped region 18, the narrowest portion is located slightly below the surface of the N+ 18-shaped region 18. When the reverse voltage reaches the breakdown voltage, a critical electric field strength E is applied to the narrow portion of the second depletion layer 22.
A portion exceeding Crit (electric field concentration point) occurs, and breakdown occurs at this portion. In this embodiment, when a reverse voltage is applied, the N+ decagonal region 18 second and third depletion layers 22
．． The diameter of the N'' shadow region 18 is determined so that it does not become full of N++
It flows into a path consisting of the N+ shaped region 16, the N shadow region 15, the N+ 18-shaped region 18, the narrow portion of the second depletion layer 22, the P+ 10-shaped region 17, and the anode electrode 13.

The avalanche diode of this embodiment has the following effects.

(1) Since the side end face of the N+ ten-shaped region 18 is surrounded by the P ten-shaped region 17, the N+ ten-shaped region 18P+ ten-shaped region 1
The width of the second depletion layer 22 generated based on the PN junction 21 of 7 is the width of the N shadow region 15, the insulation WA 12, and the anode electrode 13.
Therefore, it is not affected by the depletion layer caused by
The ions in the insulation [12 and the protective resin that coats it]
Even if the depletion layer on the surface of the N shadow region 15 changes due to ions in the
The width of the depletion layer 22 based on the PN junction 21 of No. 7 does not change,
There is little variation in breakdown voltage.

(2) In the avalanche diode of this embodiment, the depletion layer that crosses the current path of the reverse current passing through the electric field concentration point, that is, the depletion layer in the region where avalanche breakdown occurs, is formed to be relatively narrow.

Therefore, an avalanche diode whose breakdown voltage is less dependent on temperature can be realized.

(3) The electric field concentration point is located on the semiconductor substrate 1 as shown in Figure 3.
Since it is formed inside the surface of 1 (lower IJII), the creep phenomenon (an unstable phenomenon in which the breakdown voltage fluctuates in a short time when a reverse voltage is applied) does not occur. The boundaries of each region 15, 17, and 18 are shown by 24, and the equipotential curve connecting the equal electric field parts is shown by the solid line 24, and the equipotential curve located inside has a stronger electric field.

(4) Insulating film 12 formed on the top surface of N+ 10-shaped region 18
is covered with the anode electrode 13, so the anode voltage f
! 13 acts as a protective film together with the insulating film 12, achieving high reliability. In this embodiment, the insulating film 12 made of only a silicon oxide film with good productivity has the same reliability as a two-layer insulating film made of a silicon oxide film, a silicon nitride film, a phosphosilicate glass film, or the like.

[Second Embodiment] Next, an avalanche diode according to a second embodiment of the present invention will be described with reference to FIGS. 4 and 5. however,
Components denoted by numerals 12 to 23 in FIGS. 4 and 5 are substantially the same as those denoted by the same numerals in FIGS. 1 and 2, and therefore their explanation will be omitted. The semiconductor substrate 11a in FIGS. 4 and 5 includes an N shadow region 15 and an N++ type region 16.
, P+ shape region 17N+ shape region 18, and a new N+
It has a + type region (fourth semiconductor region) 25. N■
The side surface of the shape region 25 is adjacent to the N+ shape region 18, and the bottom surface is N
It is formed vertically across the N shadow region 15 so as to be adjacent to the +-shaped area 16, and as shown in FIG. 5, it is formed in the shape of an island within the N+-shaped area 18 when viewed in plan. In other words, the N++ type area 25 is an area that rises up from the N++ type area 16 in a cylindrical shape and is surrounded on the sides by the N shadow area 15 and the N+ type area 18. N++ type area 25 is P+ type area 1
7. The impurity concentration of the N++ type region 25, which is formed by diffusion in the N shadow region 15 before forming the N+ type region 18, is higher than the impurity concentration of the N shadow region 15 and the N+ type region 18 on the surface of the semiconductor substrate 11a. The exposed surface of the N++ type region 25 is covered with an insulating film 12 made of silicon oxide like the N+ type region 18. Note that, like the N+ type region 18, the N shadow region 25 is a region with a high N type impurity concentration, so it is considered to be a part of the third semiconductor region, and the N
+ shaped region 18 first portion of third semiconductor region, N++
Shape region 25 can be considered a second part.

When a reverse voltage is applied between the anode electrode 13 and the cathode electrode 14 of the avalanche diode shown in FIG. The first depletion layer 20 expands from the first PN junction 19 as shown by the dotted line, and the second depletion layer 2 spreads from the second PN junction 21 formed by the P+ type region 17N+ type region 18.
2 expands. Furthermore, a third depletion layer 23 is expanded on the surface side of the N+ type region 18 due to the electric field effect of the anode t[i13. On the surface of the N++ type region 25, an Nll region 25 is formed.
Since the impurity concentration is sufficiently high, virtually no depletion layer is generated. Note that when the impurity concentration of the N++ type region 25 approaches the impurity concentration of the N+ type region 18, a depletion layer slightly expands on the surface of the N++ type region 25.

Also in this embodiment, the narrowest portion of the depletion layers 20, 22, 23 occurs in the N+ type region 18 slightly below the upper surface of the semiconductor substrate 11a. Therefore, when a reverse voltage is applied between the anode 13 and the cathode 14, this narrow portion serves as an electric field concentration point, and breakdown occurs at this narrow portion.

The narrow portion of the second depletion layer 22 has a high impurity concentration of N+
Adjacent to this N+ type region 18 is an N++ type region 25 with an even higher impurity concentration.
Since the +-type region 25 is continuous with the N++-type region 16, the reverse current IR flows from the cathode 14, the N++-type region 16, the N++-type region 25, and the N+
It flows through the path of the shape region kA18, the P+ shape region 17 and the anode 13.

The avalanche diode of the second embodiment has the same advantages as the first embodiment, and also has the advantage that the resistance value of the path for the reverse current IR can be reduced. That is, since this avalanche diode includes an N++ type region 25 with a low resistance value in the path of the reverse current ■□, the reverse current ■1
The resistance value of the current path becomes smaller. Therefore, the operating resistance in the avalanche breakdown region is reduced.

[Third Embodiment] An overvoltage operation thyristor incorporating an avalanche diode according to a third embodiment of the present invention will be described with reference to FIGS. 6 and 7. In FIG. 6, P+ shape region 3
A thyristor 35 is formed in the vertical direction by the 1N shadow region 32, the P shadow region 33, and the N+ type region 34, and an avalanche diode 37 is formed by the N shadow region 32, the P shadow region 33, and the N+ type array region 36. ing. Thyristor 3
5 is an anode electrode 38, a cathode electrode 39, and a gate electrode i.
4o, and the avalanche diode 37 uses the gate @i4o of the thyristor 35 as an anode electrode, and the anode electrode 38 as a cathode electrode.To show the correspondence between the present invention and this embodiment, the first semiconductor region is The N shadow region 32 is the second semiconductor region, the P shadow region 33 is the second semiconductor region, the N+ type region 36 is the third semiconductor region, the anode electrode 38 is the first main electrode, and the gate electrode 40 is the second main electrode. To show the correspondence between FIG. 1 and FIG. 6, N shadow area 32 is N shadow area 15, P shadow area 33 is P + shape area 17N + shape area 3.
6N+ shape areas 18 correspond to each other. Note that it is surrounded in an annular manner by the N+ shaped area 36P and the shadow area 33.

Mana N+ type area 41 functions as a channel stopper.

The overvoltage operation thyristor shown in Fig. 6 is as shown in Fig. 7.
This is equivalent to an avalanche diode 37 being electrically connected in parallel between the anode of the thyristor 35 and the pole 38 and the gate voltage @40. A voltage is applied between the anode electrode 38 and the gate electrode 40 so that the potential toward the anode electrode 38 is high, and when this voltage exceeds the breakdown voltage of the avalanche diode 37, a reverse current flows through the avalanche diode and the thyristor 35 is activated. Conduct.

The overvoltage type thyristor shown in FIG. 6 has a small temperature dependence of the breakdown voltage of the avalanche diode 37, so the overvoltage type thyristor has a small temperature dependence of the turn-on voltage.

[Modifications] The present invention is not limited to the above-described embodiments, and, for example, the following modifications are possible.

(1) The impurity concentration of the N+ type region 18 functioning as the third semiconductor region is set according to the required avalanche voltage. N shadow region 15 or 3 as a semiconductor region
It is preferable that the impurity concentration is 5 times or more than the impurity concentration of No. 2, preferably 10@ or more.

(2) In the thyristor shown in FIG. 6, an N+, shadow region or P+ type region may be provided in the P shadow region 33, and the gate electrode 40 may be connected thereto.

(3) The avalanche diode shown in FIG. 4 can be applied to the thyristor shown in FIG. 6.

(4) As shown in Figure 8, N++ type region 1 in Figure 1
The present invention can also be applied to a semiconductor element having a three-layer structure made of PNP in which the P+ type region 26 is replaced with the P+ type region 26. Note that in FIG. 8, substantially the same parts as in FIG. 1 are given the same reference numerals.

<5) In the embodiment, the N+ type region 18 as the third semiconductor region, the P1 type region 17 as the second semiconductor region
Although only one N+ type region 18 is formed in the shape of an island, as shown in FIG. 9, a plurality of N+ type regions 18 may be formed in the shape of islands.

(6) Instead of the N++ type region 25 in FIG. 4, one or both of the N++ type regions 25a and 25b shown in FIG. 10 may be provided.In other words, at least a part of the path of the reverse current I3 By providing N++ type regions 25a and 25b with high impurity concentration (low resistivity), the nonlinearity of the reverse characteristic of the avalanche diode can be increased as in FIG. 4. In addition, N++ in FIG.
The shaped region 25b can be obtained by providing an N++ type buried layer in the N++ type region 16 and diffusing impurities in this buried layer into the N shadow region 15. In FIG. 10, parts common to those in FIG. 4 are given the same reference numerals.

(7) The impurity concentration of the N++ type region 25 in FIG.
Even if the shape regions 18 are made substantially the same, a certain effect can be obtained.

(8) In the case of the first embodiment, the anode electrode 13 is N+
Even if it does not extend over the entire surface above the shape area 18, a certain effect can be obtained. However, in order to effectively prevent breakdown voltage fluctuations and creep phenomena caused by ions, the anode voltage f! In the case of the second embodiment, in which it is desirable to extend the impurity 13 over the entire surface above the N+ type region, the impurity concentration of the N++ type region 25 is made sufficiently high to form a third depletion layer on the surface of the N++ type region 25. When the layer is not substantially expanded, the effects of the present invention can be obtained to a certain degree by extending the anode electrode 13 beyond the termination of the third depletion layer. Therefore, it is not necessary to extend the anode electrode 13 over the entire surface of the N++ type region 25. However, in order to reliably prevent breakdown voltage fluctuations and creep phenomena, it is necessary to extend the anode electrode 13 over almost the entire upper surface of the N+ type region 25. It is better to extend it.

Note that when the impurity concentration of the N++ type region 25 is slightly lowered so that the third depletion layer spreads over almost the entire surface thereof, the anode electrode 1 is formed over almost the entire upper surface of the N++ type region 25.
form 3.

(9) In the avalanche diode shown in Figure 1, N
+-type region 18N++-type region 18 may be extended downward until it is adjacent to N++-type region 16 in order to reduce the operating resistance. It is preferable that the lower surface of 18 is located above the lower surface of P+ type area 17. Therefore, as in the second embodiment, N+ type area 18
The design is such that its lower surface is located above the bottom surface of the P+ shape region 17, and the N+" shadow region 25 is spaced apart from the P+ shape region 17 and located below the bottom surface of the P+ shape region 17. However, it is also desirable as a structure for reducing operating resistance in that a desired avalanche voltage can be obtained.

(10) As shown in FIGS. 11 and 12, an N+ type area is formed in an annular shape, a P+ type area 17a surrounded by the N+ type area is provided, and this P+ type area 17a is connected to the anode electrode 13. You may.

[Effects of the Invention] As is clear from the above, according to the inventions of claims 1 and 2, the depletion layer generated based on the first semiconductor region with a low impurity concentration, the insulating film, and the second electrode has a breakdown voltage. Accordingly, it is possible to provide a semiconductor device having an avalanche junction that does not affect performance.

According to the second aspect, it is possible to provide a semiconductor device having an avalanche junction with low operating resistance.

[Brief explanation of drawings]

1 is a sectional view showing an avalanche diode according to a first embodiment of the present invention, corresponding to the line II in FIG. 2; FIG. 2 is a plan view showing the surface of the semiconductor substrate in FIG. 1; 3 is a diagram showing the electric field strength distribution at the boundary between the N shadow region and the P+ type region and the N+ type region of the avalanche diode of FIG. 1. FIG.
5 is a plan view showing the surface of the semiconductor substrate in FIG. 4; FIG. 6 is a sectional view showing the thyristor of the third embodiment; FIG. is an equivalent circuit diagram of the thyristor in FIG. 6, FIG. 8 is a cross-sectional view of a modified avalanche diode at a portion corresponding to FIG. 1, and FIG. 9 shows the surface of the semiconductor substrate of another modified avalanche diode. FIG. 10 is a cross-sectional view of another modification of the avalanche diode corresponding to FIG. 1, FIG. 11 is a cross-section of the modification of the avalanche diode, and FIG. 13 and 14 are cross-sectional views showing conventional avalanche diodes, respectively. 11... Semiconductor base, 12... Insulating film, 13...
Anode electrode, 14... Cathode electrode, 15...N
Shadow area, 16...N++ type area, 17...P+ type area 18...N1 type area.

Claims (1)

[Scope of Claims] [1] A first semiconductor region having a first conductivity type of N type or P type, and a second conductivity type having a conductivity type opposite to the first conductivity type. , a second semiconductor region adjacent to the first semiconductor region; a third semiconductor region having the first conductivity type and adjacent to the first semiconductor region; a first main electrode electrically connected to the semiconductor region directly or through another semiconductor region; and a first main electrode electrically connected to the first semiconductor region directly or through another semiconductor region. a second main electrode, the second semiconductor region and the third semiconductor region are each exposed on the surface of the semiconductor substrate, and the third semiconductor region is adjacent to the second semiconductor region. The surface of the semiconductor substrate includes a portion extending over substantially the entire upper surface of the exposed surface of the third semiconductor region, including above the boundary between the second semiconductor region and the third semiconductor region. An insulating film is formed therein, and the first main electrode extends over substantially the entire upper surface of the third semiconductor region via the insulating film, and extends in a portion adjacent to the second semiconductor region. The impurity concentration of the third semiconductor region is greater than the impurity concentration of the first semiconductor region in a portion adjacent to the second semiconductor region.
A semiconductor device having an avalanche breakdown junction characterized in that the impurity concentration is higher than that of a semiconductor region. [2] The third semiconductor region includes a first portion shallower than the depth of the second semiconductor region and a second portion deeper than the depth of the second semiconductor region with respect to the surface of the semiconductor substrate.
, the first part is arranged so as to be adjacent to the second semiconductor region, and the second part is arranged so as to be surrounded by the first part when viewed in a plan view. 2. The semiconductor device according to claim 1, wherein: