JPH02256029A - Active matrix substrate - Google Patents

Active matrix substrate

Info

Publication number
JPH02256029A
JPH02256029A JP1078861A JP7886189A JPH02256029A JP H02256029 A JPH02256029 A JP H02256029A JP 1078861 A JP1078861 A JP 1078861A JP 7886189 A JP7886189 A JP 7886189A JP H02256029 A JPH02256029 A JP H02256029A
Authority
JP
Japan
Prior art keywords
active matrix
matrix substrate
metal film
signal lines
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1078861A
Other languages
Japanese (ja)
Inventor
Hitoshi Noda
均 野田
Mamoru Takeda
守 竹田
Hiroshi Takahara
博司 高原
Ichiro Yamashita
一郎 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1078861A priority Critical patent/JPH02256029A/en
Publication of JPH02256029A publication Critical patent/JPH02256029A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To allow the connection of the active matrix substrate and driving circuit via a flexible substrate or the like and to simplify a packaging stage by forming an insulating film on the metallic film patterns connected with at least >=2 signal lines of the switching elements of the active matrix substrate. CONSTITUTION:The metallic film patterns 3 to short the signal lines are formed simultaneously with the formation of input terminals 2 of the signal lines on a glass substrate 10. The insulating film 4 is formed on the patterns 3 simultaneously with the formation of the switching elements. An auxiliary metallic film 5 is formed on the input terminals 2 in order to correct the steps generated by the insulating film 4. The patterns 3 are insulated by the film 4 in this way and, therefore, the contact of the patterns 3 and the flexible substrate is obviated even if the insulating treatment by sticking insulating tapes, etc., is not executed at the time of connecting the active matrix substrate and the driving circuit with the flexible substrate or the like. The packaging stage is thus simplified.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、液晶表示パネルに用いられるアクティブマト
リックス基板に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an active matrix substrate used in a liquid crystal display panel.

従来の技術 近年、産業機器の小型化にともない従来からの表示装置
に代わる薄型平面表示装置が要望されている0種々ある
平面表示装置の中で液晶を用いた表示装置は、消費電力
が少なく、フルカラー表示が容易である点などから注目
されている。特に、表示画素の一つ一つにスイッチング
素子を設けたアクティブマトリックス型液晶表示パネル
は表示画質が優れているため携帯用のテレビなどに応用
されている。
BACKGROUND OF THE INVENTION In recent years, with the miniaturization of industrial equipment, there has been a demand for thin flat display devices to replace conventional display devices.Among the various flat display devices, display devices using liquid crystals consume less power. It is attracting attention because it is easy to display in full color. In particular, active matrix liquid crystal display panels in which each display pixel is provided with a switching element have excellent display image quality and are therefore being applied to portable televisions and the like.

第3図は従来のアクティブマトリックス基板の構成を示
す等価回路図である。第3図において、51は薄膜トラ
ンジスタ、52は信号線をショート状態にするための金
属膜パターン、X1〜xII+は走査信号線、Y、〜Y
nは映像信号線である。
FIG. 3 is an equivalent circuit diagram showing the structure of a conventional active matrix substrate. In FIG. 3, 51 is a thin film transistor, 52 is a metal film pattern for shorting the signal line, X1 to xII+ are scanning signal lines, Y, to Y
n is a video signal line.

ところが、アクティブマトリックス基板では、基板の製
造行程中に基板に帯電する静電気によってスイッチング
素子や走査信号線と映像信号線の交差部分の絶縁膜が破
壊され、ショート状態になってしまうという問題点があ
った。この静電気による絶縁膜の破壊防止対策として、
従来では第3図に示すようにアクティブマトリックス基
板の全ての端子を金属膜パターン52でショートしてお
き、液晶パネルへの組立後この金属膜パターン52を切
断するという方法が用いられていた。
However, active matrix substrates have the problem that static electricity that builds up on the substrate during the manufacturing process destroys the insulation film at the intersections of switching elements and scanning signal lines and video signal lines, resulting in short circuits. Ta. As a measure to prevent damage to the insulating film due to static electricity,
Conventionally, as shown in FIG. 3, a method has been used in which all terminals of an active matrix substrate are short-circuited with a metal film pattern 52, and after assembly into a liquid crystal panel, this metal film pattern 52 is cut.

発明が解決しようとする課題 しかしながら、第3図に示したような従来の構成のアク
ティブマトリックス基板では信号線端子をショートして
いる金属膜パターン52が基板表面に露出していたため
、液晶パネルの完成後、フレキシブル基板などを使って
液晶パネルと駆動回路とを接続するときに、金属膜パタ
ーン52とフレキシブル基板が接触して信号線がショー
トするという問題点があり、金属膜パターン52とフレ
キシブル基板が接触しないように金属膜パターン52の
上に絶縁テープなどをはって絶縁処理を行っていた。
Problems to be Solved by the Invention However, in the conventional active matrix substrate shown in FIG. 3, the metal film pattern 52 shorting the signal line terminals was exposed on the substrate surface, making it difficult to complete the liquid crystal panel. Later, when connecting the liquid crystal panel and the drive circuit using a flexible substrate or the like, there is a problem that the metal film pattern 52 and the flexible substrate come into contact and short-circuit the signal lines. An insulating tape or the like was placed on top of the metal film pattern 52 to insulate the metal film pattern 52 to prevent contact.

本発明はかかる点に鑑みてなされたもので、静電気によ
る絶縁膜破壊を防止するための金属膜パターンとフレキ
シブル基板の接触による信号線のショートが防止できる
アクティブマトリックス基板を提供することを目的とし
ている。
The present invention has been made in view of the above, and an object of the present invention is to provide an active matrix substrate that can prevent short circuits in signal lines due to contact between a metal film pattern and a flexible substrate to prevent breakdown of an insulating film due to static electricity. .

課題を解決するための手段 本発明は上記した課題を解決するために、アクティブマ
トリックス基板のスイッチング素子の信号線を少なくと
も2本以上接続した金属膜パターン上に絶縁膜を形成す
るように構成したものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention is configured such that an insulating film is formed on a metal film pattern connecting at least two signal lines of switching elements of an active matrix substrate. It is.

作用 本発明は上記した構成により、絶縁テープなどで金属膜
パターンを絶縁することなしに、アクティブマトリック
ス基板と駆動回路とをフレキシブル基板などで接続する
ことを可能とし、実装行程を簡略化する。
Effect of the Invention With the above-described configuration, the present invention makes it possible to connect the active matrix substrate and the drive circuit with a flexible substrate or the like without insulating the metal film pattern with an insulating tape or the like, thereby simplifying the mounting process.

実施例 以下、本発明の一実施例のアクティブマトリックス基板
について図面を参照しながら説明する。
EXAMPLE Hereinafter, an active matrix substrate according to an example of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例におけるアクティブマトリッ
クス基板の構成図である。第1図において1は薄膜トラ
ンジスタ、2は走査信号および映像信号線の入力端子、
3は走査信号線および映像信号線をショートするための
金属膜パターン、4は金属膜パターン3上に形成した絶
縁膜、X1〜Xll1は走査信号線、Y1〜Ynは映像
信号線である。第2図は信号線2と金属膜パターン3、
絶縁膜4の第1図のa−a’部における略断面図である
FIG. 1 is a configuration diagram of an active matrix substrate in one embodiment of the present invention. In FIG. 1, 1 is a thin film transistor, 2 is an input terminal for scanning signal and video signal lines,
3 is a metal film pattern for short-circuiting the scanning signal line and the video signal line, 4 is an insulating film formed on the metal film pattern 3, X1 to Xll1 are scanning signal lines, and Y1 to Yn are video signal lines. Figure 2 shows signal line 2 and metal film pattern 3,
2 is a schematic cross-sectional view of the insulating film 4 taken along the line a-a' in FIG. 1. FIG.

第1図、第2図で本実施例の構造を説明する。The structure of this embodiment will be explained with reference to FIGS. 1 and 2.

信号線の入力端子2をガラス基板10上に形成するとき
に同時に信号線をショートさせる金属膜パターン3を形
成する。そして、スイッチング素子を形成するときに同
時に金属膜パターン3上に絶縁膜4を形成する。また、
入力端子2の上には絶縁膜4によって生じる段差を補正
するために、補助金属膜5を形成しである。
When forming the input terminal 2 of the signal line on the glass substrate 10, a metal film pattern 3 for shorting the signal line is formed at the same time. Then, when forming the switching elements, an insulating film 4 is formed on the metal film pattern 3 at the same time. Also,
An auxiliary metal film 5 is formed on the input terminal 2 in order to correct the step difference caused by the insulating film 4.

このように構成することによって、金W14膜パターン
3は絶縁膜4で絶縁されるのでフレキシブル基板などで
アクティブマトリックス基板と駆動回路を接続するとき
に、絶縁テープなどをはって絶縁処理を行わなくても金
属膜パターン3とフレキシブル基板が接触することはな
く、実装行程が簡略化される。
With this configuration, the gold W14 film pattern 3 is insulated by the insulating film 4, so when connecting the active matrix board and the drive circuit using a flexible board, etc., there is no need to apply insulation tape or the like to insulate the drive circuit. Even if the metal film pattern 3 and the flexible substrate are not in contact with each other, the mounting process is simplified.

発明の効果 以上の説明のように本発明は、アクティブマトリックス
基板のスイッチング素子の信号線を少なくとも2本以上
接続した金[膜パターン上に絶縁膜を形成するように構
成することで、絶縁テープなどで金属膜パターンを絶縁
することなしに、アクティブマトリックス基板と駆動回
路とをフレキシブル基板などで接続することを可能とし
、実装行程を簡略化することができる。
Effects of the Invention As described above, the present invention provides a structure in which an insulating film is formed on a gold film pattern to which at least two signal lines of switching elements of an active matrix substrate are connected. This makes it possible to connect the active matrix substrate and the drive circuit with a flexible substrate or the like without insulating the metal film pattern, thereby simplifying the mounting process.

【図面の簡単な説明】 第1図は本発明の一実施例におけるアクティブマI−I
Jフックス板の構成図、第2図は第1図のa−a’部に
おける略断面図、第3図は従来のアクティブマトリック
ス基板の構成を示す構成図である。 1・・・・・・薄膜トランジスタ、2・・・・・・入力
端子、3・・・・・・金属膜パターン、4・・・・・・
絶縁膜、5・・・・・・補助金属膜、X1〜Xff1・
・・・・・走査信号線、Y1〜Yn・・・・・・映像信
号線。 代理人の氏名 弁理士 粟野重孝 はか1名実 111
!!! 1−−一薄月IうJし゛人ヲ 2−−−3Is手 3−4^l冥ハ゛ダーツ 4−・jlを膿
[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 shows an active matrix I-I in an embodiment of the present invention.
FIG. 2 is a schematic sectional view taken along the line a-a' in FIG. 1, and FIG. 3 is a configuration diagram showing the configuration of a conventional active matrix substrate. 1... Thin film transistor, 2... Input terminal, 3... Metal film pattern, 4...
Insulating film, 5... Auxiliary metal film, X1 to Xff1.
...Scanning signal line, Y1 to Yn...Video signal line. Name of agent: Patent attorney Shigetaka Awano 111
! ! ! 1--Ichisuzuki I UJ Shiman wo 2--3Is hand 3-4^l Meihi Darts 4-・jl with pus

Claims (3)

【特許請求の範囲】[Claims] (1)ガラス基板上にスイッチング素子をマトリックス
状に配置したアクティブマトリックス基板であって、前
記スイッチング素子の信号線を少なくとも2本以上前記
ガラス基板上に形成した金属膜パターンで接続し、前記
金属膜パターン上に絶縁膜を形成したことを特徴とする
アクティブマトリックス基板。
(1) An active matrix substrate in which switching elements are arranged in a matrix on a glass substrate, wherein at least two or more signal lines of the switching elements are connected by a metal film pattern formed on the glass substrate, and the metal film An active matrix substrate characterized by having an insulating film formed on a pattern.
(2)信号線を接続した金属膜のパターンは、前記信号
線のパターン幅より十分太くして共通電極としたことを
特徴とする請求項(1)記載のアクティブマトリックス
基板。
(2) The active matrix substrate according to claim 1, wherein the pattern of the metal film to which the signal line is connected is sufficiently thicker than the pattern width of the signal line to serve as a common electrode.
(3)スイッチング素子が二端子素子、あるいは、薄膜
トランジスタで構成されていることを特徴とする請求項
(1)記載のアクティブマトリックス基板。
(3) The active matrix substrate according to claim (1), wherein the switching element is composed of a two-terminal element or a thin film transistor.
JP1078861A 1989-03-29 1989-03-29 Active matrix substrate Pending JPH02256029A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1078861A JPH02256029A (en) 1989-03-29 1989-03-29 Active matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1078861A JPH02256029A (en) 1989-03-29 1989-03-29 Active matrix substrate

Publications (1)

Publication Number Publication Date
JPH02256029A true JPH02256029A (en) 1990-10-16

Family

ID=13673610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1078861A Pending JPH02256029A (en) 1989-03-29 1989-03-29 Active matrix substrate

Country Status (1)

Country Link
JP (1) JPH02256029A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100308367B1 (en) * 1997-06-13 2002-07-18 마찌다 가쯔히꼬 Active matrix substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61130927A (en) * 1984-11-30 1986-06-18 Hitachi Ltd Liquid crystal display device
JPS62291688A (en) * 1986-06-11 1987-12-18 株式会社東芝 Display electrode array for active matrix type display unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61130927A (en) * 1984-11-30 1986-06-18 Hitachi Ltd Liquid crystal display device
JPS62291688A (en) * 1986-06-11 1987-12-18 株式会社東芝 Display electrode array for active matrix type display unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100308367B1 (en) * 1997-06-13 2002-07-18 마찌다 가쯔히꼬 Active matrix substrate

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