JPH04104226A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPH04104226A JPH04104226A JP2221162A JP22116290A JPH04104226A JP H04104226 A JPH04104226 A JP H04104226A JP 2221162 A JP2221162 A JP 2221162A JP 22116290 A JP22116290 A JP 22116290A JP H04104226 A JPH04104226 A JP H04104226A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- liquid crystal
- driving
- crystal display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010409 thin film Substances 0.000 claims description 9
- 239000010408 film Substances 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 22
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 10
- 238000000034 method Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 238000000151 deposition Methods 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 210000002858 crystal cell Anatomy 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229920000742 Cotton Polymers 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は液晶表示装置、とりわけ薄膜トランジスタをス
イッチング素子として用いたアクティブマトリクス型液
晶パネルによる液晶表示装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a liquid crystal display device, and particularly to a liquid crystal display device using an active matrix liquid crystal panel using thin film transistors as switching elements.
（従来の技術）
近年、微細加工技術、液晶材料、および実装技術の進歩
により、１〜５インチ程度のサイズで良好なテレビ画像
が得られる液晶表示装置が商用ベースで生産されるよう
になってきた。(Prior Art) In recent years, advances in microfabrication technology, liquid crystal materials, and packaging technology have led to the commercial production of liquid crystal display devices that are approximately 1 to 5 inches in size and can provide good television images. Ta.
このような液晶表示装置は、スイッチング素子を備えた
画像表示部に走査信号とデータ信号を供給するため、外
部から駆動用ＩＣを接続する必要があるが、その接続方
法は次の２つが主流である。In order to supply scanning signals and data signals to an image display section equipped with a switching element, such a liquid crystal display device needs to connect a driving IC from the outside, but the following two methods are mainstream for this connection. be.
１つは液晶表示装置を構成する一方の基板上に形成され
た走査信号線の端子群およびデータ信号線の端子群、た
とえばポリイミド樹脂薄膜ベースに銅薄膜線を多数形成
した接続フィルムを圧接して外部の駆動用ＩＣからの信
号を供給するいわゆるフィルムのキャリア方式であり、
もう１つは液晶表示装置を構成する一方の基板上の画像
表示部周辺に形成した実装端子に直接駆動用ＩＣを実装
するＣ０Ｇ（キップ・オン・グラス）方式である。One is a terminal group of scanning signal lines and a terminal group of data signal lines formed on one substrate constituting a liquid crystal display device, for example, by pressure-bonding a connection film in which a large number of copper thin film wires are formed on a polyimide resin thin film base. This is a so-called film carrier method that supplies signals from an external drive IC.
The other is the C0G (kip-on-glass) method, in which a driving IC is directly mounted on mounting terminals formed around an image display section on one substrate constituting a liquid crystal display device.
現在販売されている液晶テレビのほとんどは前者のフィ
ルムキャリア方式を採用したものであるが、ビデオカメ
ラのビューファインダーなどに使われる１インチ程度の
液晶パネルでは、省スペースのために後者のＣＯＧ方式
が採用されることが増えてきている。Most of the LCD TVs currently on sale use the former film carrier method, but the latter COG method is used to save space for approximately 1-inch LCD panels used in video camera viewfinders, etc. It is increasingly being adopted.
第３図はＣＯＧ方式を採用したアクティブ型液晶表示装
置の等何回路で、絶縁性基板１上に走査線群２と信号線
群３との交差点毎に絶縁ゲート型トランジスタ４のスイ
ッチ素子と液晶セル５が配置される。６は前述した全て
の液晶セル５に共通した透明導電層よりなる対向電極で
ある。また、７は走査線群２の実装用入力パッド１４に
ＣＯＧ接続される走査線駆動用ドライバ１７および信号
線群３の実装用入力パッドｌＯにＣＯＧ接続される信号
線駆動用ドライバ１３に駆動用電源および信号を供給す
るために絶縁性基板１上に形成された配線であり、９は
ドライバ駆動用信号供給配Ｍ７に外部からの信号を供給
するための供給側取り出し配線であり、１１および１５
はそれぞれ走査線駆動用ドライバ１７．信号線駆動用ド
ライバ１３にドライバ駆動用信号供給配線からの信号を
供給するための出力側取り出し配線である。ここで１２
および１６は、前記ドライバ１３と１７を出力側取り出
し配線１１と１５に実装接続するための実装用出力パッ
ドである。Figure 3 shows the circuits of an active liquid crystal display device that uses the COG method, in which a switch element of an insulated gate transistor 4 and a liquid crystal display are placed on an insulating substrate 1 at each intersection of a scanning line group 2 and a signal line group 3. Cell 5 is placed. Reference numeral 6 denotes a counter electrode made of a transparent conductive layer common to all the liquid crystal cells 5 described above. Further, 7 is used for driving a scanning line driving driver 17 that is COG-connected to the mounting input pad 14 of the scanning line group 2 and a signal line driving driver 13 that is COG-connected to the mounting input pad 10 of the signal line group 3. Wiring formed on the insulating substrate 1 for supplying power and signals, 9 is a supply side lead-out wiring for supplying external signals to the driver driving signal supply wiring M7, 11 and 15
are the scanning line driving drivers 17. This is an output side lead-out wiring for supplying a signal from the driver driving signal supply wiring to the signal line driving driver 13. here 12
and 16 are mounting output pads for mounting and connecting the drivers 13 and 17 to the output side lead-out wirings 11 and 15.
第４図は第３図の単位絵素の平面配置図であり、Ａ−Ａ
’綿線上断面図を第５図に示す。たとえば絶縁性基板１
上に走査線と絶縁ゲート型トランジスタのゲート配線を
兼ねる導電層１８がたとえば１０００人のＣｒ薄膜にて
選択的に被着形成され、また、絶縁性基板１上に絵素電
極２０をＩＴ○薄膜で被着形成される。そしてこののち
、能動素子が形成されるわけで、たとえば４０００人、
５００人、 １０００人の膜厚で第１のシリコン窒化層
２５（Ｓｉ、Ｎ、）、不純物をほとんど含まない第１の
非晶質シリコン層２３ａそして再び第２のＳ ｉ、 Ｎ
、層２４を好ましくは連続的に被着後、最上段のＳｉ、
Ｎ、層をゲート配線１８上に選択的に残したのち、非晶
質シリコン層２３ａと、そののちに形成するＡＩ２配線
１９および２１と良好なオーミック接触を得るための不
純物を含む第２の非晶質シリコン層２３ｂを５００人程
大全面に被着後、非晶質シリコン層２３ａと２３ｂを選
択的に残し、Ｓｉ、Ｎ、層２５を露出させる。モして絵
素電極２０と接触をとるための開口部２２を形成したの
ち、６０００人〜１００００人程度大全厚のＡｌ１を被
着後、選択的に残すことにより、信号線と絶縁ゲート型
トランジスタのソース配線Ｉ９およびドレイン配線２Ｉ
を形成することにより、液晶表示装置用半導体装置が完
成する。このとき、ドライバ駆動用信号供給配線７と、
取り出し配線９も同時に形成するが、その要部拡大図を
第６図に示し、Ｂ−Ｂ’縁線上断面図を第７図に示す。FIG. 4 is a plan view of the unit picture elements in FIG.
A sectional view taken along the cotton line is shown in Fig. 5. For example, insulating substrate 1
A conductive layer 18 serving as a scanning line and a gate wiring of an insulated gate transistor is selectively deposited on the insulating substrate 1 using, for example, a 1000 Cr thin film. It is deposited and formed. After this, active elements are formed, for example 4000 people,
A first silicon nitride layer 25 (Si, N,) with a thickness of 500 and 1000 layers, a first amorphous silicon layer 23a containing almost no impurities, and again a second Si, N layer.
, after preferably successive application of layers 24, the topmost Si,
After selectively leaving the N layer on the gate wiring 18, a second non-containing layer containing impurities is formed to obtain good ohmic contact with the amorphous silicon layer 23a and the AI2 wirings 19 and 21 that will be formed later. After approximately 500 crystalline silicon layers 23b are deposited over the entire surface, the amorphous silicon layers 23a and 23b are selectively left and the Si, N, and layers 25 are exposed. After forming an opening 22 for making contact with the pixel electrode 20, a layer of Al1 with a thickness of approximately 6,000 to 10,000 layers is deposited, and selectively left to connect the signal line and the insulated gate transistor. Source wiring I9 and drain wiring 2I
By forming this, a semiconductor device for a liquid crystal display device is completed. At this time, the driver driving signal supply wiring 7,
The lead-out wiring 9 is also formed at the same time, and an enlarged view of the main part thereof is shown in FIG. 6, and a sectional view taken along the line BB' is shown in FIG.
ここで、取り出し配線９はゲート配線１８と同じ導電層
にて形成され、絶縁層（Ｓｉ、Ｎ、層）２５を介して、
ソース配線１９およびドレイン配線２１と同じ導電層で
配線７が形成される。Here, the take-out wiring 9 is formed of the same conductive layer as the gate wiring 18, and is connected via an insulating layer (Si, N, layer) 25.
The wiring 7 is formed of the same conductive layer as the source wiring 19 and the drain wiring 21.
このとき、配線９と配線７との絶縁耐圧を向上させる目
的で第１のＳｉ、Ｎ４層２５に加え、非晶質シリコン層
２３ａ、第２のＳｉ、Ｎ、層２４や非晶質シリコン層２
３ｂを配線９と配線７の交差部に形成することが一般的
に行われている。その例を第８図に示し、ｃ−ｃ’縁線
上断面図を第９図に示す。当然多層膜２５．２３ａ、
２４．２３ｂは第４図に示す絶縁ゲート型トランジスタ
を構成する第１のＳｉ、Ｎ、層２５゜非晶質シリコン層
２３ａ、第２のＳｉ、Ｎ、層２４および非晶質シリコン
層２３ｂの形成時に同時に形成される。At this time, in order to improve the dielectric strength between the wiring 9 and the wiring 7, in addition to the first Si, N4 layer 25, an amorphous silicon layer 23a, a second Si, N, layer 24 and an amorphous silicon layer are added. 2
3b is generally formed at the intersection of the wiring 9 and the wiring 7. An example thereof is shown in FIG. 8, and a sectional view taken along the line c-c' is shown in FIG. 9. Naturally, the multilayer film 25.23a,
24 and 23b are the first Si, N, layer 25°, the amorphous silicon layer 23a, the second Si, N, layer 24 and the amorphous silicon layer 23b, which constitute the insulated gate transistor shown in FIG. formed simultaneously at the time of formation.
（発明が解決しようとする課題）
しかしながら、上記のような構成では、たとえば第６図
に示すような構成では、第８図に示すような構成に比べ
、配線７と配線９との間の絶縁多層膜２５．２３ａ、
２４．２３ｂの膜厚がたとえば２０００人少な大々るこ
とにより静電耐圧が生じ、そのために配線７と配線９と
の間の絶縁破壊による短絡が増加するという問題があっ
た。また、配線７と配線９との間の絶縁耐圧を向上させ
る第８図のような構成では、確かに静電耐圧については
向上するものの、非晶質シリコン層２３ｂの上層に導電
性金属、たとえばＡＪを被着形成後、特性安定化のため
の高温アニール（約２００℃〜２５０℃）が必要であり
、このとき、非晶質シリコン層２３ｂと第２のＳｉ、Ｎ
４層２４との間に熱的な応力の差が生じ、そのために第
２のＳｉ、Ｎ４層２４と非晶質シリコン層２３ｂとの間
の物理的密着力が非常に弱くなり、最悪の場合は配線７
が非晶質シリコン層２３ｂと共に、第２のＳｉ、Ｎ４層
２４のパタンがはがれてしまい、断線に到るという欠点
を有していた。(Problem to be Solved by the Invention) However, in the above configuration, for example, in the configuration shown in FIG. 6, the insulation between the wiring 7 and the wiring 9 is lower than in the configuration shown in FIG. multilayer film 25.23a,
There was a problem in that the film thickness of 24.23b was reduced by, for example, 2,000 layers, resulting in an increase in electrostatic withstand voltage, which increased short circuits due to dielectric breakdown between wiring 7 and wiring 9. Furthermore, in the configuration shown in FIG. 8 which improves the dielectric strength between the wiring 7 and the wiring 9, although the electrostatic withstand voltage is certainly improved, a conductive metal such as a conductive metal is added to the upper layer of the amorphous silicon layer 23b. After depositing and forming the AJ, high temperature annealing (approximately 200°C to 250°C) is required to stabilize the characteristics, and at this time, the amorphous silicon layer 23b and the second Si, N
A difference in thermal stress occurs between the second Si, N4 layer 24 and the amorphous silicon layer 23b. is wiring 7
However, the pattern of the second Si, N4 layer 24 is peeled off together with the amorphous silicon layer 23b, resulting in disconnection.
本発明の目的は従来の欠点を解消し、絶縁耐圧にすぐれ
、かつ、はがれによる断線も生じ難い構造を有するドラ
イバ駆動用信号供給配線を備えた液晶表示装置を提供す
ることである。SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device that eliminates the drawbacks of the prior art and is equipped with driver driving signal supply wiring that has excellent dielectric strength and is resistant to disconnection due to peeling.
（課題を解決するための手段）
本発明の液晶表示装置は、絶縁耐圧にすぐれ、かつ、物
理的密着力の弱さによるはがれを原因とする断線も生じ
難い構造を有するドライバ駆動用信号供給配線を提供す
るために、ドライバ駆動用信号供給配線と、その取り出
し配線の交差部の多層絶縁層を第１の絶縁層、第１の半
導体層、第２の絶縁層および第２の半導体層で構成し、
かつ第２の半導体層を第２の絶縁層の形状の外周を覆う
帯状の形状に形成するものである。(Means for Solving the Problems) The liquid crystal display device of the present invention has a signal supply wiring for driving a driver that has an excellent dielectric strength and a structure that does not easily cause disconnection due to peeling due to weak physical adhesion. In order to provide this, the multilayer insulating layer at the intersection of the driver drive signal supply wiring and its output wiring is composed of a first insulating layer, a first semiconductor layer, a second insulating layer, and a second semiconductor layer. death,
In addition, the second semiconductor layer is formed into a band-like shape that covers the outer periphery of the second insulating layer.
（作 用）
本発明は上記した構成により、絶縁多層膜を第１の絶縁
層だけで構成した場合に比べ、絶縁層の膜厚が増えるこ
とにより約５０Ｖ以上の絶縁耐圧の向上をはかることが
でき、かつ、第２の半導体層を第２の絶縁層のパターン
の外周を覆う帯状の形状に形成することにより、第２の
絶縁層と第２の半導体層との間に熱応力の差により生じ
る密着力の弱い部分の、この上層のドライバ駆動用信号
供給配線への影響を最小にすることができ、ひいてはド
ライバ駆動用信号供給配線のはがれによる断線を防止す
ることができるものである。(Function) With the above-described configuration, the present invention can improve the dielectric strength voltage by about 50 V or more by increasing the thickness of the insulating layer compared to the case where the insulating multilayer film is composed of only the first insulating layer. By forming the second semiconductor layer in a band-like shape that covers the outer periphery of the pattern of the second insulating layer, the difference in thermal stress between the second insulating layer and the second semiconductor layer causes The influence of the resulting weak adhesion portion on the driver driving signal supply wiring in the upper layer can be minimized, and furthermore, it is possible to prevent disconnection due to peeling of the driver driving signal supply wiring.
（実施例）
第１図は本発明の一実施例による液晶表示装置の要部拡
大図であり、同じく第１図のＤ−Ｄ′縁線上断面図を第
２図に示す。第３図ないし第９図に示したものと同一部
分については同じ符号を付し、その説明を省略する。(Embodiment) FIG. 1 is an enlarged view of a main part of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line DD' of FIG. 1. Components that are the same as those shown in FIGS. 3 to 9 are designated by the same reference numerals, and their explanations will be omitted.
まず第２図に示すように絶縁性基板ｌ上にドライバ駆動
用信号供給配線７の供給側取り出し配線９を第５図の絶
縁ゲート型トランジスタのゲート配線１８と同一導電性
薄膜にて同時に被着形成する。First, as shown in FIG. 2, the supply side lead-out wiring 9 of the driver driving signal supply wiring 7 is simultaneously coated on the insulating substrate l with the same conductive thin film as the gate wiring 18 of the insulated gate transistor shown in FIG. Form.
そののち、第１のシリコン窒化層２５、第１の非晶質シ
リコン層２３ａ、第２のシリコン窒化層２４を連続被着
後、ドライバ駆動用信号供給配線７と、供給側取り出し
配線９の交差部を覆う形状に蝕刻を行う。そして、第２
の非晶質シリコン層２３ｂを被着後、非晶質シリコン層
２３ａ、 ２３ｂとを同時に、かつ、第２のシリコン窒
化層２４の形状の端面を覆う帯状の形状にある幅をもっ
て蝕刻する。そののち、ドライバ駆動用信号供給配線７
を第５図の絶縁ゲート型トランジスタのソース配線１９
と同時に被着形成する。以上の被着形成は第５図の絶縁
ゲート型トランジスタの各層の被着形成と全く同一層の
同一工程で形成される。After that, after sequentially depositing the first silicon nitride layer 25, the first amorphous silicon layer 23a, and the second silicon nitride layer 24, the intersection of the driver drive signal supply wiring 7 and the supply side extraction wiring 9 is completed. Etch the shape to cover the area. And the second
After depositing the amorphous silicon layer 23b, the amorphous silicon layers 23a and 23b are simultaneously etched to a band-like shape with a width that covers the end face of the second silicon nitride layer 24. After that, the driver drive signal supply wiring 7
The source wiring 19 of the insulated gate transistor in FIG.
Adhesion is formed at the same time. The above deposits are formed in exactly the same layer and in the same process as the deposits of each layer of the insulated gate transistor shown in FIG.
以上のように本実施例により形成した液晶表示装置にお
いて、ドライバ駆動用信号供給配線７と供給側取り出し
配線９との交差部の絶縁耐圧は、第８図に示す構成に比
較してもほとんど変わらぬ程度を確保でき、かつ、非晶
質シリコン層２３ｂを帯状に形成することにより、熱応
力の差の大きいシリコン窒化層２４と非晶質シリコン層
２３ｂとの接触面積を最小にできる。この構成により、
その上層にドライバ駆動用信号供給配線７を被着形成し
ても、密着力の弱いシリコン窒化層２４と非晶質シリコ
ン層２３ｂの影響を最小にでき、かつ配線７を密着力の
強いシリコン窒化層２４の露出部の面積を最大にできる
ことにより、配線７の非晶質シリコン層２３ｂを伴った
はがれを防止することができる。As described above, in the liquid crystal display device formed according to this embodiment, the dielectric strength voltage at the intersection of the driver drive signal supply wiring 7 and the supply side take-out wiring 9 is almost unchanged compared to the configuration shown in FIG. By forming the amorphous silicon layer 23b in a band shape, the contact area between the silicon nitride layer 24 and the amorphous silicon layer 23b, which have a large difference in thermal stress, can be minimized. With this configuration,
Even if the driver driving signal supply wiring 7 is formed on the upper layer, the influence of the silicon nitride layer 24 and the amorphous silicon layer 23b, which have weak adhesion, can be minimized, and the wiring 7 can be made of silicon nitride, which has strong adhesion. By maximizing the area of the exposed portion of the layer 24, it is possible to prevent the wiring 7 from peeling off along with the amorphous silicon layer 23b.
（発明の効果）
本発明によれば、ドライバ駆動用信号供給配線とその取
り出し配線との交差部の絶縁層と第１の絶縁層、第１の
半導体層、第２の絶縁層、第２の半導体層の多層で構成
することにより、信号供給配線をその取り出し配線の交
差部の絶縁耐圧を向上させ、信号供給配線間の絶縁破壊
による短絡不良を低減させることができる。かつ、第２
の半導体層の形状を第２の絶縁層のパターンの外周を覆
う帯状の形状に形成することにより、第２の半導体層の
上層に形成されたドライバ駆動用信号供給配線のはがれ
による断線を防止することができ、その実用的効果は大
なるものがある。(Effects of the Invention) According to the present invention, the insulating layer, the first insulating layer, the first semiconductor layer, the second insulating layer, and the second insulating layer at the intersection of the driver drive signal supply wiring and its output wiring By configuring the signal supply wiring with multiple layers of semiconductor layers, it is possible to improve the dielectric strength of the intersection of the signal supply wiring and its output wiring, and to reduce short circuit failures due to dielectric breakdown between the signal supply wiring. And the second
By forming the semiconductor layer in a band-like shape that covers the outer periphery of the pattern of the second insulating layer, disconnection due to peeling of the driver driving signal supply wiring formed on the upper layer of the second semiconductor layer is prevented. It can be done, and its practical effects are great.
第１図は本発明の一実施例による液晶表示装置の要部拡
大図、第２図は同装置の要部断面図、第３図は一船釣Ｃ
ＯＧ用液晶表示装置の等価回路図、第４図は液晶表示装
置の単位絵素の平面配置図、第５図は第４図の要部断面
図、第６図および第８図は液晶表示装置の従来例の要部
拡大図、第７図および第９図はそれぞれ第６図及び第８
図の要部断面図である。
１ ・・・絶縁性基板、 ２ ・・・走査線群、３ ・
・・信号線群、 ４ ・・・絶縁ゲート型トランジスタ
、 ５ ・・・液晶セル、 ６ ・・・対向電極、 ７
・・・ ドライバ駆動用信号供給配線、 ８・・・外
部信号供給用実装パッド、 ９ ・・・信号供給側取り
出し配線、１０・・・信号線駆動用ドライバ実装用入力
パッド、１１・・・信号出力側取り出し配線、１２・・
・信号線駆動用ドライバ実装用出力パッド、１３・・・
信号線駆動用ドライバ、１４・・・走査線駆動用ドライ
バ実装用入力パッド、１５・・・信号出力側取り出し配
線、１６・・・走査線駆動用ドライバ実装用出力パッド
、１７・・・走査線駆動用ドライバ、 １８・・・導電
層、 １９・・・ ソース配線、２０・・・絵素電極、
２１ ・・・ ドレイン配線、２２゜２６、２７・・・
開口部、２３・・・非晶質シリコン層、２４．２５・・
・シリコン窒化層。
特許出願人 松下電器産業株式会社Fig. 1 is an enlarged view of the main parts of a liquid crystal display device according to an embodiment of the present invention, Fig. 2 is a sectional view of the main parts of the same device, and Fig. 3 is a one-boat fishing C
An equivalent circuit diagram of an OG liquid crystal display device, Fig. 4 is a planar arrangement of unit picture elements of the liquid crystal display device, Fig. 5 is a sectional view of the main part of Fig. 4, and Figs. 6 and 8 are the liquid crystal display device. The enlarged views of the main parts of the conventional example, Figures 7 and 9 are similar to Figures 6 and 8, respectively.
It is a sectional view of the main part of the figure. 1...Insulating substrate, 2...Scanning line group, 3.
... Signal line group, 4 ... Insulated gate transistor, 5 ... Liquid crystal cell, 6 ... Counter electrode, 7
... Signal supply wiring for driver drive, 8... Mounting pad for external signal supply, 9... Signal supply side extraction wiring, 10... Input pad for driver mounting for signal line drive, 11... Signal Output side wiring, 12...
・Output pad for mounting driver for signal line driving, 13...
Driver for signal line driving, 14... Input pad for mounting driver for driving scanning line, 15... Signal output side take-out wiring, 16... Output pad for mounting driver for driving scanning line, 17... Scanning line driving driver, 18... conductive layer, 19... source wiring, 20... picture element electrode,
21... Drain wiring, 22゜26, 27...
Opening, 23...Amorphous silicon layer, 24.25...
・Silicon nitride layer. Patent applicant Matsushita Electric Industrial Co., Ltd.
Claims (1)
上にマトリクス状に配列された画素電極と、前記画素電
極に近接して接続されてなる薄膜トランジスタと、前記
薄膜トランジスタのソース電極に接続されてなる信号配
線と、前記薄膜トランジスタのゲート電極に接続されて
なる走査配線を有してなる液晶表示装置において、前記
基板上の前記信号配線および、前記走査配線に信号を供
給すべく、前記基板上に形成、あるいは実装接続された
駆動用ドライバに入力信号を供給してなる第１のドライ
バ駆動用入力配線を形成し、それと交差するように形成
された第２の配線との交差部の絶縁を保つための絶縁層
が第１の絶縁層、第１の半導体層、第２の絶縁層および
第２の半導体層の多層膜で構成され、前記第２の半導体
層を、前記第２の絶縁層のパターンの外周部に覆う帯状
に形成することを特徴とする液晶表示装置。A liquid crystal is sealed on a pair of substrates, pixel electrodes arranged in a matrix on one of the substrates, a thin film transistor connected in close proximity to the pixel electrode, and a thin film transistor connected to the source electrode of the thin film transistor. In the liquid crystal display device, the liquid crystal display device includes a signal wiring formed on the substrate and a scanning wiring connected to the gate electrode of the thin film transistor. A first driver driving input wiring is formed by supplying an input signal to a driving driver formed or mounted and connected, and the intersection with a second wiring formed to intersect with the first driver driving input wiring is insulated. The insulating layer for maintaining the structure is composed of a multilayer film including a first insulating layer, a first semiconductor layer, a second insulating layer, and a second semiconductor layer, and the second semiconductor layer is connected to the second insulating layer. A liquid crystal display device characterized in that a pattern is formed in a band shape covering the outer periphery of the pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22116290A JPH083592B2 (en) | 1990-08-24 | 1990-08-24 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22116290A JPH083592B2 (en) | 1990-08-24 | 1990-08-24 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04104226A true JPH04104226A (en) | 1992-04-06 |
| JPH083592B2 JPH083592B2 (en) | 1996-01-17 |
Family
ID=16762448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22116290A Expired - Fee Related JPH083592B2 (en) | 1990-08-24 | 1990-08-24 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH083592B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015043064A (en) * | 2013-02-25 | 2015-03-05 | 株式会社半導体エネルギー研究所 | Display device and electronic apparatus |
| EP3369112A4 (en) * | 2015-10-30 | 2019-06-19 | Boe Technology Group Co. Ltd. | Display substrate, display device containing the same, and method for fabricating the same |
| US11621312B2 (en) | 2020-03-20 | 2023-04-04 | Samsung Display Co., Ltd. | Display device |
-
1990
- 1990-08-24 JP JP22116290A patent/JPH083592B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015043064A (en) * | 2013-02-25 | 2015-03-05 | 株式会社半導体エネルギー研究所 | Display device and electronic apparatus |
| EP3369112A4 (en) * | 2015-10-30 | 2019-06-19 | Boe Technology Group Co. Ltd. | Display substrate, display device containing the same, and method for fabricating the same |
| US11621312B2 (en) | 2020-03-20 | 2023-04-04 | Samsung Display Co., Ltd. | Display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH083592B2 (en) | 1996-01-17 |
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| LAPS | Cancellation because of no payment of annual fees |