JPH0225519B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for receiving audio data in speech synthesis. Remarkable progress has been made in recent technology related to speech synthesis methods, with waveform coding methods such as PCM and DPCM, and linear predictive coding methods represented by PARCOR being developed and put into practical use. Furthermore, line spectrum pairs (LSP:
Line Spectrum Pair) method has been developed. This LSP method encodes the characteristics of the frequency spectrum using frequency domain parameters, and the present invention is a method that reads this encoded data from a storage device, etc., synthesizes it into speech, and sends it as audio to an output terminal, etc. An audio data receiving method that reads audio data every frame period, and allows speech synthesis to be processed normally even if data is insufficient in a certain frame period during speech synthesis, as long as corrected data is received by the next frame period. The purpose is to provide The present invention provides a data buffer stack unit having an input terminal for inputting encoded audio data from an external storage device to a speech synthesis device that performs speech synthesis, and a data load terminal for setting the audio data. Logic is applied to the data load terminal from the data buffer stack unit to a frame pulse indicating that a conversion process is in progress for converting the audio data, and a repeat operation signal for repeatedly synthesizing the same audio data that has been subjected to the conversion process. The data stored in the data buffer stack section is The present invention is characterized in that new audio data can be stored in the data buffer stack section by inputting a signal to the input terminal and the data load terminal, regardless of the presence or absence of the data. The present invention will now be described in detail using the drawings. FIG. 1 is a system configuration diagram according to the present invention. In the figure, 1 is a control device, 2 is a speech synthesizer, 3 is a storage device, 4 is a digital-to-analog converter, and 5
is a low pass filter, AMP is an amplifier, 7 is a transformer, and S ₁ and S ₂ are speakers. In FIG. 1, a control device 1 specifies an address 13 to a storage device in which audio data is stored, and the designated audio data 32 enters a speech synthesizer 2 that performs arithmetic processing. The speech synthesizer 2 is started and controlled by the control device 1 using a control signal 21, and data requests and status information from the speech synthesizer 2 are sent to the control device 1 via a status signal 12. On the other hand, the digital information of the voice synthesized by the voice synthesizer 2 is transferred to the digital-to-analog converter 4.
to speaker S ₁ , or an internal digital-to-analog converter converts analog audio to speaker S 1.
Sent to _S2 . FIG. 2 is a circuit diagram of the speech synthesizer 2 shown in FIG. 1. In the figure, 22 is a data buffer stack section that holds the necessary amount of audio data, 23 is an interface section, 231 is a control section that receives control signals from the control device, 232 is a status register that sends status signals to the control device, 24 is a control section consisting of an oscillation and timing circuit; 25 is an arithmetic section; 26 is a conversion section that takes in data from the data buffer stack section at an appropriate timing;
7 is an interpolation section, 28 is a sound source section which takes in pitch information from the data in the data buffer stack, 29 is a digital filter, and 20 is a digital/analog conversion section. Data buffer stack section 22
Audio data sent from the storage device (for example, consisting of sound source pitch, amplitude, LSP parameters, etc.)
D ₀ to D ₇ and the data load signal DL, which is a clock for writing audio encoded data, are used as input information,
The control register 231 of the interface section 23 receives a control register load signal.
CRL, repeat signal RPT that maintains audio information for a certain period of time, signal line T ₀ that sets the frame period,
_T1 (in this embodiment, four types can be specified with two bits _T0 and _T1 ), a mode signal MODE, and other signals A, B, etc. are input. The repeat signal is input in order to repeatedly output a certain audio output. In addition, the status register outputs an audio data request signal REQ, a fault indication ALM, a running (voice synthesis processing in progress) indication RUN, etc. The control unit inputs control information etc. from an external device (for example, a device system different from the control device), and also inputs the frame pulse FP or signal line created internally.
It outputs frame pulses FP and other various timing signals generated according to the frame period specified by T ₀ and T ₁ . Frame pulse FP is used for internal conversion of input data/
This indicates calculation/transfer processing feedback, and is used to inhibit external input data to prevent data conflicts. The operation of the speech synthesizer shown in FIG. 2 will be briefly explained based on the system configuration diagram shown in FIG. The storage device 3 stores sound source pitch, amplitude information, and quantized frequency spectrum of the sound of words or sentences, whose features are extracted by sampling frequency.
The audio data is stored as audio data such as LSP parameters, and the audio data is sent to the audio synthesizer 2 in units of 8 bits, for example, by address designation from the control device 1. This sent audio data is held in the data buffer stack section 22, and read out to the conversion section 26 and sound source section 28 at frame intervals.
The conversion section decodes the amplitude information LSP parameter and sends it to the interpolation section 27. The interpolation section 27 linearly interpolates the converted data input from the conversion section for each frame period for one frame, and outputs one set for each sample period to the digital filter section.Meanwhile, the sound source section 28 uses the sound source pitch information to perform linear interpolation for one frame. Generates an impulse or white noise that drives a digital filter. The digital filter section 29 executes a predetermined synthesis operation based on input coefficients from the interpolation section, impulses from the sound source section, or random number input, and outputs audio information (digital). The output section includes a terminal OUT ₁ that outputs this digital output information as it is to an external device, and a terminal that outputs it as analog information via the digital-to-analog conversion section 20.
Equipped with OUT ₂ . Note that the same effect can be obtained even if a memory for storing voice data is provided within the voice synthesis device. The data buffer stack unit 22 consists of a group of shift registers in several stages to hold a set of audio data, and each time the data is set to the input terminals D ₀ to D ₇ and DL, it is shifted in units of, for example, 1 byte. Hold the required number of bytes. For this reason, conventionally, when some data is erroneously stored in the data buffer stack section 22, or when some data that should be stored is missing, it has not been possible to correct the data. Therefore, there is a drawback that erroneous data may be reproduced as is in the audio.The present invention, in order to solve the above-mentioned problem, makes it possible to correct and add data. Furthermore, in order to efficiently correct and add data, the present invention focuses on the fact that new data is not required while data is being repeatedly processed.
During repeat processing, corrected and additional data is input to the data buffer stack section. FIG. 3 is a circuit configuration diagram that specifically enables the data transfer method of the present invention, and FIG. 4 is an explanatory diagram showing the temporal relationship with the frame period. In FIG. 3, the same symbols as those used in FIG. 2 indicate the same components; I is an inverter, OR is an OR circuit, and AND is an AND circuit. Figure 4 is the third
Input terminals D ₀ to D ₇ , DL, ST and output terminal FP in the figure
It shows the level relative to the time. When the start from the control device is input from the start signal ST, the interface section 23 instructs the control section, and the frame period setting terminal shown in FIG.
A frame pulse FP is generated according to the instructions of T ₁ , T ₀ and the mode signal MODE. This frame pulse FP is inverted by an inverter I, the repeat signal is ORed by an OR circuit, and the output information is ANDed by a data load signal DL and an AND circuit, thereby creating a data buffer stack section 22. Instructs to enable/disable reception of audio data. Normally, the output of the repeat signal is at a low level (L level) and a repeat operation is not performed, so data reception is controlled by the frame pulse. For example, during voice synthesis or before the activation signal is applied, the voice data can be transferred by changing the data load signal DL from low level (L level) to high level (H level) at any time while the frame pulse is at low level (L level). (It goes without saying that the opposite change is also possible.) When the frame pulse becomes high level (H level), it becomes unacceptable even if a change from low to high level is input to the data load signal. Further, during the repeat operation, even if the frame pulse is at a high level (H level), audio data can be accepted by changing the data load signal from a low level to a high level. The above logic is shown in the table below. In this table, data load terminal DL is set depending on the conditions of frame pulse FP and repeat signal RPT.
regulates the signals input to the When there is a rising edge change in the signal input to the data load terminal DL, it indicates that data reading is to be performed. That is, in the circuit configuration of FIG.
Data is accepted and invalidated (not accepted) according to the logic in the table below.

【table】

[Table] Note that the high (H) and low (L) signal levels are not limited to this logic, and can be similarly configured as high (L) and low (H). In Figure 4, the frame pulse rises (a)
While data is being transferred from the data buffer stack to the converter and sound source, data in the data buffer stack may be added, except during repeat operation.
Although it cannot be corrected, it is possible to accept audio data while a frame pulse is generated, for example, the period indicated by i in the figure, and the data of 8 bits x the number of required buffers indicated by D ₀ to D ₇ is initially d. After the data is set at the DC, corrections, additions, etc. to the data can be made at the DC. FIG. 5 shows an example of the data structure stored in the data buffer stack section. In the figure, C is control information, T is sound source pitch, AP is amplitude, and W ₁ to _{W 8} are LSP parameters. This data represents one phoneme in 8 bits x 6 words, and several tens of blocks of these are collected to reproduce one word. These 6 bytes of information are sequentially received and stored in the previous data buffer stack. According to the reception method of the present invention, these 6 bytes of data are re-inputted together with the data load signal between frame pulses, thereby invalidating the old data. In the above example, one phoneme is composed of 8 bits x 6 words, but the invention is not limited to this. As explained above, according to the audio data reception method of the present invention, it is possible to modify data in the period between frame pulses, and even if data is insufficient, it is also possible to add data in the same period. . In addition, by inputting audio data before starting speech synthesis, it is possible to start speech synthesis immediately after startup, and it can be used even for storage devices with slow access times, so it has a wide range of applications.
Can provide LSP method.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram according to the present invention, FIG. 2 is a circuit configuration diagram of a speech synthesis device according to the present invention, and FIG.
The figure is a partial circuit configuration diagram of a voice synthesis device for realizing the voice data reception method of the present invention, Figure 4 is an explanatory diagram showing the time relationship with the frame period according to the present invention, and Figure 5 is the voice data structure. It is a figure showing an example. 22: Audio data buffer stack section, 23:
Interface section, 24: Control section, 26: Conversion section, 28: Sound source section, _D0 to _D7 : Audio data, DL:
Data load signal, FP: frame pulse,
RPT: Repeat signal, I: Inverter, AND:
AND circuit, OR: OR circuit.

Claims (1)

[Scope of Claims] 1. A data buffer stack unit having an input terminal for inputting encoded voice data from an external storage device to a voice synthesis device that performs voice synthesis, and a data load terminal for setting the voice data. a frame pulse indicating that a conversion process is in progress for converting the audio data from the data buffer stack unit;
A repeat operation signal for repeating voice synthesis of the same converted voice data is logically connected to the data load terminal for a period from immediately after a frame pulse is generated to immediately before the next frame pulse is generated. During input of repeat operation signal regardless of frame pulse,
Regardless of the presence or absence of data stored in the data buffer stack, new audio data can be stored in the data buffer stack by inputting a signal to the input terminal and the data load terminal. Characteristic voice data reception method.