JPH0664477B2 - Speech synthesizer - Google Patents

Description

The present invention relates to a voice synthesizer that synthesizes voice data and outputs a voice signal.

The method used in the speech synthesizer is PARCOR (partial autocorrelatio)
n) (Partial autocorrelation) method, LPC (linear predictive codi
ng) (linear predictive coding) method, LSP (line spectrum pai
r) (line spectrum pair) method and the like are known. Since these methods have a higher data compression degree than the waveform coding method in which the voice waveform is encoded in PCM or the like, the capacity of the memory for storing the voice data can be reduced.

In speech synthesis, for example, one set of speech data (for example, 6 bytes) is converted for each frame cycle by a predetermined procedure, and interpolation output for each sample cycle is added as a coefficient of a digital filter by linear interpolation or the like, and a pulse train from a sound source section is added. Alternatively, white noise is added to a digital filter to perform voice synthesis. For example, in the synthesis of voices containing the same sound over a plurality of frames, that is, in the synthesis of so-called long sound or signal sound, voice data over a plurality of frames Need to prepare.
That is, when a long sound or a continuous signal sound is synthesized and output, a large amount of voice data corresponding to it has to be accumulated.

The present invention relates to the synthesis of voices containing the same continuous sound,
The purpose is to enable composition with one or more sets of audio data. Here, the voice data is data in which characteristic portions of the voice (pitch period, amplitude, characteristic parameters, etc.) are converted into data, and is shown in correspondence with the drawings of the embodiment in order to clarify the configuration of the present invention. That is, characteristic components such as the pitch period, amplitude, and characteristic parameter of the voice are extracted, and the voice data stored in the external memory (2) as voice data having a constant byte length is read for each specific period and voice synthesis is performed. In the voice synthesizer, a conversion unit (16) for converting the amplitude and characteristic parameter data in the voice data read in the specific cycle into digital filter coefficients, and converting the conversion unit (16). Interpolation means (17) for generating and interpolating digital filter coefficients at predetermined intervals between the specific cycles by the digital filter coefficients obtained in this way and the digital filter coefficients obtained in the immediately preceding cycle. A pulse train generated based on the data of the pitch period in the audio data, and the interpolation means (17). A digital filter means (19) for performing voice synthesis by performing a predetermined filter operation using the obtained digital filter coefficient, and a memory for storing control information given from an external device (1) such as start, stop, and repeat operation of voice synthesis. Means (1
2), when the information instructing the repeat operation in the control information is stored in the storage means (12), the conversion operation of the audio data by the conversion means (16) and the interpolation by the interpolation means (17) A voice synthesizing device characterized in that the same sound is synthesized by stopping the operation and giving the digital filter coefficient obtained by the interpolating means (17) immediately before the operation to the digital filter means (19). . Examples will be described in detail below.

FIG. 1 is a block diagram when voice synthesis is performed by control of a microprocessor or the like. 1 is a microprocessor, 2 is a memory storing a voice tape, 3 is status information sent to the microprocessor 1, Further, a voice synthesizing circuit 4 which operates according to control information from the microprocessor 1 and synthesizes voice by processing such as conversion and interpolation of voice data from the memory 2 is used for original oscillation for generating timing signals and the like. Is a crystal oscillator, 5 is a DA converter, 6 is a low-pass filter, 7 is an amplifier, 8 and 10 are speakers, and 9 is a transformer.

The voice data is read from the memory 2 by the address signal from the microprocessor 1 and added to the voice synthesizer circuit 3. The control information from the microprocessor 1 starts and stops the voice synthesizer and selects the frame period. , Voice synthesis is executed based on the voice data. When the combined output is digital serial output, it is converted into an analog audio signal by the DA converter 5, amplified by the amplifier 7 via the low-pass filter 6, and the speaker 8 is driven. Since the simple DA converter is built in the voice synthesis circuit 3, the speaker 10 can be driven via the transformer 9, for example. The voice quality in this case is somewhat low because it is converted to an analog signal by the simple DA converter.

In the present invention, a repeat mode designating bit is provided in the control information added to the voice synthesizing circuit 3. When this bit is set to, for example, "0", a normal voice synthesizing process is performed and "1" is set. In this case, conversion of audio data, interpolation, etc. are stopped, and audio signals according to the same data are output. That is, the same sound is continuously output, and the voice data for that is 6 bytes, for example.

FIG. 2 is a block diagram of the voice synthesizing circuit. Reference numeral 11 is a data buffer stack consisting of registers which set voice data (D0 to D7) by a signal and hold the voice data until conversion. Is an interface section, 13 is a control register for setting control signals ST, RPT, T0, T1, MODE, SBE with signals, 14 is a signal as status information, and is a status register for outputting with signal SE, and 15 is voice synthesis. Reference numeral 16 denotes a conversion unit configured by a read-only memory (ROM) for converting audio data into filter coefficients, and 17 an interpolation unit for interpolating the filter coefficients added for each frame period for one frame and outputting for each sample period, Reference numeral 18 is a sound source section, 19 is a digital filter section, 20 is a simple DA converter, and 21 is a control section for generating a timing signal and controlling each section.

The voice synthesizing circuit 3 is an integrated circuit, V _DD and V _SS V _SA are power supply voltages, and the symbols shown at the other terminals are signals. For example, ST is a start signal indicating voice synthesis start, RPT is a repeat mode designation signal, is a voice data request signal, is an alarm signal, FP is a frame pulse, SOUT is a digital voice output signal, POUT and NOUT are analog voice output signals, XOUT is a basic clock for internal logical operation, WSYN is a sync signal of SOUT, MR is an internal flip-flop and a reset of counters, CKST is a control of a crystal oscillation circuit, and CLK and XTAL are crystal oscillator connection terminals.

In the case of the LSP system, as the voice data, for example, a 1-bit start bit, a 7-bit pitch period data, a 2-bit frame length designating bit and a 6-bit amplitude data,
A set of 6 bytes consisting of 4-bit LSP parameters makes it possible to specify a frame length of 5, 10, 20, 40 mS.

Such voice data is added to the data buffer 11 from the memory, set by the signal (data load pulse), the conversion unit 16 converts the LSP parameter and the amplitude data into filter coefficients, and transfers them to the interpolation unit 17. It The interpolator 17 linearly interpolates every sample period and outputs a filter coefficient to the digital filter unit 19.
Further, the sound source section 18 generates impulses or white noise according to the pitch cycle data in the voice data and adds them to the digital filter section 19.

The digital filter unit 19 includes an adder / subtractor circuit, a multiplier circuit, etc., and operates as a voice synthesizing filter by the operation of the pulse train from the sound source unit 18 and the filter coefficient from the interpolating unit 17, for example, a 16-bit serial voice signal is synthesized. Is output.

The above operation is for the case where the repeat mode designating signal RPT is "0", and when the repeat mode designating signal RPT is set to "1" to perform the repeat operation, the conversion and interpolation operations are stopped as described above. Then, the pulse train from the sound source unit 18 is output as the same sound by the calculation by the digital unit 19 with a constant filter coefficient.

FIG. 3 is a block diagram of an essential part of the embodiment of the present invention.
1, 32, 33, 39, 43 are inhibit gates, 40 is an AND gate, 46, 47 are OR gates, 34 is a flip-flop, 35 is a timing adjustment circuit, 36 is a register for holding pitch cycle data, 37 is a sound source generation circuit. , 38 and 45 are addition circuits, 41 is a difference value register, 44 is an interpolation value register, and 42 is a 1 / 2n circuit.

The voice data D0 to D7 read from the memory are set in the data buffer 11 by the data load pulse DL. When the repeat mode designating signal RPT is "0", "0" is added to the data terminal D of the flip-flop 34, and even if the write timing pulse CRL is applied to the clock terminal C, the flip-flop 34 is not set, so that the output terminal. Q
Remains "0". Therefore, each output of the timing adjustment circuit 35 also becomes "0". And read timing pulse for conversion
t1 is added to the data buffer 11 via the inhibit gate 31 and the OR gate 46 so that the amplitude data and LSP parameters in the audio data are transferred to the converter 16 and the pitch period data is transferred to the register 36 of the sound source 18. Added. A pitch cycle data update timing pulse t2 is applied to the register 36 via the inhibit gate 32, and the pitch cycle data is updated at that timing. The sound source generation circuit 37 outputs a pulse train according to the pitch cycle data of the contents of the register 36 and adds it to the digital filter unit 19.

The conversion output of the conversion unit 16 is applied to the addition circuit 38 of the interpolation unit 17, and the difference calculation timing signal t3 applied via the inhibit gate 33 causes the output of the addition circuit 38 to differ via the AND gate 40 and the OR gate 47. It is added to the value register 41. The adder circuit 38 is a conversion output and digital filter section.
The difference between the output of the adder circuit 45 and the filter coefficient added to 19 is set in the difference value register 41, and the contents of the difference value register 41 are divided into sample periods by the 1 / 2n circuit 42, and the divided outputs are added. Added to circuit 45. The interpolation value register 44 stores the filter coefficient previously output to the digital filter unit 19, and the adding unit 45 adds the filter coefficient of this previous output and the divided output, and the resulting filter coefficient is supplied to the digital filter unit 19. It is output and stored in the interpolation value register 44. Next time, the adder circuit 45 takes out the newly stored filter coefficient from the interpolation value register 44 and adds it to the divided output. That is, the difference between the coefficient input from the conversion unit 16 and the coefficient of the previous frame is calculated for each frame cycle, the difference is divided by the number of samples in one frame, and the value for each sample is calculated. Interpolation processing is performed by adding each value to the coefficient of the previous frame for each sample, and the filter coefficient is added to the digital filter unit 19 for each sample.

When the repeat mode designating signal RPT becomes "1", the flip-flop 34 is set when the write timing pulse CRL becomes "1", and the timing adjusting circuit 35 adjusts the timings respectively and the inhibit gates 31, 32, 3
Added to 3,43, which allows data buffering
The reading from 11 is stopped, and the updating operation of the register 36 of the sound source section 18 is stopped. Adder circuit 45 for each sample
Since the divided output for addition at is blocked by the inhibit gate 43, the interpolation operation is stopped. Therefore, the sound source generation circuit
37 outputs a pulse train according to the pitch cycle data of the previous frame, the contents of the interpolation register 44 does not change in frame cycle units, and is fixed at the filter coefficient immediately before the interpolation operation is stopped. It is added to the section 19 and the same sound is continuously output.

FIG. 4 is a diagram for explaining the operation, and FIG. 4A shows the case where the repeat mode designation signal RPT is set to “1” during the period when the request signal is “1”, and the frame pulse FP changes from “1” to “0”. When it becomes ", the request signal becomes" 0 "and the audio data DATA
Is requested, the data of #m is read, and the voice synthesis operation M
In the period T1 of, the conversion of the data from # m-2 to # m-1 and the filter operation in the digital filter section are performed, and voice synthesis is performed.

When the repeat mode designation signal RPT becomes "1", the request signal does not become "0" after the next frame pulse FP, so that new audio data DATA is not read.
Then, in the period T2, the filter operation is performed with the interpolation value immediately before the rise of the frame pulse FP, and the conversion, difference calculation, and interpolation operation are not performed.

When the repeat mode designation signal RPT becomes "0", # m-2 to # m-1 in the period T3 of the next frame pulse FP.
The final step of interpolating the data of # 1 and the filter operation are performed, and then the conversion of #m data and the difference calculation of # m-1 and #m data are performed. Then, the request signal becomes "0" and the next data # m + 1 is read.

FIG. 4B shows a case where the repeat mode designation signal RPT is set to "1" while the request signal is "0".
The alarm signal is in the "1" state, the request signal becomes "1" after the frame pulse FP after the repeat mode designation signal RPT changes from "1" to "0", and other than normal operation Become. The voice synthesizing operation during the period when the repeat mode designating signal RPT is "1" is similar to the above case.

Although the above-described embodiment mainly describes the LSP method, it is also applicable to the PARCOR method and the LPC method.
The voice data may be the analysis result of a relatively long word or sentence, or the analysis result of a voice unit used in the VCV method in which a vowel V and a consonant C are combined.

As described above, the present invention is an apparatus for performing voice synthesis by reading voice data and a fixed number of bytes for each specific period of a designated frame period, and for controlling the control register 13 for storing control information. Storage means and conversion means such as a conversion unit 16 for converting voice data into filter coefficients,
The repeat mode specifying signal RPT provided in the control information is provided with an interpolating unit such as an interpolating unit 17 for interpolating the filter coefficient for each sample period, and a digital filter unit 19 for performing operations such as addition and subtraction multiplication according to the filter coefficient. When stored in the storage means such as the control register 13, the conversion operation by the conversion means and the interpolation operation by the interpolation means are stopped, and speech synthesis is performed immediately before that by using the result converted by the conversion means. When continuously synthesizing and outputting sounds, it is not necessary to read the audio data in every specific cycle,
Since the same sound of arbitrary length can be synthesized and output with one set of voice data, the capacity of the voice data memory can be reduced, and the synthesis of signal sounds and the like becomes easy.

[Brief description of drawings]

FIG. 1 is a block diagram of a system for synthesizing voice by controlling a microprocessor, FIG. 2 is a block diagram of a voice synthesizing circuit of an embodiment of the present invention, and FIG. 3 is a main part of an embodiment of the present invention. A block diagram and FIG. 4 are operation explanatory diagrams. 1 is a microprocessor, 2 is a memory, 3 is a voice synthesis circuit, 11 is a data buffer stack, 12 is an interface unit, 13 is a control register, 14 is a status register, 15 is a voice synthesis unit, and 16 is a conversion unit. , 17 is an interpolation unit, 18 is a sound source unit, 19 is a digital filter unit, 20 is a DA converter, and 21 is a control unit.

Front page continued (72) Inventor Yujiro Sasahara 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Fumada Itakura, 3-9-11 Midoricho, Musashino City, Tokyo Nippon Telegraph and Telephone Public Corporation Musashino Telecommunications In the laboratory (72) Inventor Shigeki Sagayama 3-9-11 Midoricho, Musashino-shi, Tokyo Inside Nippon Telegraph and Telephone Public Corporation Musashino Telecommunications Research Institute (72) Inventor Noboru Tsunemura 3-9-11 Midoricho, Musashino-shi Japan Telegraph and Telephone Public Corporation Musashino Electro-Communication Research Laboratory (56) References JP-A-55-2234 (JP, A) JP-A-51-123003 (JP, A)

Claims (1)

[Claims] 1. A characteristic component such as a pitch period, an amplitude, a characteristic parameter of a voice is extracted, and the voice data stored in an external memory (2) as voice data having a constant byte length is read every specific period. In a voice synthesizer for reading voice synthesis, a conversion unit (16) for converting the amplitude and characteristic parameter data in the voice data read at each specific cycle into digital filter coefficients, and the conversion unit (16). ), And an interpolation means for generating and interpolating a digital filter coefficient at a predetermined interval between the specific cycles by the digital filter coefficient obtained by the conversion and the digital filter coefficient obtained in the immediately preceding cycle. (17), a pulse train generated based on the pitch cycle data in the audio data, and the interpolation means (1 Digital filter means (19) for performing voice synthesis by performing a predetermined filter operation using the digital filter coefficient obtained from 7) and control information given from an external device (1) such as start, stop and repeat operation of voice synthesis. Storage means for storing (1
2), when the information instructing the repeat operation in the control information is stored in the storage means (12), the conversion operation of the audio data by the conversion means (16) and the interpolation by the interpolation means (17) A voice synthesizing apparatus which synthesizes the same sound by stopping the operation and giving the digital filter coefficient (19) obtained by the interpolating means (17) immediately before the operation.