JPH0310960B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voice synthesis device that synthesizes voice data and outputs a voice signal.

As a speech synthesis method, PARCOR (partial autocorre
−lation) (partial autocorrelation) method, LPC
(linear predictive coding) method, LSP (line spectrum pair) method, etc. are known. These methods have a higher degree of data compression than waveform encoding methods in which audio waveforms are encoded into PCM or the like.

Speech synthesis involves, for example, converting a set of audio data (for example, 6 bytes) for each frame period according to a predetermined procedure, adding the interpolated output for each sample period using linear interpolation etc. as coefficients of a digital filter, and converting the pulse train from the sound source. Alternatively, white noise is added to a digital filter to obtain a speech synthesis output. Normally, the audio data of the next frame is read while processing a certain frame, and if there is insufficient audio data or cannot be read at all, abnormal data is used as the basis. Since voice synthesis is performed using the same method, the voice output will be abnormal.

An object of the present invention is to detect abnormalities in audio data as described above and prevent abnormal audio output. Examples will be described in detail below.

Figure 1 is a block diagram of a system that performs speech synthesis under the control of a microprocessor.
is a microprocessor, 2 is a memory that stores audio data, 3 is a speech synthesis circuit, 4 is a crystal oscillator for primary oscillation for timing signal generation, etc., and 5 is a DA.
Converter, 6 is a low-pass filter, 7 is an amplifier,
8 and 10 are speakers, and 9 is a transformer.

Voice data is read from the memory 2 according to the address signal from the microprocessor 1 and applied to the voice synthesis circuit 3, and control information from the microprocessor 1 controls the start and stop of voice synthesis in the voice synthesis circuit 3, and the frame period. The selection etc. are controlled, and the state information of the speech synthesis circuit 3 is sent to the microprocessor 1.
will be sent to. When the audio output of the audio synthesis circuit 3 is a digital serial output, it is converted into an analog audio signal by the DA converter 5, and is applied to the amplifier 7 via the low-pass filter 6, and the speaker 8 is driven by the amplified output. Furthermore, since the speech synthesis circuit 3 has a built-in simple DA converter, it is also possible to drive the speaker 10 via the transformer 9. The audio quality in this case is somewhat low because it is converted into an analog audio signal by a simple DA converter.

Figure 2 is a block diagram of the speech synthesis circuit.
Reference numeral 11 denotes a data buffer stack consisting of a group of registers in which audio data D0 to D7 are set by signals and held until the audio data is converted;
is the interface section, 13 is the start/stop signal ST,
Repetition signal RPT that stops interpolation operation and specifies repeated synthesis operation using the same data; frame period setting signals T ₀ and T ₁ ; variable/fixed frame length mode specification signal MODE; Top bit enable signal
A control register is used to set control signals such as SBE, etc.; 14 is a status register that outputs a signal as a status signal by a signal SE; 15 is an audio converter; 17 is an interpolation unit that interpolates and outputs the filter coefficients added at each frame period at each sample period; 18 is a sound source unit;
19 is a digital filter section, 20 is a simple type
A DA converter 21 generates timing signals etc.
This is a control unit that controls each part, and is implemented as an integrated circuit. The symbol shown on each terminal represents the signal, V _DD , V _SS , V _SA are the power supply voltages, and SOUT is, for example,
16-bit serial digital audio output signal,
For example, POUT and NOUT are analog audio output signals converted to analog signals by an 8-bit simple DA converter 20, XOUT is a basic clock for internal logic operations, WSYN is a synchronization signal for SOUT, and MR is an internal flip-flop, counter, etc. CKST is the control signal for the crystal oscillation circuit, CLK and XTAL are the crystal resonator connection terminals, and FP is the frame pulse.

In the case of the LSP method, the audio data includes, for example, a 1-bit start bit, 7-bit pitch cycle data, 2-bit frame length designation bits, and 6-bit start bit.
A set of 6 bytes consists of bit amplitude data and LSP parameters of 4 bits each, and the frame length can be specified as, for example, 5, 10, 20, or 40 mS.

Such audio data is added to the data buffer stack 11 from the memory, set by a signal (data load pulse), converted into filter coefficients by the conversion section 16 using the LSP parameters and amplitude data, and then sent to the interpolation section 17. Added. The interpolation section 17 performs linear interpolation for each sample period and adds filter coefficients to the digital filter section 19. Further, the sound source section 18 generates a pulse train according to the pitch period data in the audio data and applies it to the digital filter section 19.

The digital filter unit 19 includes an addition/subtraction circuit, a multiplication circuit, etc., and operates as a voice synthesis filter by calculating the pulse train from the sound source unit 18 and the filter coefficients from the interpolation unit 17, and converts, for example, a 16-bit serial digital audio signal. Output.

FIG. 3 is a block diagram of the main parts of the embodiment of the present invention, 31, 32, 33, 39, 43 are inhibit gates, 40 is an AND gate, 46, 47 are OR gates, 35 is a data shortage detection, timing A detection and control circuit 36 that performs adjustment and operation restart control includes a register 3 that holds pitch cycle data.
7 is a sound source generation circuit, 38 and 45 are addition circuits, 41
is a difference value register, 44 is an interpolation register, and 42 is a 1/2 ⁿ circuit.

The audio data D0 to D7 read from the memory are set in the data buffer stack 11 by the data load pulse DL as described above. Normally, each output of the detection and control circuit 35 is "0", so the inhibit gates 31, 32, 33, 43
is open, and the conversion read timing pulse t
1, the audio data is read from the data buffer stack 11, the amplitude data and LSP parameters are added to the converter 16, and the pitch period data is added to the register 36 of the sound source section 18, and the pitch period data update timing is set. Register 3 by pulse t2
The contents of 6 are updated. The sound source generating circuit 37 outputs a pulse train according to the pitch cycle data of the register 36 and applies it to the digital filter section 19.

The conversion output of the conversion unit 16 is applied to the addition circuit 38 of the interpolation unit 17, and the difference with the filter coefficient of the previous frame is output, and the difference value calculation timing pulse t is output.
3 is set in the difference value register 41, and its contents are divided into sample periods by the 1/2 ⁿ circuit 42. Therefore, the difference between the coefficients input from the converter 16 and the coefficients of the previous frame is calculated for each frame period by the adder circuit 38, and this difference is calculated by 1/2 ⁿ circuits based on the number of samples in one frame. divided,
A value for each sample is obtained, and this value is added to the contents of the interpolated value register 44 in an adder circuit 45 to obtain 1.
The filter coefficients for each sample will be output.

The detection and control circuit 35 is a data load pulse
Count the DL, e.g. 6 per frame period.
It is determined based on the timing pulse t4 whether or not a byte of audio data has been read. If the count value is insufficient, it means that the audio data is insufficient, so each of the detection and control circuits 35 Set the output to “1”. Therefore, inhibit gate 31,
32, 33, and 43 are closed, the data buffer stack 11 is read, and the register 36 of the sound source section 18 is closed.
update and interpolation operations are stopped. As a result, voice synthesis using the missing data is not performed, and instead, the same sound based on the voice data of the previous frame is output.

Figure 4 is a block diagram of the main parts of the detection and control circuit, CNT is a 3-bit binary counter, FF
1, FF2 are positive edge trigger flip-flops, G1 to G5 are gate circuits, data load pulse is, SR is system reset signal,
M1 and M2 are operating signals that become "1" when the speech synthesis section is in operation, DT is a detection timing signal, SP is a sample clock, CLK is a basic clock, is a request signal, is an alarm signal, and RS is a signal shown in Figure 3. The output signal RT input to each inhibit circuit 31, 32, 33, 43 is a timing signal that activates the request signal.

Since the operating signal M1 is normally "1", when the system reset signal SR becomes "0",
The counter CNT, flip-flop FF1, and timing circuit T are reset, and the flip-flop
FF2 is set. Thereby the request signal
REQ becomes "0" and the alarm signal becomes "1". This is a state where the synthesis operation is stopped, and DT, SP,
Since timing pulses such as CLK are not generated, flip-flop FF2 and timing circuit T do not operate.

During the synthesis operation, timing pulses such as DT, SP, and CLK are generated, and the operation is as follows.

When the data load pulse is counted by the counter CNT and 5 bytes of audio data are read, the count becomes "101", and the 6th byte data load pulse causes the gate circuit G1 to
output becomes “0” and counter CNT becomes “000”
and flip-flop FF2 is reset. Further, the flip-flop FF1 is set when the output of the gate circuit G2 becomes "1", the request signal becomes "1", and the request for audio data is completed. During speech synthesis operation, the operating signal M1 is "1" and various timing signals are also generated, so the timing signal after a predetermined time
The flip-flop FF1 is reset by RT, and the request signal becomes "0" and the next audio data is requested. Further, an enable signal EN is inputted to the counter CNT so that the counter CNT counts only when an audio data request is issued.

If the flip-flop FF1 is in the set state when the detection timing signal DT becomes "1", the flip-flop FF2 is set and the alarm signal becomes "0", indicating an abnormal state. In other words, if the count value of the data load pulse is insufficient, the flip-flop FF
1 remains reset, so the request signal becomes “0” and even though data is requested,
This indicates that audio data has not been received and is insufficient.

By setting the flip-flop FF2, the timing circuit T outputs an output signal RS of "1" at an appropriate timing, the aforementioned inhibit gates 31 to 33, and 43 are closed, and the conversion operation and interpolation operation are stopped. , the audio is synthesized using the audio data of the previous frame, thereby preventing the synthesis of abnormal audio.

After that, when the count value of the counter CNT reaches a predetermined value, the output of the gate circuit G1 becomes "0" and the flip-flop FF2 is reset, thereby the alarm signal is restored to "1".
Timing circuit T by sample clock SP
is set and the output signal RS becomes "0" again, so a new frame period is set and the aforementioned inhibit gates 31-33, 43 are opened to restart the speech synthesis operation.

Figure 5 is an explanatory diagram of the operation, and the frame pulse
After the FP, the request signal becomes "0" and the audio data is read by the data load pulse as described above, but the next frame pulse
If the predetermined number of bytes of audio data are not read by FP, the count value of counter CNT will not reach the predetermined value as described above, and an alarm signal will be sent.
ALM becomes “0”. As a result, the frame pulse FP indicated by the dotted line is not output.

Also, in period T1 of synthesis operation M, conversion of audio data #m and difference calculation between data #m-1 and #m are performed, and in the next period T2, this difference value is used. Interpolation and filter operations are performed. During the period T3 in which the alarm signal becomes "0", a filter operation is performed using the immediately preceding interpolation value, and no conversion, difference calculation, or interpolation operation is performed. The filter operation can be performed at any time in units of sample periods.

When audio data DATA #m+1 is read,
As described above, the count value of the counter CNT becomes a predetermined value, the alarm signal becomes "1", and the request signal also becomes "1". After the next frame pulse FP, the request signal becomes "0" and audio data DAT #m+2 is read. In the period T4 of the synthesis operation M, the final step of interpolating the data #m-1 to #m, the conversion of the data #m+1, and the calculation of the difference between the data #m and #m+1 and the filter operation are performed. It will be done.
Then, in the next period T5, from #m to #m+
1 data interpolation and filter operation are performed,
From then on, normal compositing operation will occur.

As mentioned above, when the audio data is insufficient, the conversion operation is stopped and synthesized audio based on the audio data of the previous frame is output, so that abnormal audio will not be synthesized. Also, by intentionally leaving the audio data in a state of shortage, new synthesis will be stopped until the audio data is complete.
The speed of speech synthesis becomes slow, and therefore it is also possible to realize speech synthesis with an arbitrary frame period.

In addition, although the above embodiment mainly describes the LSP method, it can also be applied to the PARCOR method, LPC method, etc., and as audio data,
It is also possible to use the analysis results of relatively long words or sentences, or the analysis results of speech pieces used in the VCV method of combinations of vowels V and consonants C, etc.

As explained above, the present invention provides an apparatus that performs speech synthesis by reading a certain number of bytes of audio data every specific period such as a designated frame period. a detection means for detecting a shortage using a counter CNT or the like;
Means for stopping the conversion operation by stopping reading from the data buffer stack 11 when a shortage of audio data is detected, and holding the interpolation result of the immediately previous audio data when the conversion of audio data is stopped. and a means for restarting the conversion operation when the audio data is collected after the shortage of audio data is detected, and stops the audio synthesis using the missing data to prevent abnormal audio from being output. Speech synthesis is performed based on the immediately previous interpolation result, and the result can be made closer to natural speech than when the output of synthesized speech is completely stopped. Moreover, it is also possible to perform speech synthesis at an arbitrary speed by using such a function, and the range of applications can be expanded.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a system that performs speech synthesis under the control of a microprocessor, and FIG. 2 is a block diagram of a speech synthesis circuit according to an embodiment of the present invention.
FIG. 3 is a block diagram of a main part of an embodiment of the present invention, FIG. 4 is a block diagram of a main part of a detection and control circuit according to an embodiment of the present invention, and FIG. 5 is an operation explanatory diagram. 1 is a microprocessor, 2 is a memory, 3 is a speech synthesis circuit, 11 is a data buffer stack, 1
2 is an interface section, 13 is a control register, 14 is a stator register, 15 is a speech synthesis section, 16 is a conversion section, 17 is an interpolation section, 18 is a sound source section, 19 is a digital filter section, 20 is a DA converter, 21 is a control unit, 35 is a detection and control circuit,
36 is a register, 37 is a sound source generation circuit, 41 is a difference value register, 44 is an interpolation value register, and CNT is a counter.

Claims (1)

[Claims] 1. In a speech synthesis device that reads speech data and synthesizes speech by converting, interpolating, and calculating the speech data, detection detects a shortage of speech data at the time of converting the speech data. means, stopping means for stopping the conversion of the audio data when a shortage of audio data is detected; holding means for holding the interpolation result of the immediately preceding audio data when the conversion of the audio data is stopped; and audio data. and restarting means for restarting the audio data conversion operation when the audio data is collected after detecting a shortage of the audio data, and when the audio data shortage is detected by the detection means, the audio data conversion operation is restarted by the stopping means. A speech synthesis device characterized in that the speech synthesis device performs speech synthesis using the interpolation and holding result of the immediately preceding speech data held by the holding means.