JPH02254759A - Thin film semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent an OFF-current from increasing at irradiation with back light by a method wherein the part of a semiconductor layer other than a channel section is crystallized into a crystalline region, and an optical shielding layer is provided to an interface between a gate insulating layer and the crystallized region. CONSTITUTION:A semiconductor layer 14 is composed of an amorphous silicon region 30 and a crystalline region 31, where the crystalline region 31 is, at least, formed on the part other than a channel section 35 and moreover an optical shielding layer 34 is formed on an interface between a gate insulating layer 13 and the crystallized region 31. Therefore, the part other than the channel section 35 is not only crystallized but also shielded from light, so that the part of the semiconductor layer 14 other than the channel section 35 becomes low in sensitivity to a shaded and a visible ray to restrain optical carriers from occurring. By this setup, an OFF-current can be made small at irradiation with back light.

Description

DETAILED DESCRIPTION OF THE INVENTION 1 Tomogami Nigorigoka I The present invention relates to a thin film semiconductor device such as a flat panel display that employs an active matrix drive method and a method for manufacturing the same, and more specifically, an address line and a method for manufacturing the same. A gate insulating layer, a semiconductor layer, The present invention relates to a thin film semiconductor device in which ohmic contact layers are sequentially laminated and a method for manufacturing the same.

1. In recent years, with the advancement of information technology, there has been a desire for display elements, especially color display elements, to have even higher definition and brightness.

Currently, CRT (Cat
Although cathode ray tube (hode ray tube) displays are the mainstream, there is an increasing demand for flat panel displays that are smaller, lighter, consume less power, and can provide higher image quality.

Amid this growing demand, thin film transistors (Thin film transistors) using amorphous silicon as switching elements have been developed.
n Filn+ Transistor; T F
T ) type flat panel displays are considered promising because they can be made to have a large area and can be manufactured at low cost, and many studies have been conducted on them. In other words, the characteristics of a TPT type flat flat panel display using amorphous silicon are that it can be made into a large area, and that it can be manufactured using a relatively low-temperature process (around 300 degrees Celsius), so an inexpensive glass substrate can be used. , continuous film formation maintains the cleanliness of the film interface.

Of the flat panel displays, the Liquid Crystal Display (Liquid Crystal) uses liquid crystal.
1Display (LCD) is currently the most widely used display with a high future potential.

As driving methods for this LCD, there are a simple matrix driving method and an active matrix driving method. Of these, the active matrix driving method is a method in which a switch element is provided for each pixel to drive and control each pixel independently. Therefore, in principle, each pixel can be driven with a density ratio close to 100%, and the contrast ratio of each pixel can be increased.

For these reasons, TFT-type thin film semiconductor devices that adopt an active matrix drive method as a drive method and use amorphous silicon as a switch element are expected to develop as semiconductor devices for new media in the future.

Next, FIG. 9 shows the structure of a TPT in a conventional thin film semiconductor device of this type.

A gate electrode 52 is patterned on the upper surface of the glass substrate 51, and a gate insulating layer 53 is laminated on the upper surface of the gate electrode 52.

Furthermore, a semiconductor layer 54 made of amorphous silicon is laminated on the upper surface of this gate insulating layer 53, and an ohmic contact layer is formed on the upper surface of this semiconductor layer 54.
0 amorphous silicon layers 55 are stacked.

A drain electrode 56 is laminated on the upper surface of this n0 amorphous silicon layer 55.
A source electrode 57 is formed at a predetermined location on the gate electrode 52, facing in the horizontal direction of the gate electrode 6 and sandwiching a channel portion 59 therebetween. Both the drain electrode 56 and the source electrode 57 are made of high melting point metal layers 56a, 57a such as chromium and A12.
It has a laminated structure with layers 56b and 57b. Further, a protective film 58 is provided between the drain electrode 56 and the source electrode 57.
is formed. Here, the n amorphous silicon layer 55 quickly transports electrons induced in the channel portion 59 to the source electrode 57 or the drain electrode 56, and the flow of holes accumulated in the channel portion 59 (off current). It has the function of blocking leakage current and reducing leakage current.

The amorphous silicon that constitutes the semiconductor layer 54 is a good photoconductor for visible light, and in an LCD, backlight is irradiated onto the TFT from the direction of arrow X to display characters or images. It is displayed and displayed.

However, when the semiconductor layer 54 is irradiated with this backlight, electrons in the portion of the semiconductor layer 54 that is not shielded by the gate electrode 52 are excited, photocarriers are generated, and a current (photocurrent) is generated.
flows. Therefore, the drain current (off current) when the gate voltage is 0 or negative increases, and the off current was 10-"A to 10-"A when not illuminated by the backlight, but when exposed to the backlight Sometimes it rises to about 101A to 10-'A. If the off-state current increases when the gate voltage is 0 or negative, the on-off ratio of the TPT decreases, and the LCD
This results in deterioration of display characteristics.

In other words, in a TFTLCD that uses amorphous silicon as the semiconductor layer 54, characters or images are displayed by applying a charge to the liquid crystal layer for a certain period of time, but if the off-state current is large, this may become a leakage current. As a result, it becomes impossible to hold the signal charges accumulated in the liquid crystal layer, resulting in a significant decrease in contrast ratio and image stability. Therefore, in order to obtain good display characteristics with a high contrast ratio, it is important to create an amorphous silicon TPT with stable characteristics and low off-current due to photocarriers during backlight irradiation.

As a measure to reduce the above-mentioned increase in off-state current, there are measures to reduce the generated photocurrent by providing a light shielding layer on the surface of the gate insulating layer 53 or by reducing the thickness of the semiconductor layer 54 made of amorphous silicon. .

However, if a light shielding layer is provided on the surface of the gate insulating layer 53, the number of processes will increase, which may lead to a decrease in product yield.In addition, if the thickness of the semiconductor layer 54 is made thin, the photocurrent will decrease. However, the off-state current does not necessarily fall to the desired current value, and neither of these methods provides a fundamental solution.

The present invention has been made in view of these problems, and provides a thin film semiconductor device equipped with a TPT that reduces the increase in off-state current during backlight irradiation, and a method for manufacturing the same, without reducing productivity. is intended to provide.

In order to achieve the above object, the present invention comprises an address line, a data line arranged orthogonally to the address line, a thin film semiconductor element, and a pixel, and the thin film semiconductor element is configured. In a thin film semiconductor device in which a gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially stacked between a gate electrode, a drain electrode, and a source electrode, the semiconductor layer includes an amorphous silicon region and a crystallized region. and the crystallized region is formed in a portion other than the channel portion, and further, a light shielding layer mainly made of metal is formed at the interface between the gate insulating layer and the crystallized region. It is said that

TP whose semiconductor layer is composed only of amorphous silicon
When T was irradiated with backlight and the characteristics of the off-current based on the generation of photocarriers were measured, the off-current during light irradiation was found to be different from the opposite part between the gate electrode and the drain electrode or the opposite part between the gate electrode and the source electrode. It was found that it increases in proportion to the overlap width. That is, photocarriers are mainly generated within the amorphous silicon semiconductor layer located between the opposing portion of the gate electrode and the drain electrode or between the opposing portion of the gate electrode and the source electrode, and are generated between the drain electrode and the source electrode. It drifts due to the electric field.
It is thought that the off-state current increases. In other words, it is thought that as a result of direct irradiation of the backlight onto a portion of the semiconductor layer that does not face the gate electrode, photocarriers are likely to be generated in this portion.

Furthermore, since light has wave properties, it exhibits a diffraction phenomenon.

Therefore, in a plan view, light is also irradiated to portions near both ends of the gate electrode where the gate electrode and the drain electrode and the gate electrode and the source electrode overlap, which causes an increase in off-state current.

Therefore, the present invention includes crystallizing at least a portion of the semiconductor layer excluding the channel portion to form a crystallized region, and forming a light shielding layer at the interface between the gate insulating layer and the crystallized region, This is aimed at reducing the generation of optical carriers during light irradiation.

Further, the method for manufacturing a thin film semiconductor device according to the present invention includes a step of forming an amorphous silicon layer on a surface of a gate insulating layer, a step of forming a metal film on a surface of the amorphous silicon layer, and a step of forming a metal film on at least a channel portion. The method is characterized in that it includes a step of removing the metal film and the amorphous silicon layer, and a step of forming a crystallized region and a light shielding layer by causing a solid phase diffusion skin reaction between the metal film and the amorphous silicon layer.

When an Al2 film with a thickness of 400 to 500 layers is formed on the surface of an amorphous silicon layer with a thickness of 1000 layers using a vacuum evaporation method, and then annealing is performed at a temperature of 250°C for 10 minutes in a N2 atmosphere, the result is annealing at a low temperature. Despite the treatment, as is clear from the laser Raman spectrum shown in FIG. 7, it was found that a sharp peak appeared in the spectrum near a wave number of 520 cm-'.

On the other hand, when the semiconductor layer is made of only amorphous silicon, it has been confirmed that a wide spectrum characteristic unique to amorphous material appears, which has a peak in the vicinity of a wave number of 480c+a-'. In other words, it is considered that as a result of the annealing treatment, the intermolecular bond strength increases and the amorphous silicon layer is crystallized into almost a polycrystalline state.

In addition, after forming an amorphous silicon layer on the surface of a SiN film that is normally used as a gate insulating layer, Aβ is deposited on the surface of the amorphous silicon layer, and then a solid phase is formed between the amorphous silicon layer and Al1 by thermal annealing. Diffusion reaction was performed for 10 minutes, and SIMS (Second
ary Ion Mass Spectrum) was measured. FIG. 8 is a characteristic diagram showing the SIMS profile, in which the horizontal axis shows the sputtering time (+5 inches) and the vertical axis shows the intensity (1!L)/5ect. still,
The annealing temperature was 250°C. This SIMS is
This is an analysis of electrons ejected by irradiating a sample with ions of molecules such as Ox, Ns, and Cs, and there is a substantially proportional relationship between sputtering time and film thickness depth.

Therefore, as is clear from this SIMS profile, it has been found that the strength of Al1 is maximum near the interface between the crystallized region (crystallized region) and the SiN film (indicated by X in the figure). In other words, Aβ on the surface of the amorphous silicon layer diffuses into the amorphous silicon layer, /l is deposited on the surface of the SiN film, and the crystallized region and 5
It is considered that the A2 layer is interposed at the interface with iNll. This A12 layer has the effect of blocking light.

Therefore, the present invention causes a solid-phase diffusion reaction between the amorphous silicon layer formed on the surface of the gate insulating layer and the metal, and selectively crystallizes the amorphous silicon layer, thereby forming a crystallized region and a light shielding layer. The aim is to manufacture these efficiently.

Hereinafter, a thin film semiconductor device and a method for manufacturing the same according to the present invention will be described in detail.

FIG. 2 is a plan view of a main part of an active matrix drive type thin film semiconductor device. The main parts are an address line 4 for transmitting, a data line 2 for transmitting a signal to the drain electrode 16, and a pixel 3 connected to the source electrode 17, and these are arranged in a matrix on the surface of the glass substrate 11 as one set. It is arranged. Also, TFTl is connected to this address line 4 and data line 2.
The address line 4 is provided near the intersection with the address line 4, and the address line 4 also serves as the gate electrode 12.

Next, the structure of the thin film semiconductor device will be explained in detail with reference to FIGS. 1 and 3. Figure 1 is A- in Figure 2.
A sectional view is shown, and FIG. 3 is a BB sectional view taken in FIG. 2.

Address lines 4 which also serve as gate electrodes 12 are patterned on the upper surface of the glass substrate 11 . This gate electrode 12 is composed of a Cr, Mo, Ta, Aβ, or NiCr film, or a laminated film of these films. The thickness of the gate electrode 12 is determined by the material of the pus, the structure of the target TPT, the wiring resistance, etc. In the present invention, the thickness of the gate electrode 12 is 300 to 3000, more preferably 500 to 1.
The number will be determined within the range of 500 people.

A gate insulating layer 13 is laminated on the upper surface of the gate electrode 12 . As the gate insulating layer 13, a thin film having a high specific resistance, excellent insulation properties, high breakdown voltage, and good interface characteristics is used. In the present invention, as the gate insulating layer 13 satisfying such conditions, SiN film, SiO film, 5
iON film, Ta1on film produced by other forming methods such as sputtering, Aβ20. film,
Alternatively, a laminated film of these may be used. Gate insulating layer 1
When using a SiN film as 3, silicon-based gas, such as 5iH4 and NH, any mixed gas, or 5IH4
and N2, or by decomposing a mixed gas of S I H4, NH, and N2 by plasma CVD, and depositing SiN on the glass substrate 11. When forming a SiN film, the substrate temperature has a large effect on the film characteristics, and the substrate temperature is usually 250°C.
As mentioned above, the temperature is more preferably 300° C. or higher, and the thickness of the gate insulating layer 13 in the present invention is as follows:
It is determined to obtain the desired TPT characteristics, and is usually 5
00 to 5000 people is desirable, more preferably 100 people
The range is from 0 to 3000 people.

On the upper surface of the gate insulating layer 13, a semiconductor layer 14 having a rectangular shape in a plan view and a pixel 3 having a square shape in a plan view are laminated.

The pixel 3 is composed of a transparent electrode. The transparent electrode is an ITO film (Sn
For a 0 pixel 3 wA storage using a Nesa film (a mixture of ow and In), a Nesa film (SnO = ), etc., the range is preferably 500 to 2,000, more preferably 1,000 to 1,500.

Further, the semiconductor layer 14 includes an amorphous silicon region 30 and a crystallized region 31. The crystallized region 31 is formed up to a portion overlapping with the gate electrode 12 in a plan view, and is configured so that the amorphous silicon region 30 is not irradiated with light even if a light diffraction phenomenon occurs. That is, the semiconductor layer 14 has an amorphous silicon region 30 at least below the channel portion 35 formed between the drain electrode 16 and the source electrode 17, and crystallized regions 31 on both sides of the amorphous silicon region 30.
It is said that This crystallized region 31 is for reducing the off-state current generated by photocurrent, and is preferably formed in all parts except the channel part 35. It is better not to form crystallized regions where
Crystallization facilitates electrical contact between the address line 4 and the data line 2, and the gate insulating layer 13
This is because if a pinhole occurs in the circuit, there is a risk of a short circuit.

Therefore, the crystallized region 31 is a portion excluding the intersection of the address line 4 and the data line 2 (see FIG.
It is most preferable to form it in the shaded area C). Also,
This crystallized region 31 is made of polycrystalline silicon, microcrystalline silicon, or the like.

The thickness of the semiconductor layer 14 depends largely on the off-state current of the TFTl and the photocurrent during light irradiation. In the present invention, the thickness is usually 200.
~4000 people are employed, more preferably ~500 people.
The number is in the range of 3,000 people.

The film forming temperature is 100℃~ to obtain good film properties.
Desirably 400°C, more preferably 200°C to 300°C
℃ range.

A light shielding layer 34 mainly made of a metal such as A is formed at the interface between the crystallized region 31 and the gate insulator 113. The light shielding layer 34 is formed substantially simultaneously with the formation of the crystallized region 31 by a solid-phase diffusion reaction occurring between amorphous silicon and metal, as will be described later.

Note that by further performing hydrogen annealing treatment after this, transistor characteristics such as crystallinity such as grain boundary characteristics and field effect mobility can be improved. This hydrogen annealing treatment is performed by placing the sample in a heat treatment furnace, for example, and the annealing temperature is preferably performed at a temperature that does not exceed the film formation temperature of amorphous silicon. Further, as another method of the hydrogen annealing treatment, the sample may be set in a plasma CVD apparatus, and hydrogen gas may be introduced to generate plasma. According to this method, the n amorphous silicon layer 15 can be formed in the plasma apparatus after the hydrogen annealing treatment, so that the manufacturing process time can be shortened.

Thus, an n0 amorphous silicon layer 15 is laminated on the upper surface of the semiconductor layer 14 as an ohmic contact layer. This n0 amorphous silicon layer 15 is formed for the purpose of facilitating the movement of electrons, which are carriers, and blocking the flow of holes, and is mainly formed of a silicon-based gas, for example, a mixed gas of SiH4 and PH8. As for the electrical characteristics of the a n'' amorphous silicon layer 15, the dark specific resistance is 10'Ω·am to 10Ω·
It is desirable that it is am, more preferably 10'Ω・
The range is from cm to 102Ω·cm. Furthermore, the activation energy is preferably 0.4 eV to 1,000 leV, more preferably 0.3. It is in the range of eV to 0.2 eV. n
The film thickness of the amorphous silicon layer 15 needs to be determined to be an appropriate thickness in order to prevent film peeling, etc., but it is usually 1.
00 to 1000 people is desirable, more preferably 100 people
The range is from A to 500A.

Further, on the upper surface of the n0 amorphous silicon layer 15, a drain electrode 1 whose one end is connected to the gate insulating layer 13 is provided.
6 and a source electrode 17 whose one end is connected to the pixel 3.
They are formed to face each other with the channel portion 35 in between.

The drain electrode 16 and the source electrode 17 are usually made of Cr, M
o, high melting point metal layers 16a, 17a, 17c such as Ti and A
Stabilization of characteristics is achieved by forming a laminated structure with J2 layers 16b and 17b. High melting point metal layer 16a, 1
The film thickness of 7a and 17c is 10% considering the peeling of the film etc.
The range is preferably 0 to 1000 people, more preferably 100 to 500 people. Also, AI2 layer 16b
, the thickness of 17b is preferably about 2,000 to 2 μm, more preferably 5,000 to 1.5 μm.
is within the range of

A protective film 18 is formed on the channel portion 35 . This protection layer 118 is formed for the purpose of preventing deterioration of the TPT due to moisture or contamination in the channel portion 35, and is typically made of a SiN film or the like formed by plasma CVD, similar to the gate insulating layer 13. Also, the film thickness is 5
The range is preferably from 00 to 5,000 people, more preferably from 1,000 to 3,000 people.

Note that by further performing hydrogen annealing treatment in a heat treatment furnace after this, it is possible to improve the adhesion between the eyebrows and improve transistor characteristics such as field effect mobility.

Next, a method for manufacturing a thin film semiconductor device according to the present invention will be explained based on FIG.

■ Patterning the address line 4 which also serves as the gate electrode 12 made of Cr on the glass substrate ll (FIG. 1(a))
.

■ After sequentially forming a gate insulating layer 13 made of SiN or the like, an amorphous silicon layer 32, and a protective film 18 made of SiN or the like to a predetermined thickness using the plasma CVD method, a photoresist 21a is applied to the surface of the protective layer 11JI18. (Figure (b)).

■Protective film 18 in the area corresponding to the shaded area C in Figure 2
is removed using a well-known photo-etching technique (FIG. 4(c)).

■With the photoresist 21a left, Aε, Ag,
A metal film 20 is formed by depositing a metal such as Sn or In on the entire surface of the sample using a resistance heating method. The film thickness of the metal 1120 is determined to be 100 or more, taking into account the solid phase diffusion reaction treatment described below.
1000 people is desirable, more preferably 100 to 50 people
The number is in the range of 0 ((d) in the same figure).

(2) A portion of the metal film 20 other than the portion where the protection m1B has been removed (the 0 portion) is removed together with the photoresist 21a by a lift-off method (FIG. 2(e)).

Next, a solid phase diffusion reaction is caused between the amorphous silicon layer 32 and the metal film 20 to form a crystallized region 31 and a light shielding layer 34.

Although electron beam annealing and laser beam annealing can be used to carry out the solid-phase diffusion reaction, thermal annealing is preferred in order to easily and quickly form crystallized regions on large-area substrates. It is preferable to do so. That is, heat treatment is performed using this thermal annealing method to cause a solid phase diffusion reaction between the contact surfaces of the amorphous silicon layer 32 and the metal film 20, and the metal forming the metal film 20 is diffused into the amorphous silicon layer 32. The crystallized region 31 is formed by crystallization. Further, the metal constituting the metal film 20 is diffused toward the gate insulating layer 13 side by this solid phase diffusion reaction, and a light mainly made of the metal is diffused to the interface between the gate insulating layer 13 and the crystallized region 31. The annealing temperature for forming the shielding layer 34 cannot exceed the substrate temperature for forming the amorphous silicon layer 32 in a plasma CVD apparatus, but if the substrate temperature is 300°C,
℃~300℃, more preferably 200℃12
The temperature range is 80°C. Further, the annealing time is desirably 5 to 30 minutes, more preferably 10 to 20 minutes.

After this annealing treatment, the metal film 20 remaining on the surface is removed by cleaning with chemicals (FIG. 2(f)).

■Next, apply photoresist 21b to the sample surface (
Figure (g)).

(2) The protective pus 18 other than the channel portion 35 formed between the drain electrode 16 and the source 1 and the pole 17 is removed by using the photo-etching technique (FIG. 1(h)).

■With the photoresist 21b remaining, 0 is applied to the sample surface.
A high melting point metal layer 16a (17a) such as 0 amorphous silicon 115 and Cr is formed (FIG. 1(i)).

[Phase] The n'' amorphous silicon layer 15 and the high melting point metal layer 16a (17a) on the protection 11118 are removed together with the photoresist 21b by a lift-off method (FIG. 6(j)).

(2) Thereafter, the semiconductor layer 14, the amorphous silicon layer 15, and the high melting point metal layers 16a and 17a having a predetermined shape are formed again using the well-known photoetching technique. (
Figure (k)).

Next, by sputtering method, Snow or Sn
After forming a pixel 3 by depositing a mixture of ow and In on the surface of the gate insulating layer 13, appropriate photoetching is performed to form a high melting point metal layer 17c at one end of the pixel 3 (as shown in the figure). (β)).

(2) Finally, Aβ is deposited on the surface of the sample, and the photoetching process is performed again to form a drain electrode 16, a source electrode 17, and a data line (FIG. 3(m)).

A thin film semiconductor device can be manufactured by the above method. Furthermore, as mentioned above, hydrogen annealing treatment may be performed between the step (1) and the step (2).Furthermore, after the step [phase] is completed, hydrogen annealing treatment may be performed to improve transistor characteristics, etc. You can also do that.

2. According to the thin film semiconductor device according to the present invention, the semiconductor layer includes an amorphous silicon region and a crystallized region, and the crystallized region is formed at least in a portion excluding a channel portion, and further includes a gate insulating layer and a crystallized region. Since a light shielding layer is formed at the interface with the crystallized region, at least the portion excluding the channel portion is crystallized and light is shielded. Therefore, the portion of the semiconductor layer other than the channel portion is shielded from light and has low sensitivity to visible light, and together with this, the generation of photocarriers is suppressed.

Furthermore, in the manufacturing process of the thin film semiconductor device, an amorphous silicon layer is formed on the surface of the gate insulating layer, and a metal film is formed on the amorphous silicon layer at least on a portion other than the channel portion. A solid phase diffusion reaction is caused between the amorphous silicon layer and the metal film, and the metal is diffused into the amorphous silicon layer to form the crystallized region and the light shielding layer. can be formed efficiently.

1 standing Examples according to the present invention will be described below.

In addition, the code of the component parts is "means to solve the problem"
The same reference numerals as those used in Figures 1-
See Figure 4].

A film with a thickness of 10 mm was applied to a thoroughly cleaned 5 inch square glass substrate 11.
000 Cr was vapor deposited, and then a pattern of address lines 4 which also served as gate electrodes 12 was formed by photo-etching. Channel length as TPT is 8μr
ri and channel width W of 200 μm.

Thereafter, the glass substrate 11 was set in a plasma CVD apparatus, and while the inside of the vacuum container was evacuated, the glass substrate 11 was heated, and the heating temperature was set at 300°C. When the degree of vacuum inside the vacuum container became less than 1 O''' Torr, the exhaust system was switched from the diffusion pump (DP) to the mechanical booster pump (MBP), and 100% SiH4 was pumped through the mass flow controller (MFC) at 8 SCC.
M, NHs 40SCCM, N□ 80SCCM
The reaction pressure was adjusted to 0.5 Torr. 13.56M when the pressure becomes constant
Set the radio frequency (RF) power of H1 to an output of 50W and
The voltage was applied for a minute to form a gate insulating layer 13 of SiN. The formed gate insulating layer 13 has a refractive index of 1.82 and an optical band gap Eg of 5.82. leV and relative dielectric constant were 6.1. The film thickness was 3000 people.

Next, in the plasma CVD apparatus, an amorphous silicon layer 3 with a thickness of 1000 nm is formed on the SiN gate insulating layer 13.
2 was formed. What are the formation conditions? 00%S i H4 l0
3C (:M flow), reaction pressure was set to 0.2 Torr, and radio frequency (RF) power output was set to 100 W. The film forming time was 8 minutes. The formed amorphous silicon layer 32 As electrical characteristics, dark specific resistance ρd=2X10I0Ω・cm, activation energy Ea
= 0.7 eV, and as an optical characteristic, the optical band gap Eg = 1.75 eV.

Next, in the plasma CVD apparatus, a protective film 18 made of SiN and having a thickness of 1500 nm was deposited on the amorphous silicon layer 32. The film forming conditions were the same as those for the SiN gate insulating layer 13, and the film forming time was 10 minutes.

After forming the protective film 18, the sample is taken out, and the portion of the protective film 18 corresponding to the shaded area C in FIG. 2 is removed using a well-known photoetching technique.

Thereafter, the sample was placed in a vacuum evaporation apparatus with the photoresist 21a remaining, and Af2 was evaporated by the resistance heating method when the degree of vacuum was less than IXIO-''Torr. there were.

Next, a portion of the A2 adhering to the sample surface is removed together with the photoresist 21a by a lift-off method.

After this, the sample was set in a heat treatment furnace, and N2 was heated at if2/m
The Aε remaining on the surface of the film was annealed at 250° C. for 15 minutes using hot phosphoric acid and washed. Note that the formation of the crystallized region 31 and the light shielding layer 34 is completed at this stage. Here, after the solid-phase diffusion reaction was completed, the hydrogen content in the crystallized region 31 was separately measured by FT-IR, and the hydrogen content was 1%.

Next, after applying photoresist 21b to the sample surface,
The protective film 18 other than the channel portion 35 formed between the drain electrode 16 and the source electrode 17 is removed.

After that, set the sample in the plasma CVD apparatus again,
An amorphous silicon layer 15 was formed. The formation conditions were a substrate temperature of 120°C, 100% SiH4
SCCM11%H8 based PH1 IO3ccM
The reaction pressure was 0.2 Torr, and high frequency (
RF) power was applied with the output set to 100 W, and film formation was performed for 4 minutes. The thickness of the formed n1 amorphous silicon layer 15 was 500 mm. The characteristics of this n4 amorphous silicon layer 15 were determined from a separate experiment: dark specific resistance pci=5ooΩ・cm, activation energy Ea=O
The optical bandgap Eg was 12 eV, and the optical band gap Eg was 1.7 eV.

Next, the sample was set in a vacuum evaporation apparatus, and Cr was heated in a tungsten boat to form a 300-layer Cr layer (high melting point metal layer 16a (17a)) on the sample surface.

Next, the Cr layer of the channel portion 35 and the amorphous silicon layer 15 are removed using the photoresist 2 by a lift-off method.
It was removed along with 1b.

After that, photoetching is performed to form the semiconductor layer 14 into a predetermined shape.
, an n0 amorphous silicon layer 15, and a Cr layer (high melting point metal layers 16a and 17a).

Next, the glass substrate 11 was again set in the vacuum deposition apparatus, and a mixture of SnO□ and In was deposited on the surface of the gate insulating layer 13 by sputtering to form the pixel 3 (transparent electrode). The film thickness of the formed pixel 3 is 100
0 people, and its dimensions are 300 um, x 300
It was g m.

Thereafter, in the same manner as described above, a Cr layer (high melting point metal layer 17C) having a thickness of 300 was formed at the end of the pixel 3 by tungsten boat heating and photoetching.

Thereafter, an A2 layer with a thickness of 1.0 μm was formed over the entire surface of the sample by electron beam evaporation.

Thereafter, the above photoetching process was performed again, and Af2 was removed using a phosphoric acid-based aqueous solution to form a drain electrode 16, a source electrode 17, and a data line 2.

The electrical characteristics of the thin film semiconductor device produced as described above are shown below.

Initial characteristics (without backlight irradiation) Field effect mobility (u): 0.2 cm”/V
・Sea threshold voltage (VT): 3V Drain voltage (Va): IOV On current gate voltage (■, ): 1 x 10°IA when gate voltage (■, ) is 25V 1 x 10''8A when gate voltage (Vg) is 15V Off current gate When the voltage (■, ) is 0■, it is 5×10°"A When the gate voltage (■, ) is -lO■, it is 5X10-"A On current/off current: Approximately 10a Illuminance of the backlight (Lux ) : 20001ux Drain voltage (V, ): IOV When the on-current gate voltage (V, ) is 25V, lXl0-'A When the gate voltage (V, ) is 15V, lXl0-'A Off-current gate voltage cvg) is OV When 5X 10-11A When gate voltage (V, ) is -10V, 1X10''A On current/Off current: Approximately 105~10'Also. ■、−
1.Characteristics are shown in Figure 5.

In this way, the off-state current, which was less than 10" A when the backlight was not illuminated, is at most 10" A even when the backlight is illuminated.
It can be seen that the on-off ratio only increases from 1 to 10-''A, and exhibits good on-off characteristics with an on-off ratio of 10' to 108 even during light irradiation.

The semiconductor layer 14 is not provided with the crystallized region 31 in the comparatively difficult semiconductor layer 14.
The TPT was formed under the same conditions as in the example except that the TPT was made of amorphous silicon.

The electrical characteristics of this comparative example are shown below.

Initial characteristics (without backlight irradiation) Field effect mobility (u): 0.5 cm”/V-
See threshold voltage (■〒): 1. OV Drain voltage (Va): 10V On current: 1 x 10° 4A when gate voltage (Vg) is 25V 7 x 10''IIA when gate voltage (Vg) is 15V Off current: 1 when gate voltage (Vg) is OV ×10°1m A When the gate voltage (■, ) is -10V, 5 Engineering.)-.

On current When the gate voltage (■,) is 25V lXl0-'A When the gate voltage (■1) is 15V lXl0-'A 0V Off current When gate voltage (■1) is 0■ lXl0-'A When the gate voltage (V, ) is -10V 5X10-”A On current/off current: approx. 10' Further, the Va It characteristics are shown in FIG.

As described above, it is observed that the off-state current of the drain current during backlight irradiation increases to about 101 A, and the on-off characteristics are significantly deteriorated.

1Ω emergence As described in detail above, in the thin film semiconductor device according to the present invention, the semiconductor layer that generates a photocurrent when irradiated with backlight is composed of an amorphous silicon region and a crystallized region, and A crystallized region is formed at least in a portion excluding the channel portion, and a light shielding layer mainly made of metal is formed at the interface between the gate insulating layer and the crystallized region. As the portion is crystallized, light is shielded, and generation of carriers in this portion can be suppressed. Therefore, it is possible to obtain a thin film semiconductor device equipped with a TPT having good characteristics with a small off-state current. It was manufactured by forming a metal film on the surface of the amorphous silicon layer located in the part excluding the upper part, and then forming a crystallization region and a light shielding layer by solid phase diffusion reaction, so the crystallization of the amorphous silicon layer The formation of the crystallized region and the light shielding layer can be performed almost simultaneously, and the crystallized region and the light shielding layer can be formed efficiently. , it is suitable for mass production.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 shows a TP provided in a thin film semiconductor device according to the present invention.
A sectional view showing one embodiment of T (A-A sectional view in FIG. 2, FIG. 2 is a partially omitted plan view of the thin film semiconductor device according to the present invention, and FIG. 3 is a BB--B sectional view in FIG. 2) Figure, Figure 4 (
a) to (m) are cross-sectional views showing one embodiment of a method for manufacturing a thin film semiconductor device, and FIG. 5 shows V and -I in the present invention. Figure 6 is a characteristic diagram showing V, -1 in a comparative example, Figure 7 is a characteristic diagram showing the laser Raman spectrum of the thin film semiconductor device of the present invention together with a comparative example, and Figure 8 is a characteristic diagram showing the completion of solid phase diffusion reaction. A characteristic diagram showing the SIMS profile of the sample after
FIG. 9 is a sectional view showing a part of a conventional example. 1... TPT (thin film semiconductor element), 2... Data line, 3... Pixel, 4... Address line, 12
...Gate electrode, 13...Gate insulating layer, 14...
・Semiconductor layer, 15...n''''a''1 morphous silicon 3
2-layer contact layer), IB...drain electrode,
17... Source electrode, 20... Metal film, 30...
Amorphous silicon region, 31...Crystallization region, 3
2... Amorphous silicon layer, 34... Light shielding layer, 35... Channel portion. Patent a applicant: Sumitomo Metal Industries Co., Ltd. Agent:
Patent Attorney Ryuji Iuchi Figure 3 Figure 2 Figure 4 (j) (k) (i) (m) Figure 5 VG (V) Figure 6 Figure 7

Claims (2)

[Claims] (1) A gate electrode comprising an address line, a data line disposed perpendicular to the address line, a thin film semiconductor element, and a pixel, and forming the thin film semiconductor element;
Between the drain electrode and the source electrode, a gate insulating layer,
In a thin film semiconductor device in which a semiconductor layer and an ohmic contact layer are sequentially stacked, the semiconductor layer is composed of an amorphous silicon region and a crystallized region, and the crystallized region is formed at least in a portion excluding a channel portion. A thin film semiconductor device, further comprising a light shielding layer mainly made of metal, formed at an interface between the gate insulating layer and the crystallized region. (2) forming an amorphous silicon layer on the surface of the gate insulating layer; forming a metal film on the surface of the amorphous silicon layer; removing the metal film on at least the channel portion; A method for manufacturing a thin film semiconductor device, comprising: forming a crystallized region and a light shielding layer by causing a solid phase diffusion reaction with a silicon layer.