JPH02192766A - Thin film semiconductor element - Google Patents

Abstract

PURPOSE:To unnecessitate light shielding, reduce the number of photo masks, simplify manufacturing process, and speed up element response by arranging a drain electrode and a source electrode in the vertical direction, and forming a semiconductor layer and an ohmic contact layer. CONSTITUTION:On a glass substrate 31, a drain electrode 32 is patterned; there on an N<+> amorphous silicon layer 33 is formed as an ohmic contact layer; further an amorphous silicon layer 34 is formed as a semiconductor layer; there on an N<+> amorphous silicon layer 35 and a source electrode 36 are formed in sequence; an insulating layer 37 and a gate electrode 38 are formed on the side surface of the lamination layer. The area which this element occupies on the substrate is small, and the semiconductor layer is not irradiated with light, so that photo carrier does not generate. It is not necessary to provide the source and the drain electrodes with a missing part, so that the number of photo mask can be reduced, and the channel length depends upon the film thicknesses of the semiconductor layer and the ohmic contact layer. Thereby the channel length can be shortened.

Description

[Detailed Description of the Invention] The present invention relates to a thin film semiconductor device, more specifically a thin film semiconductor device including a gate electrode, a drain electrode, a source electrode, an insulating layer, a semiconductor layer and an ohmic contact layer. In particular, it relates to a device that is applied to, for example, an active matrix drive type flat panel display.

In recent years, with the advancement of information technology, there has been a demand for higher definition and higher brightness in the field of displays for displaying images. Currently, CRTs (cathode ray tubes) are the mainstream in most household and other fields. However, there is an increasing demand for flat panel displays that are small, lightweight, consume low power, and can provide high image quality. Among flat panel displays, LCDs using liquid crystals are currently the most widely used and promising displays. As driving methods for this LCD, there are a simple matrix driving method and an active matrix driving method. Among these, the active matrix driving method is a method in which a switch element is provided for each pixel to independently drive and control each pixel. Therefore 100 for each pixel
It is possible to drive at a duty ratio close to %, and it is possible to obtain a large pixel contrast ratio.

A thin film transistor (TPT) type switching element using amorphous silicon can be made in a large area and can be manufactured at low cost, so it is viewed as promising and has been studied extensively. Characteristics of thin film transistor (TPT) displays using amorphous silicon include the possibility of large-area displays and the relatively low-temperature process (30
Since it can be manufactured at a temperature of around 0°C, an inexpensive glass substrate can be used, and continuous film formation maintains the cleanliness of the outer surface of the film.

Based on the above, thin film transistor (TPT) type displays employing an active matrix drive method and using amorphous silicon are expected to develop as candidates for future new media displays.

Next, the conventional amorphous silicon thin film semiconductor device (TP
The structure of T) is shown in Figure 4. A gate electrode 12 is patterned on the upper surface of the glass substrate 11 (upper side in FIG. 4), and a gate insulating film 13 is formed on the upper surface of the gate electrode 12.
are formed in layers. Furthermore, an amorphous silicon layer 14 is laminated on the upper surface of this gate insulating film 13.
On the upper surface of this amorphous silicon layer 14, an n" amorphous silicon layer 15 is formed as an ohmic contact layer.
are formed in layers. A drain electrode 16 is further laminated on the upper surface of this n0 amorphous silicon layer 15, and a source electrode 17 is formed at a predetermined location facing the drain electrode 16 in the horizontal direction and sandwiching the gate electrode 12 therebetween. The drain electrode 16 and the source electrode 17 are each a laminate of a Cr layer 18 and an A1 layer 19. Further, a protective film 20 is formed between the drain electrode 16 and the source electrode 17.

When an amorphous silicon TPT is used as the switching element of an LCD, the area occupied by the TPT and the wiring is 20% and 15% of the total substrate area, respectively, and the aperture ratio (the area occupied by the pixel on the substrate) is percentage) is 50% to 60
It will be about %. As the applications for LCDs expand, higher definition and higher image quality are required.
The proportion of the area occupied by wiring and wires further increases, reaching 30% and 25%, respectively, and the aperture ratio ranges from 30% to 4.
It is expected to drop to 0%. If the aperture ratio decreases, the screen will become darker and the image quality will deteriorate. If the brightness of the backlight is increased to maintain screen brightness, power consumption will increase and elements and color filters will deteriorate.

(2) Currently, about eight photomasks are required to manufacture amorphous silicon TPT, but the manufacturing process is long and disadvantageous in terms of yield and cost.

(2) In terms of characteristics, when backlight enters, the off-state current that flows when the TPT is off increases by about four orders of magnitude. Therefore, there is a problem in that the on-off ratio becomes small and the contrast ratio of the display becomes small.

Therefore, in view of the above-mentioned problems, the present invention provides TPT
The object of the present invention is to provide a thin film semiconductor element that occupies a small area, is suitable for high definition, has a simple manufacturing process, is advantageous in terms of yield and cost reduction, and has a reduced increase in off-state current due to backlighting.

f To solve the above problem, the present invention provides a thin film semiconductor device including a gate electrode, a drain electrode, a source electrode, an insulating layer, a semiconductor layer, and an ohmic contact layer, wherein the drain electrode and the source Electrodes are arranged vertically, a semiconductor layer and an ohmic contact layer are formed between the two electrodes, and an insulating layer and a gate electrode are formed on the sides of the laminated layer consisting of the two electrodes, the semiconductor layer, and the ohmic contact layer. This is a characteristic feature.

According to the above-described structure for No. 1, since the drain electrode and the source electrode are arranged in the vertical direction, the area occupied by the stack of thin film semiconductor elements on the glass substrate is reduced. Since the semiconductor layer is sandwiched between the upper and lower drain and source electrodes, no light hits the semiconductor layer and no photocarriers are generated.Also, when manufacturing this thin film semiconductor device, defects are created in the drain and source electrodes. Since this is not necessary, the number of photomasks is reduced. Furthermore, since the channel length is determined by the thickness of the semiconductor layer and the ohmic contact layer, the channel length can be shortened without being subject to photolithography restrictions.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be exemplarily described based on the drawings.

First Embodiment FIG. 1 is a sectional view of a thin film semiconductor element. In the figure, 31 is a glass substrate, a drain electrode 32 is patterned on the glass substrate 31, and an n'' amorphous silicon layer 33 is formed as an ohmic contact layer on top of the drain electrode 32.
3, and an amorphous silicon (a-5i;H) layer 34 containing hydrogen is formed thereon as a semiconductor layer. On this amorphous silicon layer 34, n"
An amorphous silicon layer 35 and a source electrode 36 are formed in this order.

An insulating layer 37 is formed on the side surface of the laminated layer consisting of the drain electrode 32, n0 amorphous silicon layer 33, amorphous silicon layer 34, n1 amorphous silicon layer 35, and source electrode 36, and a gate electrode 38 is further formed on the side surface of the insulating layer 37. It is formed. For example, silicon nitride (SiN), silicon oxide (Sin), or the like is used for the insulating layer 37.

Next, an embodiment of the method for manufacturing the above-mentioned thin film semiconductor device will be described based on FIG. 2.

(2) As the glass substrate 31, for example, Corning 7059 glass with a diameter of 5 inches is used. This glass substrate 3
1 is thoroughly cleaned, Cr is deposited, and wet etching is performed to form a Cr drain electrode 32 with a width of 10 mm.
It is formed to a thickness of μm (FIG. 2(a)). In addition, the drain electrode 3
The film thickness of No. 2 is required to be 800 Å or more because it is necessary to block back light from the glass substrate 31, and is set to 1200 in this embodiment.

■Next, the glass substrate 31 on which the drain electrode 32 is formed
(hereinafter referred to as the sample) using a plasma CVD device (not shown)
The inside of the reaction vessel was evacuated and the sample was heated.The heating temperature was set to 300℃.The oil diffusion pump was connected when the degree of vacuum inside the reaction vessel became 5 X I O-'Torr or less. The pulp being pumped is closed, the exhaust system is switched from the oil diffusion pump (DP) to the mechanical booster pump (MBP), and the mass flow controller (M
FC), 100% monosilane gas (IOSCCM, 10,100pp), and pace phosphine gas (IO3ccM) were introduced into the reaction vessel via a FC), and then the pressure inside the reaction vessel was adjusted to 0.2 Torr by exhausting with MBP.

After 5 minutes had passed since the gas flow rate and the pressure in the reaction vessel were stabilized, RF lightning current was started to flow without adjusting the matching unit to cause glow discharge between the electrodes. RF power 5
The voltage was maintained at 0W and discharged for 3 minutes, and 0W was applied as an ohmic contact layer on the glass substrate 31 and drain electrode 32.
3 amorphous silicon layers 33 were laminated.

■Next, evacuate the inside of the reaction vessel using DP to increase the vacuum level to 5x.
1O-'Torr or less, then switch from DP to MBP, introduce 100% monosilane gas as a raw material gas into the reaction vessel using IOSCCM, and reduce the pressure inside the reaction vessel to 0.
The pressure was adjusted to 2 Torr. Then, 5 minutes after the flow rate became stable, RF power of 150 W was applied and film formation was performed for 10 minutes to form an amorphous silicon layer 34 on the n4 amorphous silicon layer 33.

■After forming the amorphous silicon layer 34, 100%
Monosilane gas was introduced at IO 3 ccM at 10,100 pp, and base phosphine gas was introduced at IO 3 CCM, and the pressure inside the reaction vessel was adjusted to 0.2 Torr. After 5 minutes have passed since the gas flow rate and the pressure inside the reaction vessel have stabilized, R
F power of 50 W was applied and film formation was performed for 3 minutes to form an n1 amorphous silicon layer 35 as an ohmic contact layer on the amorphous silicon layer 34. after that,
After turning off the RF power, stop introducing the raw material gas,
The MBP was fully opened to exhaust the inside of the reaction vessel, and when the glass substrate temperature became 50° C. or less, the MBP was closed to open the reaction vessel to atmospheric pressure, and the sample was taken out.

(2) Next, the sample taken out was placed in a vacuum evaporation apparatus, and 1200 Cr was evaporated using the resistance wire heating method. Furthermore, after patterning was performed using photolithography to form a resist pattern 39 (FIG. 2(b)), a source electrode 36 of a desired pattern was formed by wet etching.

■After removing the above resist pattern 39, apply resist again, and use the drain electrode 32 as a mask.
A resist pattern 40 was formed by irradiating ultraviolet rays from the glass substrate 31 side (FIG. 2(C)). Using this resist pattern 40, the n3 amorphous silicon layer 35,
The amorphous silicon layer 34 and the n-amorphous silicon layer 33 were formed into desired shapes by wet etching. After removing the resist pattern 40, a resist pattern 41 was again formed by photolithography (FIG. 2(d)).

Next, the sample on which the resist pattern 41 was formed was set in a dry etching device at an angle of about 40°, and after evacuating the inside of the reaction vessel to 5×10 Torr, the sample was heated to CL 30
After adjusting the pressure in the reaction vessel into which SCCM, O*1105CC is introduced, to 0.2 Torr, the RF power was adjusted to 15
0W was applied for 20 minutes, and as shown in Figure 2(e), n+
The amorphous silicon layer 35, the amorphous silicon layer 34, and the n'''' amorphous silicon layer 33 were etched in a tapered manner.

■Next, a part of the n0 amorphous silicon layer 35, the amorphous silicon layer 34, and the n+ amorphous silicon layer 33 were removed by photolithography (to form a resist pattern 42 (FIG. 2(f)) and wet etching (see FIG. 2(f)). Figure 2 (g)).

(2) Next, the resist pattern 42 was removed, and then the sample was set in the plasma CVD apparatus again, and the inside of the reaction vessel was evacuated by DP, and the sample was heated to 300° C. to a vacuum degree of 5×10 −7 T.

When it becomes below rr, switch from DP to MBP,
In the reaction vessel, 100% monosilane gas was used as raw material gas, IOSCCM, NH, 40SCCM, Na 60SCCM.
CM was introduced and the pressure inside the reaction vessel was maintained at 0.5 Torr. After 5 minutes had passed since the gas flow rate and the pressure inside the reaction vessel were stabilized in this state, RF power was applied at 50 W for 20 minutes to form an insulating layer 37 (Fig. 2 (h)). After turning off, the introduction of raw material gas was stopped, the MBP was fully opened to exhaust the inside of the reaction vessel, and when the temperature of the glass substrate 31 became 50° C. or lower, the MBP was closed and the sample was taken out.

(2) Next, the sample was placed in a vacuum evaporation apparatus, and 1,200 Cr was evaporated using the resistance wire heating method. After that, a resist pattern 43 is formed by photolithography, as shown in FIG.
)) Using this resist pattern 43, the gate electrode 38 and part of the insulating layer 37 were removed by wet etching (FIG. 2(i)).

A thin film semiconductor element can be manufactured by the above method.

Amorphous silicon TPT created in this way
The characteristics were measured and were as follows.

For each thin film layer, an n+ amorphous silicon layer 33
The film properties of the amorphous silicon layer 34 were as follows: specific resistance was 2 x 10" Ωcm, activation energy was 0.30 e■, and film thickness was 400 mm. The film properties of the amorphous silicon layer 34 were that the specific resistance was 9XIO' Ω・cm, activation energy is 0.72
eV, optical band gap was 1.75 eV, and film thickness was 1200 nm.

The SiNx film characteristics of the insulating layer 37 have a refractive index of 1.9.
5. Film thickness is 2500mm, optical bandgap is 4.2
It was eV.

Regarding the electrical characteristics of the amorphous silicon TFT array, the field effect mobility was 0.15 cm2/■·S, and the on-off ratio was about 4 digits.

In this embodiment, a drain electrode 32 and a source electrode 36 are stacked vertically with n''' amorphous silicon layers 33, 35 and 34 in between, and the area occupied by the amorphous silicon TPT is 10
Small as 00μm2, conventional amorphous silicon TP
T (Fig. 4) was able to be reduced to approximately one-third. Even if the area occupied by the amorphous silicon TPT is small, the channel length (corresponding to the thickness of the amorphous silicon layer 34) can be shortened in this embodiment without being limited by photolithography.
The on-state current was 8XIO-'A, which was a sufficiently large value.

By the way, when making an amorphous silicon TPT finer by photolithography, there is a limit to making the line width thinner, so there is a limit to making the channel length shorter. However, in this embodiment, the amorphous silicon layer 34
Since the channel length can be shortened by making the film thinner, it is not subject to the limitations of photolithography, and the channel length can be significantly shortened compared to photolithography.

In addition, in the conventional amorphous silicon TPT, when the backlight is irradiated, the off-state current increases by about 4 orders of magnitude, so the on-off ratio decreases by about 4 orders of magnitude, but in the amorphous silicon TPT of this embodiment, the amorphous silicon layer 34 Since light was completely shielded by the drain electrode 32, the off-state current did not increase.

Second Embodiment FIG. 3 is a plan view of a thin film semiconductor device according to the present invention, in which amorphous silicon TPT is assembled in a matrix. be. In FIG. 3, 44 is a pixel I
It is a transparent electrode made of TO (oxide of In and Sn). The method of manufacturing the amorphous silicon TPT arranged in a matrix is almost the same as in the first embodiment.

The electrical characteristics of this matrix-like amorphous silicon TPT include a field effect mobility of 0.14 cm2/V・S;
The on-off ratio was about 4 digits.

As mentioned above, the area occupied by the amorphous silicon TPT is about 3 minutes compared to the conventional process.
4 area can be taken larger, and the aperture ratio is 1.
It was increased by about 0% to 20%. Furthermore, since the amorphous silicon layer 34 was completely shielded from light by the drain electrode 32, there was no increase in off-state current even when irradiated with backlight.

Further, the number of photomasks required to assemble the amorphous silicon TPT in a matrix is 6 in this embodiment, which reduces the number of manufacturing steps by about 60% compared to the conventional 8 or 9 required.

As is clear from the above explanation, in the thin film semiconductor device according to the present invention, the drain electrode and the source electrode are arranged in the vertical direction, and the area occupied by the device in the liquid crystal is small, so that it is easy to use in LCD. When used for driving purposes, the aperture ratio can be increased. In addition, since the semiconductor layer is sandwiched between the upper and lower drain and source electrodes and is shielded from light, no photocarriers are generated from the semiconductor layer, so there is no increase in off-state current during backlight irradiation, so there is no need to provide a light shield. . Furthermore, since there are no defects in the drain and source electrodes compared to the conventional method, the number of photomasks used is reduced, the manufacturing process is simplified, and yields are improved and costs reduced. Furthermore, since the channel length is determined by the thickness of the semiconductor layer without being restricted by photolithography, the response time of the element can be shortened by shortening the channel length, and the speed can be increased.

Figure 1 is a sectional view showing an embodiment of a thin film semiconductor device according to the present invention, and Figures 2 (a) to (i) are an embodiment of a method for manufacturing a thin film semiconductor device. FIG. 4 is a cross-sectional view showing the formation of a drain electrode, (b) the formation of an n'' amorphous silicon layer, an amorphous silicon layer, and a source electrode, and (c) the formation of a resist pattern 40 (
d) shows the formation of the resist pattern 41; (e)~
(g) shows the etching of the n''7 amorphous silicon layer, (h) shows the formation of the insulating layer and the gate electrode, and (i) shows the etching of the insulating layer and the gate electrode. FIG. 3 is a plan view of a thin film semiconductor device in which amorphous silicon TPT is assembled in a matrix, and FIG. 4 is a cross-sectional view of a conventional example.

32...Drain electrode, 33.35...n0 amorphous silicon layer (ohmic contact layer), 34.
...Amorphous silicon layer (semiconductor layer), 36...
Source electrode, 37... Insulating layer (gate insulating layer), 38
Gate electrode patent applicant: Sumitomo Metals Co., Ltd. 1 agent:
Patent Attorney Ryuji Iuchi Figure 2 Figure 1 Figure 2 Figure 2

Claims (1)

[Claims] A thin film semiconductor device including a gate electrode, a drain electrode, a source electrode, an insulating layer, a semiconductor layer, and an ohmic contact layer, wherein the drain electrode and the source electrode are arranged vertically, and a semiconductor layer and an ohmic contact layer are provided between the two electrodes. What is claimed is: 1. A thin film semiconductor device comprising: an insulating layer and a gate electrode formed on the side surface of the laminated layer consisting of both electrodes, a semiconductor layer, and an ohmic contact layer.