JPH02254573A - Raster arithmetic unit - Google Patents

Abstract

PURPOSE:To obtain general usefullness to the length and width of a word by inserting a data selector in front of a barrel shifter, arranging plural data selectors in back of the barrel shifter and providing plural function decoders corresponding to the minimum length and width of the word. CONSTITUTION:When a raster arithmetic unit is used with the maximum word length, the value of the word length is set to a word length register 12 and shift quantity, arithmetic class, bit mask data, number of words to be transferred, source data, destination data and pattern data, etc., are set to the other various registers. Then, the raster arithmetic units is operated. In this case of the maximum word length, a data selector 13 outputs data from source registers 10 and 11 to a barrel shifter 15 with maintaining an order as it is and data selectors S1-S4 send data for the maximum length and width of the word from the barrel shifter 15 to function decoders F1-F4. When the unit is used by the 1/2 or 1/4 word length of the maximum word length, the value of the word length is set to the word length register 12 respectively and the unit is used. Thus, the general usefullness to the length and width of the word can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In a raster arithmetic device that performs control TJ of bitmap graph ink.

To solve the problem of a decrease in the processing capacity of a raster arithmetic unit due to a change in the number of bits for simultaneous operation and the difficulty of responding to a change in one word length.

A data selector that sorts the output of the source register according to the word length used is inserted before the barrel shifter, and a plurality of data selectors are placed after the barrel shifter,
and by having a Funk Silane decoder that supports multiple minimum word lengths and widths.

To realize a raster arithmetic device that is versatile with respect to word length and width and has high processing efficiency.

C Industrial application field] The present invention uses bitmap graphics.

Involved in devices that process and control bitmap graphics using sliced pixel (brain type) in display systems.

In particular, the present invention relates to a raster arithmetic device that can flexibly accommodate various word lengths and widths.

(Prior art) Fig. 7 is a diagram for explaining a touch-sensitive raster calculation device.
FIG. 8 shows an example of a conventional raster arithmetic device.

FIG. 7(a) is an example of a system using the raster arithmetic device 100, in which 50 is a CPU, 51 is a main storage device, and 52
are various input/output devices (Ilo).

53 is a display control circuit; 54 is a display such as a CRT;
BUS is the bus, BUF is the buffer, P is the display 5
4 represents a memory brain in which image data to be displayed is stored.

- For devices that process and control bitmap graphics using sliced pixel (plane type).

The display data displayed on the display 54 is the plane P.
For example, in the case of a monochrome image, there is one brane P, and in the case of a color image, there are two or more branes P depending on the number of display colors.

In a system that handles bitmap displays, the raster arithmetic unit 100 is used when plain type display data is processed at high speed.

The raster rendering) E device 100 has each brane P independent, and as shown in FIG. 7(b), source data 60, destination data 61. A logical operation of a pool algebra using a funxilan specified by 5 is performed on the three operands of the pattern data 62, and the result is output as new destination data 63. By writing this to the memory of plane P as new display data.

You can generate various shapes.

FIG. 7(B) shows an example in which a funxilan that performs the logical operation of (source) OR (destination) AND (pattern) is specified. Depending on the settings, similar processing is possible.

The internal configuration of the conventional raster arithmetic device 100 is 8th if 2N.
It is as shown in the figure.

In FIG. 8, source registers 10.11.

This is a register in which source data 60 shown in FIG. 7(b) is read from plane P and stored.

Here, two registers are prepared.

This is to adjust the bit position to be processed since reading is performed according to word boundaries.

In order to adjust the position, a barrel shifter 15 is provided,
The barrel shifter 15 shifts data by the number of bits of the shift amount set in the shift amount register 14 in one clock.

The funk silane decoder FtJNC receives source data shifted by the barrel shifter 15 and destination data read into the destination register 2O according to the funk silan set in the funk silan register 22.

A logical operation is performed on the pattern data read into the pattern register 21.

The mask register 23 is a register that holds data for masking the left side portion of the destination line outside the window to be processed. The mask register 24 is a register that holds data for masking the right side portion outside the window to be processed.

The transfer word number counter 25 decreases the number of processed words for one line by -1.
The transfer word number hold register 26 is a register that holds the number of processed words for one line.

The output sofa 27 has a function decoder FUNC.
This is a buffer that holds the result of the calculation, and this output is written to the destination area in the plane P via the external bus 29.

A CPU 50 shown in FIG. 7(a) sets data in various registers in this raster arithmetic device and controls the mask arithmetic device like a sequencer.

[Problem to be solved by the invention]

In order to increase the speed of display processing, not only the CPU that processes data (but also the mask calculation device) is required to have high processing power.One means to increase the speed is to
The goal is to widen the bus width and increase the number of bits that can be processed simultaneously.

However, conventionally, the word length that can be calculated by a mask calculation device as shown in FIG. 8 has been fixed and is the same as the bus width determined by the type of CPU. That is, the configuration of the conventional mask calculation device cannot handle processes other than design word length and width.

This is because it is impossible to perform focus alignment using the barrel shifter 15 on the long board. On the other hand, if the design word length width is sufficiently large and it is partially used, the data from the source registers 10 and 11 will become discontinuous.

Processing becomes impossible.

In addition, even if the design word length width is more than twice the used word length, it is not possible to process two branes.
When I try to process the brain.

Since the function decoder FUNC cannot handle each brane, there is a problem in that even if the processing is forced, for example, in a time-division manner, the processing capacity will be reduced.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a mask arithmetic device which is versatile for one word length and has good processing efficiency.

[Means to solve the problem]

FIG. 1 shows an example of the configuration of the present invention.

The two source registers 10 and 11 are 9 and 0 word length register 12 each has the size of the maximum word length width that can be processed.
, the value of the bond term length is set in advance by an external CPU. The data selector 13 is the ll length register 12.
It functions to rearrange the outputs of the source registers 10 and 11 according to the values of .

The barrel shifter 15 is a circuit that performs a focus alignment operation on the output of the data selector 13 by shifting the focus according to the contents of the shift amount register 14. The barrel shifter 15 has a size twice the maximum word length and width.

The output of the barrel shifter 15 is sent to a plurality of data selectors s.
It is divided into t to S4 and input. Data selector Sl
The number of ~S4 is determined by the value obtained by dividing the number of bits of the maximum word length and width that can be processed by the number of bits of the minimum word length and width. In this example, there are four.

Also regarding function decoders F1 to F4.

It is divided into the number of bits of the maximum word length and width that can be processed divided by the number of bits of the minimum word length and width. Function decoders Fl-F4 each have data selectors 81 to 81.
S4 output and destination register 20. Based on the output of the pattern register 21, a logical operation of the function (operation type) specified by the function register 22 is executed.

The mask registers 23 and 24 are registers that hold bit mask data for masking unprocessed portions on the left and right sides of the line to be processed.

The transfer word number counter 25 decreases the number of transfer words for one line by -1.
The transfer word number hold register 26 is a register that holds the number of transfer words for one line to be processed. The value of the transfer word number hold register 26 is set by the transfer word number counter 2 at the start of processing for each line.
5, and the value of the transfer word counter 25 is 1! i
-1 is subtracted for each processing. Further, at the start of processing for one line, the value of the mask register 23 is output to the function decoders F1 to F4. Transfer word counter 2
When the value of 5 becomes O, the value of another mask register 24 is output to the function decoders F1 to F4.

The output sofa 27 has a function decoder Fl-
The calculation result by F4 is set, and data is output from there to the external bus 29 with the maximum word length and width.The external bus 29 and each register are connected by the internal bus 28 with the maximum word length and width.

[Effect]

When using the raster arithmetic device shown in FIG. 1 with the maximum word length, set the word length value in the IN length register 12, and set the value of the word length in the IN length register 12, and set the value of the 2-shift amount and the operation value in the other various registers as before. Seed, bitmask data, number of transferred words, source data 2
Set date data, pattern data, etc. and operate.

In the case of this maximum word length, the data selector 13 is.

The data from the source registers 10 and 11 are output to the barrel shifter 15 in the same order, and the data selector 81
~S4 sends data for the maximum word length and width of the barrel shifter 15 to the funxylan decoders F1~F4. This realizes the calculation of the maximum word length.

Also, when this raster arithmetic device is used with 2, for example, one-half or one-fourth of the maximum word length.

Each word length value is set in the word length register 12 and used. As a result, the data selector 13 rearranges the data from the source register 10.11, and the data selectors 81-s4.

The output of the barrel shifter 15 depends on the word length used.

Group each funk silane decoder F1 to F4
supply to. Therefore, operations depending on the word lengths used can be executed independently and simultaneously.

In the example shown in FIG. 1, "maximum word length bit number + i small word length bit number - 4", and the data selectors 81 to 54.
Although 4kl of Funk Silane decoders FINF4 are provided, it is of course not limited to 2.

The same applies to other cases as well.

〔Example〕

FIG. 2 shows an example of how the raster arithmetic device shown in FIG. 1 is used.

FIG. 3 is an embodiment of the present invention, FIG. 4 is an explanatory diagram of the operation according to the embodiment of the present invention, FIG. 5 is a 611m example using the raster arithmetic device of the present invention, and FIG. 6 is the raster arithmetic device of the present invention. The processing flow for operating the is shown below.

In FIG. 2, BUS is a bus connected to a CPU (not shown), 81 to B4 are buffers, P1 to P4 are frame memory planes, and 100 is a bus with a maximum word length of 64 bits.
This is a raster arithmetic device capable of processing a minimum word length of 16 bits.

The bit width of the bus BUS is determined by the CPU model. If this bus width is 16 bits.

The raster arithmetic device 100 according to the present invention is connected and used as shown in FIG. 2(a). This raster calculation device 10
By setting the word length of 0 to 16 bits, red, green,
Up to 4 planes P provided for each display color such as blue
For I to P4.

Logical operations can be performed independently and simultaneously.

In a system where the bus width is 32 bits, by setting the word length of the raster arithmetic unit 100 to 32 bits, the second
As shown in figure (b), two planes P1. Logical operations can be performed on P2. Furthermore, the bus width is 6
Even in a 4-bit system, two raster arithmetic devices I00 according to the present invention can be used by connecting them as shown in FIG. 2(C).

In Figure 3, the maximum word length is 64 bits and the minimum word length is 16 bits.
In Figure 0, which shows the configuration of the raster arithmetic unit used as bint, the same symbols as in Figure 1 correspond to those shown in Figure 1, and 30 is used for external CPU etc. to access each register. It is an access decoder.

In this case, source registers 10, 11 . Destination register 20. Pattern register 21, mask register 23.24. The output cover and filter 27 are 64 bits, and the barrel shifter 15 is 64 bits.

It becomes 128 bits.

Since the minimum word length is 16 bits, four 16-bit decoders are prepared as funxylan decoders F1 to F4. The shift amount register 14 is.

Since the maximum shift amount is 64, 6 bits is sufficient. The funxilan register 22 is a combination of 3 operands and has 256 types of operations.

It is made with 8 bits, and this is each Funk Thin Decoder F.
Four are prepared corresponding to 1 to F4.

Transfer word counter 25. Transfer word count hold register 26
differs depending on the width of the interval to be actually calculated, but in this embodiment it is made up of 16 bits.

The access decoder 30 has 304 signals from C3O indicating data enable for every 16 bits of the 64 bits of the RD defect signal indicating the write operation, and 4 signals for selecting each internal register. Input the book address signal and control access to each register i
T! Output the number.

When these signals are inputted by executing an instruction by the CPU, by decoding them with the access decoder 30, it is possible to know which register is being accessed.

The reason why four C8O-3 are prepared is to enable access to each of the minimum word lengths of 16 bits. 6
If 4 bits are used, they will be active at the same time.

Further, in order to perform raster operations continuously, a source register 11. which is accessed continuously. Destination register 20. A dedicated access signal line for a load signal to pattern register 21 is provided. Further, a dedicated access signal line for output signals for continuously obtaining output from the output buffer 27 is also provided.

These signal lines are created by decoding two (not shown) address lines of the CPU, and are realized by external logic, although they differ depending on (a) to (c) shown in FIG.

The circuit shown in FIG. 3 can be constructed using one type of LSI.

It is convenient because it can be used in correspondence with a plurality of minimum word lengths to maximum word lengths.

Data selection by the data selector 13 and data selectors 81 to S4 shown in FIG. 3 is performed according to the word length used.
This is done as shown in FIG. 4(b).

In addition, in FIG. 4 (B), the data read from the frame memory for each plane P1 to P4 is divided into 1 FIG. 4 (B).
As shown in the figure, each 16 bits is 0°1.2. It is expressed as...

When the word length used is 16 bits, the barrel shifter 15 has
0.1 data on plane P1, 0.1 data on plane P2.
1 data, 0. of plane P3. The data selector 13 selects data so that the data is input in the order of data 1 and data 0 and 1 of plane P4. The data selectors 31-S4 send the data shifted by the necessary number of bits by the barrel shifter 15 to each function decoder F1-F4, and the results of raster operation are outputted to each plane PL-P4.

In the case of 32-bit width and 64-bit width, Fig. 4 (b)
As shown in FIG. 2, the data selector 13 and the data selectors 81 to S4 select data according to the word length used.

Next, the raster operation performed by the processing IJm of the CPU 50 will be described with reference to FIGS. 5 and 6.

Here, the plane Pi shown in FIGS. 5(a) and 5(b),
Sources stored in each source area SA of P2 ■
, ■ to the raster calculation device 100. Next, send the destination data ■ stored in the destination area DA.

Furthermore, a series of processes are repeated in which the pattern data (2) stored in the pattern area PA is sent, and the result (2) of raster calculation based on them is written back to the destination area DA.

The processing by the CPU 50 is performed as shown in FIGS. 6(a) to (11).

Since the value of the word length register 12 shown in FIG. 3 is determined at the time of system design, it is set in advance during IPL or the like.

ial~(al First, the values of the shift amount register 14, funxylan register 22, mask register 23, 24 and transfer word count hold register 26, which vary depending on the transfer specification, are sent.Transfer word count hold register 2
The six cent value is automatically transferred to the transfer word counter 25.

(r) Read the first source ■. This is because two words of the source are required for one word of the destination in order to match the pit alignment with the destination. The read address is generated from the CPU 50, as shown in FIG. 5(b).

(Resource ■ Read the next source ■, source ■.

The data is sectored into the source register 11 shown in FIG.

fh) Read the destination, the destination data is the destination register 20
is set to

(1) Read the pattern. The pattern data is sent to the pattern register 21.

(Writes the output of the Jl Funk Silane decoder to the destination.

(k) Check whether the transfer in the X direction has been completed by counting the number of transferred words. The processing operations (1 to (c) are repeated until the transfer in the X direction is completed. During this time, the generation of an address for the brain is performed by the CPU 50. .

From the second time onwards, only one word needs to be read into the source register 11.

(11) Every time the transfer in the X direction is completed, count how many lines have been transferred and check whether the transfer in the Y direction has been completed.
``Repeat steps from ) to (g)). Once completed, complete the process related to raster operations.''

〔Effect of the invention〕

As explained above, according to the present invention, one raster arithmetic unit can be used flexibly in response to various bus widths, and when the word length is not the maximum, it can be used in accordance with the number of bits to be processed. hand,? ! [It also becomes possible to process branes of numbers. Even when processing a plurality of branes, the processing capacity does not decrease, and it is useful because it has versatility, especially when implemented as an LSI.

[Brief explanation of drawings]

FIG. 1 shows a configuration example of the present invention. FIG. 2 shows an example of how the raster arithmetic device shown in FIG. 1 is used. FIG. 3 shows an embodiment of the present invention. FIG. 4 is an explanatory diagram of the operation according to the embodiment of the present invention. FIG. 5 shows an example of control by the raster arithmetic device of the present invention. FIG. 6 is a processing flow for operating the raster arithmetic device of the present invention. FIG. 7 is a diagram for explaining the instant raster arithmetic device. FIG. 8 shows an example of a conventional raster arithmetic device. In the figure, 10.11 is a source register, 12 is a word length register, 13 is a data selector, 14 is a shift amount register,
15 is a barrel shifter, 51 to S4 are data selectors, F
1 to F4 are funxian decoders, and 20 is a destination register. 21 is a pattern register, 22 is a funky silane register, 23.24 is a mask register, 25 is a transfer word counter, and 26 is a transfer! An i failure hold register, 27 an output buffer, 28 an internal bus, and 29 an external bus. Patent applicant: BFNY Co., Ltd. Representative: Patent attorney: Yoshiyoshi Ogasawara (2 others)

Claims (1)

[Claims] In a raster arithmetic device that controls bitmap graphics, there is provided a source register (10, 11) with a maximum word length width and a data selector that rearranges the output of the source register according to the word length used. (13), a barrel shifter (15) with a width twice the maximum word length width that uses the output of the data selector as input, and a plurality of data that selects the output of the barrel shifter according to the word length used. A plurality of selectors (S1 to S4) that perform arithmetic processing according to a specified function based on the outputs of the plurality of data selectors and the outputs of the destination register and pattern register, each having a maximum word length width. 1. A raster arithmetic device comprising: a function decoder (F1 to F4) corresponding to a minimum word length width, and having a variable word length width.