JPH01154286A - Graphic processor - Google Patents

Abstract

PURPOSE:To control a processing speed, while holding the same function and to suppress the development quantity of a hardware and a firmware of a processor, etc. by connecting in series one piece of or plural processors loaded with the same firmware in accordance with necessity. CONSTITUTION:The graphic processor is constituted by using a processor P1 loaded with plural firmwares F1-F6 and connecting a necessary number of processors. The firmwares F1-F6 are modules for processing each part of a flow of a graphic processing of a coordinate converting part 31, a clip part 32, etc. by a program. the processor P1 is loaded with an MPU, and this MPU can be switched so that it can execute a service to all of the firmwares F1-F6 or can execute a service to a part thereof. Also, a necessary number of processes can be connected in series.

Description

[Detailed Description of the Invention] [Summary] Regarding the configuration of processors that process graphic data, the purpose of this invention is to enable combinations of high-speed versions and low-priced versions, and to combine multiple processors in one processor. Equipped with firmware (graphic processing module), the MPU in the processor can be switched to service only one firmware or multiple firmware, and the required number of processors can be connected in series. composition.

[Industrial application field]

The present invention relates to a graphic display device, and particularly to the configuration of a processor that processes graphic data.

Generally, in a graphic display device, the user describes information such as the shape and color of the figure that the user wants to display as a figure list.
The display device processes the graphic list in the order in which it is written and finally displays the graphics on the screen.

[Conventional technology]

Traditionally, when designing a graphic display device,
The flow of graphic processing is divided into several processing modules such as "coordinate transformation section" and "clip section", and each processing module is realized with hardware or processor and firmware depending on the balance between performance and cost.
It was common to realize a graphic display device by combining them via a FIFO bath sofa.

In this way, after designing the second display device to operate as fast as possible, for example, the display speed may be a little slow, but the device's functions (types of shapes such as line segments and polygons, shapes such as solid color and ropes) When it became necessary to design an identical device at a lower cost, we had no choice but to redesign the device anew.

In other words, if we focus on part of the flow of graphic processing, even though the processing functions are the same, in order to achieve the conflicting goals of a high-speed version and a low-priced version, it is usually necessary to design separate hardware and firmware. did not become.

[Problem that the invention seeks to solve]

In the conventional method, separate designs are made for the configurations of both the high-speed version and the low-priced version, which has the disadvantage of resulting in increased costs due to duplication of processes.

The present invention aims to improve these points and to make it possible to combine them into a high-speed version and a low-cost version.

[Means for solving problems]

As shown in FIG.
A graphics processor is constructed by connecting a required number of processors P1 equipped with processors P1 to F6. Firmware Fl, F2. . . . are processing modules that process each part of the flow of graphic processing, such as the above-mentioned "coordinate transformation section" and "clip section", using a program.

Although not shown, the processor P1 is also equipped with a microprocessor (MPU), and this MPU has firmware Fl, F2 . It is possible to switch between servicing all or a part of... In addition, the required number of processors can be connected in series.

[Effect]

This processor is used as shown in Fig. 1(d) and (d). As shown in Figure 1 (C), the MPU of the Prosensor serves only one firmware (Fl in the figure), and in this example, 6
This is a high-speed graphics processor that is connected in series. Pl, F2. ...F6 is the 6 processors, PI only handles Fl, F2 only handles F2,
...F6 serves only F6. In this way, the MPU of each processor only needs to service one firmware, which enables high-speed processing.

In graphic processing, each process, such as coordinate transformation and then clip processing, has an order, so processor P1. P2.・
. . . is a serial connection, in which the processing result of the previous stage processor is received, the processing of that stage is performed, and the result is passed to the subsequent stage processor. Of course, pipeline processing is possible; it is not possible to receive a data block from the previous stage, process it, pass the result to the next stage, and then receive the next data block from the previous stage and process it. Ru.

In FIG. 1(d), the MPU of processor P1 services all firmware F1 to F6.

Therefore, the processor in FIG. 1 (dl) is one and has the same processing function as the six processors in FIG. 1 (bl. However,
In FIG. 1(d), one MPU must service all firmware Fl-F6, so
Processing will be slower.

〔Example〕

FIG. 2 is a diagram showing a configuration example of a graphic display device which is an application example of the present invention. This display device includes a segment buffer 1, a segment management section 2, a geometric processing section 3, a surface painting section 4, and a DDA (Digital Diff.
The display unit 5 includes a frame buffer 6, a frame buffer 6, and a display unit 7. The geometry processing section 3 further includes a coordinate transformation section 3 and a crimp section 32. The segment buffer 1 stores a graphic list such as graphic elements and coordinate transformation matrices. The segment management section 2 manages and reads segment buffers and controls the entire display device.

When displaying graphic elements, the segment management section 2 reads out the graphic list stored in the segment buffer 1 and transfers it to the next-stage geometric processing section.

The geometry processing unit 3 is one in which one or more processors according to the present invention are connected in series, and the coordinate transformation unit 31 is configured to:
Seven-trix operations are performed on the coordinate data of graphic elements to perform geometric transformations such as rotation, movement, and scaling of the graphic elements. When displaying a graphic on the screen, the clipping unit 32 performs a process of trimming graphic elements that protrude outside the display area.

The area painting section 4 generates a vector sequence that contains graphic elements. Further, the DDA section 5 decomposes each vector into pixel columns and writes them into the frame buffer 6. The display unit 7 visually displays the contents of the frame buffer 6.

FIG. 3 shows the hardware configuration of the processor of the present invention. As shown in the figure, this processor P1 (P2, etc. is also the same)
microprocessor (MPU) 11, read-only memory (ROM) 12, random access memory (RAM)
)13, Input FIFO (First In Firs)
t Out ) buffer 14, output FIFO buffer 1
5.

The MPU II performs processing such as data input/output and calculations.

The ROM 12 stores firmware (F1 to F6 described above) that defines the operation of the MPU II. Furthermore, this (ROM
) can also be implemented using RAM. RAM13
stores the coefficients, work area, data, and tables that specify the flow of control necessary for the operation of MPU II. Input F
IFOI 4 stores data here when inputting data from the outside (previous stage) of the processor, absorbs synchronization deviations in receiving and passing data with the previous processing block, and improves the MPU utilization rate. It is intended to improve. In addition, when the processor outputs data to the outside (later stage), the output FIFOI 5 stores the data here, so that the data reception with the subsequent processing block absorbs the synchronization shift related to the transfer, and the MPU This is to improve the operating rate. Series connection of multiple processors is done through this input/output PIFO.

When inputting data to this processor, the data is written to the input FIFO I 4 via the data line a.

At this time, if the input FIFO is full, the signal line
Notify external parties to that effect. When the MPU II needs input data, it sends it to the input FIFO via the data line C.
Import data from I4. At this time, the input FIFO
If 4 is empty, the signal line d indicates this to the MPU II.
will be notified. The MPU stops processing while the input FIFO is empty.

When the MPU II outputs data to the outside, it outputs the data to the output PIFOI 5 via the data line e. At this time, if the output PIFOL 5 is full, the MPU is notified of this via the signal line r.

The MPU II stops processing while the output FIFO is full of data. When data is output from this processor to the outside, the data is output via the data line g. At this time, if the output FIFO I 5 is empty and there is no data to be output, this is notified to the outside via a signal line.

The other ends of the signal lines S and H are the MPUs of the front and rear processors.
Connect to. MP by these signal lines S, d, f, h
U does not need to constantly monitor the status of input/output FIFO (
This allows the user to concentrate on firmware processing and speeds up the processing.

Input FIFOI 4 and output FIFOI 5 are RAM13
shall be located in the same address space as . FIG. 4 shows an example of the address space of the RAM and FIFO.

As shown in FIG. 4(a), if the generated address points to the built-in RAM, reading and writing from the MPU II will be performed with the built-in RAM 13, and the generated address will be generated as shown in FIG. 4(b). If the address points to an input or output FIFO, reading and writing are automatically performed to the outside via the FIFO.

It is assumed that the address range of the input FIFO and the output FIFO has an appropriate width, and any address within that range can be specified to communicate with the FIFO.

Specifically, the lower bit string of the address is ignored and only the upper bit string is decoded. With this function, even when inputting and outputting several words of data consecutively, it is possible to do so while incrementing the address as if reading and writing from RAM.

Switching between the built-in RAM and the FIFO can be easily done by using a combination of pace registers and Intel Nox registers that are normally provided in microprocessors.

That is, when communicating with the built-in RAM, the pace register is configured to fill the internal QRAM, and when communicating with the input/output FIFO, the pace register is configured to fill the input/output FIFO.
to point to. There is no need to specify RAM, input FIFO 1 output 14FO with an instruction, just specify RAM with an address.
It is possible to read/write data to/from the input FIFO, read data from the input FIFO, and write data to the output FIFO. The index register is used to read and write while incrementing the address to be accessed.

In this way, even with the same firmware, it is possible to read from and write to the built-in RAM or read and write from the FIFO by switching the pace register.

Next, using FIG. 5, it will be explained that by using these functions, different configurations can be handled with the same firmware. Figure 5 shows a processor with two processing modules installed inside the processor.
Fig. 1 shows an example in which only Fl and F2 are mounted. In each figure, thick lines indicate the flow of data, and thin lines indicate the flow of control.

FIG. 5(a) is an example in which only the processing module 1 is used. In this case, the input data is input from the input FIFO, and the processing result is output from the output FIFO.
(None of the output FIFOs are shown in the figure).Furthermore, after processing the - set of data, control returns to the beginning of the processing module 1, that is, to input processing.

On the other hand, Figure 5) is an example in which both processing modules 1 and 2 are used. In this case, in processing module 1, the input light is input to the input FIFO 1, and the cutting edge is to the built-in RAM, and the control is to the processing module 2. In the processing module 2, the input light is to the built-in RAM, and the output light is to the output FIF.
The O1 control is performed by the processing module 1.

These pieces of information are written in tables in advance, and changes in the configuration can be handled by referring to these tables during processing. A specific method for this is, for example, when a processor is initialized by power-on or reset, a host computer transfers a table to be stored in each processor. In that case, each processor identifies this table setting command, writes out its own table to the internal RAM 13, and then transfers it to the next stage.

As is clear from Figures 5(a) and (b), the input light and output light are determined by the pace register settings, so the only difference between Figures 5(a) and (b) is the pace register settings. This allows it to be used both as a processor for the IMPUI processing module and as a processor for the IMPU2 processing module.

Note that one or both of the input and output side FIFOs can be omitted. However, if both are omitted, MP
A decrease in the efficiency of U is expected.

Further, when the processor operates in synchronization with the modules before and after it, the signal lines S, d, f, and h can be omitted.

〔Effect of the invention〕

As explained above, according to the present invention, by connecting one or more processors equipped with the same firmware in series as necessary, the processing speed can be adjusted while maintaining the same functions. (LS
I) The amount of development of hardware and firmware can be suppressed, and costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a block diagram showing an example of the use of the present invention, FIG. 3 is a block diagram showing the hardware configuration of the processor, FIG. 4 is an explanatory diagram of the RAM space, FIG. 5 is an explanatory diagram of the operation of the embodiment of the present invention.

Claims (14)

[Claims] (1) A graphics processor that performs a series of graphic processing as a whole by connecting a plurality of identical processors in series and each performing a separate process. (2) The graphics processor according to claim 1, wherein the number of series connections can be varied from 1 to n. (3) The processor includes: - a microprocessor (11) that performs processing such as data input/output and arithmetic operations, and - a read-only memory or random access memory (12) that stores firmware that describes the operation of the microprocessor.・Random access memory (13
), and each input and output port is set in the same address space as the random access memory (13). (4) Each of the input and output ports of the processor has a suitable address width, and includes means for treating any access within that range as an access to the respective port. Graphics processors as described in section. (5) Changing the number of series connections from 1 to n is achieved by changing the table in the random access memory (13) and determining the input/output address and control transfer destination by referring to the table in the random access memory (13). A graphics processor according to claim 4, which is implemented by. (6) The processor further includes signal lines (b, h) indicating whether input/output with the outside is possible, and if it is determined from the signal lines that input/output is not possible, the microprocessor 6. The graphics processor according to claim 5, having a function of stopping processing. (7) The processor further includes FIFO buffers (14, 15) for either or both input and output, and the input/output between the FIFO, the buffer, and the microprocessor is caused by the FIFO buffer being empty or full. 6. The graphics processor according to claim 5, further comprising a function of stopping the processing of the microprocessor if it is not possible until it becomes possible. (8) A graphics system that has a configuration in which a plurality of identical processors are connected in series, each of which performs separate processing, thereby performing a series of graphic processing as a whole. (9) The graphics system according to claim 8, wherein the number of series connections can be varied from 1 to n. (10) The processor includes: - a microprocessor (11) that performs processing such as data input/output and arithmetic operations, and - a read-only memory or random access memory (12) that stores firmware that describes the operation of the microprocessor.・Random access memory (13
), and each input and output port is set in the same address space as the random access memory (13). (11) Each of the input and output ports of the processor has a suitable address width, and includes means for treating any access within that range as an access to the respective port. The graphics system described in Section. (12) Changing the number of serial connections from 1 to n is achieved by changing the table in the random access memory (13) and determining the input/output address and control transfer destination by referring to the table in the random access memory (13). A graphics system according to claim 11, which is performed by. (13) The processor further includes signal lines (b, h) indicating whether input/output with the outside is possible, and if it is determined from the signal lines that input/output is not possible, the processor is connected to the microprocessor until it becomes possible. 13. The graphics system according to claim 12, comprising a function of stopping processing of a processor. (14) The processor further includes FIFO buffers (14, 15) for either or both input and output, and input/output between the FIFO buffer and the microprocessor is impossible because the FIFO buffer is empty or full. 13. The graphics system according to claim 12, further comprising a function of stopping processing of the microprocessor until it becomes possible to do so.