JPH03268024A - Microprocessor, information processor and graphic display device using it - Google Patents

Abstract

PURPOSE:To execute the picture element arithmetic operation at high speed by a small number of register resources by allocating plural arithmetic units having a multiplying function to one register unit, and actuating them simultaneously by an exclusive instruction. CONSTITUTION:Plural arithmetic units 2 - 5 having a multiplying function are provided, and also, one register designated by an instruction is divided into plural areas, and each arithmetic unit 2 - 5 is allowed to correspond to the respective areas. For instance, a register unit is divided into four areas, and the arithmetic units 2 - 5 are connected to each of them through data lines 10 - 13. Also, in an instruction controller 6, an instruction for actuating simultaneously the multiplying functions of the arithmetic units 2 - 5 is registered in advance, and in accordance with this instruction, a general arithmetic unit 1 executes such processings as an arithmetic operation and a data transfer, etc., to all areas of the register unit. In such a way, the information processing can be executed efficiently.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing device using electronic technology, and particularly to a microprocessor and a graphic processing device that are intended to process graphic data at high speed. Applicable.

[Conventional technology]

Conventional devices are described in I.E.E., Computer Graphics and Applications, 198
July 9th issue, pages 85 to 94 (IEEE Com
puter Graphics & Applications
ions, July.

1987, pp. 85-94), technology that divides one register into multiple areas for simple addition and processes data using multiple adders corresponding to each area. It performed information processing such as parallel pixel calculations.

This device is suitable for performing simple processing such as brightness interpolation in graphics processing, but in processing that requires multiplication, such as alpha blending processing to create transparency, pixel calculations are performed using a combination of many instructions. It was necessary to write a multiplication program for this purpose, making effective processing difficult.

[Problem to be solved by the invention]

The present invention provides a means for efficiently performing information processing such as parallel pixel operations including multiplication, which have been difficult to perform efficiently using conventional techniques.

[Means to solve the problem]

To achieve the above object, the present invention provides a register group consisting of a plurality of registers, a register selection device that selects one register unit from the register group, and at least a multiplication function that performs operations on different bit strings in the register. An information processing device is configured from a plurality of arithmetic devices having a plurality of arithmetic devices, a general-purpose arithmetic device that performs data processing on the total bit length of the register unit, and a control device that controls the register group, the general-purpose arithmetic device, and the arithmetic device. This is what I did.

[Effect]

In order to provide multiple arithmetic units with multiplication functions and further improve register usage efficiency in parallel pixel operations,
One register specified by an instruction is divided into a plurality of areas, and each area is associated with the arithmetic unit. If a means for storing only a part of the bit string of the operation result in the register is provided, the register utilization efficiency will be further improved.

Furthermore, if a signal line for transmitting arithmetic auxiliary signals such as a carry signal is provided between each arithmetic unit, a plurality of arithmetic units used in the present invention can be combined to form an arithmetic unit with a larger bit length. These hardwares are controlled by a control device.

The information processing device according to the present invention can be a component of a microprocessor. In that case, the microprocessor is equipped with dedicated instructions and has an internal control unit that interprets them.

By applying the above information processing device to a display device or a printing device using a cathode ray tube, a high-performance graphic processing device can be realized.

〔Example〕

FIG. 1 is a configuration diagram showing an embodiment of an information processing apparatus according to the present invention. In FIG. 1, numerals 2, 3, and 4.5 are arithmetic units, each having a multiplication function.

General-purpose arithmetic unit 1 is connected to data bus 15 , and instruction control device 6 is connected to instruction bus 16 . The command bus and data bus may be shared.

The instruction control device 6 transmits control signals corresponding to the instructions to the arithmetic devices 2, 3, 4, and 5, the register selection device 7, and the general-purpose arithmetic device 1 via a control line 9, thereby controlling their respective operations. Registered in the instruction control device 6 is an instruction for simultaneously activating the multiplication functions of the arithmetic units 2, 3, 4.5. Control 4I
9 may be given to each device independently. The register selection device 7 selects a necessary register unit from the register group 8 according to the instruction. 14 is a register group control line. In the case of a processor with a 32-bit general purpose arithmetic bag W1, the register unit is 32 bits in principle, but
In register pairs used in double-precision operations, the register unit may be 64 bits or 128 bits.

In the present invention, a register unit is divided into a plurality of bit strings and used. An arithmetic unit is provided corresponding to each divided area. In the embodiment shown in FIG. 1, the register unit is divided into four areas, and arithmetic units 2, 3, 4.5 are connected to each area via data lines 10, 11, 12, 13. The number of divisions in register units can be specified by an instruction. The total number of arithmetic units is four in the embodiment shown in FIG. 1, but as many as necessary are provided depending on the number of divisions in register units. The general-purpose arithmetic unit 1 performs processing such as arithmetic operations and data transfer on the entire register unit area.

When a system with such a configuration is used to calculate graphic data, extremely high-speed graphics processing can be achieved. Hereinafter, a case will be described as an example in which alpha blend processing, which is often used in computer graphics, is executed in a system where the general-purpose calculation bag W1 is a 32-bit processor. Generally, a pixel is expressed by three elements, R (red), G (green), and B (blue), and each is assigned, for example, 8-bit data. The alpha blend process converts two pixel data (R1, Gl, Bl) and (R2, G2°B2) into P
:Q ratio is used to create a sense of transparency, and the pixel data (R3, G3°B3) after mixing is expressed by the following equation.

R3=PXR1+QXR2 G3=PXG1+QXG2 B3=PXB1+QXB2 FIG. 6 is a schematic diagram of alpha blending that can be accelerated by the information processing apparatus according to the present invention. The parts surrounded by small circles in the figure represent pixels. If this processing were to be performed by a 32-bit general-purpose arithmetic unit, six multiplications and three additions would have to be performed.

Another disadvantage is that when 8-bit data is allocated one by one to a 32-bit space, which is a register unit, the remaining 24 bits are wasted. In the present invention, 8 pints of data are allocated to a 32-bit space in register units at a maximum of 4 times, and an arithmetic unit 2゜3.4.5 having a multiplication function is provided to handle each data in parallel. By doing this, we aimed to increase speed and improve register usage efficiency.

Furthermore, by providing a dedicated instruction for activating multiple arithmetic units at the same time, efficient programming becomes possible. Some conventional technologies have made it possible to reduce the number of additions by operating 8-bit adders in parallel, but there is no effective means for multiplication, which takes up most of the calculation time. I didn't have it. In the conventional technology, even if a data structure for parallelization of addition is defined and four pieces of 8-bit data are allocated in a 32-bit space, the addition part and the multiplication part are There were drawbacks such as the need for data type conversion processing when transferring data between parts. However, in the present invention all these drawbacks are solved. The example described above is an example in which a 32-bit general-purpose arithmetic unit and an 8-bit arithmetic unit are combined, but the bit lengths of these can be arbitrarily determined by the system designer.

FIG. 2 is a diagram showing an example of the calculation contents to be executed by the calculation devices 2, 3, 4.5. 21 is the multiplicand, 22 is the multiplier,
23 is the calculation result. The multiplicand 21 divides a 32-bit area into 8-bit units, and stores four integer data a, b, c,
d is assigned. Similarly, for multiplier 22, ev f
+ gv h is assigned. Operation result 23 is also 8
Separated by bit, aXe, bXf, cXg, dX
The upper 8 bits of each h are given. Multiplier 22. The multiplicand 21 and the calculation result 23 are stored inside the register group 8. Also, only one 8-bit data h is specified in the multiplier 22, and the calculation result 23 is dXh, bXh, cX
By defining an instruction to store the upper 8 bits of h and dXh, calculation efficiency can be improved when one multiplier is common to four multiplicands.

In the above example, the upper 8 bits of the product were used as the calculation result, but
In some cases, the lower bits are stored in a register as the result of the operation. By using register pairs, it is also possible to store four sets of 16-bit products obtained by four sets of 8-bit multiplications in a 64-bit space.

The data for the multiplier 22 and the multiplicand 21 can be of various types, such as signed integers, unsigned integers, floating point numbers, fixed point numbers, etc. Also, the bit length is 8 bits and 16 bits.
bit, 24 bit, 32 bit, 64 bit, 128
Any value suitable for the system, such as 13 bits or 13 bits, can be selected. The command control device 6 has a command bus 16
It has the function of determining the data type and bit length according to the information obtained from the data.

Since the arithmetic units 2, 3, and 4.5 are controlled by the instruction control unit 6, they can easily have addition/subtraction functions, product-sum functions, and division functions in addition to multiplication functions.

The arithmetic units 2, 3, and 4.5 for executing the product-sum operation each have a structure in which an adder and a multiplier are connected.

In FIG. 7, arithmetic units 2, 3,
An example of the configuration that 4.5 should take is shown below. 71 is an adder, and 72 is a multiplier.

The flags indicating information accompanying the calculation contents described above are:
In the case of having it inside the general-purpose arithmetic unit 1, and in the case of having it inside the arithmetic unit 2, 3,
4.5, internally in the register group 8, and externally as a signal.
Some systems do not specifically define flags. FIG. 8 shows an embodiment of a flag method for storing flags in general-purpose registers. In this example, rl stores a carry flag C indicating a carry in addition or a borrow in subtraction, r2 stores a sign flag S representing a sign, and r3 stores a Z flag representing zero. When flags are stored in register units in register group 8 in this way, the register unit is divided into multiple areas in the same shape as the registers that store operation results, and the flags associated with each operation are stored in the corresponding areas. By using the flag signals generated in the arithmetic units 2, 3, 4.5, it is possible to easily store the flag signals in the register group 8.

FIG. 3 is a block diagram showing another embodiment of the present invention. The calculation auxiliary signal lines 30, 31, 32.33 are connected to the calculation device 2,
3.4.5, and is used when a plurality of arithmetic units E2゜3.4.5 are combined and used organically.

For example, if the arithmetic units 2, 3, 4.5 are 8-bit adders, the arithmetic auxiliary signal is a carry signal, and the arithmetic auxiliary signal lines 30, 31, 32 are used, the arithmetic units 2, 3, 4.
．． 5 is equivalent to a 32-bit adder as a whole. At this time, if the calculation auxiliary signal line 31 is not connected, two sets of 16
It becomes a bit adder. In addition, when the arithmetic units 2 and 3°4.5 are 8-bit shift arithmetic units, the arithmetic auxiliary signal line 3
By using 0, 31, 32, and 33, it becomes a 32-bit rotary quintuple arithmetic unit. The above switching of functions is performed by the command control device 6.

FIG. 4 shows an example of an instruction for simultaneously activating a plurality of multiplication functions among the arithmetic units 2, 3, and 4.5. The operation code 41 is defined according to the content of the operation. Further, the operand 42 specifies a register unit as a source and destination of data related to an operation. rl, r2.
r3 represents a register unit. This instruction is characterized in that it can be written in one step even when multiple multipliers are assigned to one register unit at the same time, and is an effective means when the information processing device according to the present invention becomes a component of a microprocessor. Become. The instruction opcode and operands differ depending on whether the operation unit of the arithmetic unit 2, 3, 4.5 is 8 bits or 16 bits, if the arithmetic unit only performs multiplication, or if it performs a multiply-accumulate operation. You can define multiple items with different expressions. Further, a part of the bit string constituting the instruction is used to distinguish between the processing state according to the present invention and the processing state by the general-purpose arithmetic unit 1. FIG. 9 is an example of an instruction provided with a bit for switching to a processing state according to the present invention.

92 is an instruction bit string, and 91 is a processing state switching bit. By setting a plurality of processing state switching bits, more complex control becomes possible.

FIG. 5 shows another embodiment of the invention. The microprocessor 54 includes the functions of the information processing device according to the present invention.

Storage device 151 and display device! ! By connecting 52 via bus 53 to a microprocessor 54 according to the invention, a graphics display device is obtained which provides particularly fast alpha blending processing. Frame memory 55 stores pixel data. By connecting a printing device to the bus 53, a printing device capable of printing the figures displayed on the display device 52 is obtained.

〔Effect of the invention〕

As described above, in the present invention, arithmetic units with multiple multiplication functions can be assigned to one register unit and can be activated simultaneously by a dedicated instruction, thereby realizing a system that executes high-speed pixel operations with few register resources. can. In particular, alpha blend processing in graphics has the effect of significantly reducing calculation time and improving memory usage efficiency by shortening programs.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an example of calculation contents executed by the calculation device according to the invention.
FIG. 3 is a configuration diagram showing another embodiment of the present invention. Fig. 4 is a diagram showing one embodiment of the instructions according to the present invention, Fig. 5 is a block diagram showing still another embodiment of the present invention, Fig. 6 is a schematic diagram of alpha blending, and Fig. 7 is a sum of products. FIG. 8 is a diagram showing an embodiment of a flag system according to the present invention, and FIG. 9 is a diagram showing an embodiment of an instruction having a bit for switching the processing state. DESCRIPTION OF SYMBOLS 1... General-purpose arithmetic device, 2, 3, 4.5... Arithmetic device with multiplication function, 6... Instruction control device, 7... Register selection device, 8... Register group, 9. ...Control line, 10°11.12.13...Data line, 14...
Register group control line, 15...data bus, 16...
Instruction bus, 21... Multiplicand, 22... Multiplier, 23.
... calculation result, 30.31, 32, 33 ... calculation auxiliary signal line, 41 ... operation code, 42 ... operand, 51 ... storage device, 52 ... display device, 53 ...
- Bus, 54... Microprocessor, 55... Frame memory, 71... Adder, 72... Multiplier,
91...Processing state switching bit 4 Figure 5 Figure Figure 5 Figure Figure Figure 5

Claims (1)

[Claims] 1. A register group consisting of a plurality of registers, a register selection device that selects one register unit from the register group, and a plurality of registers each having at least a multiplication function that performs an operation on different bit strings in the register. An information processing device comprising: an arithmetic device; a general-purpose arithmetic device that performs data processing on the total bit length of the register unit; and a control device that controls the register group, the general-purpose arithmetic device, and the arithmetic device. 2. The information processing apparatus according to claim 1, wherein a part of the bit string of the multiplication result of the arithmetic unit is stored in a divided part of the selected register. 3. The information processing apparatus according to claim 1 or 2, further comprising a signal line for transmitting a calculation auxiliary signal between the calculation units. 4. The information processing apparatus according to claim 1, wherein the microprocessor is provided with a dedicated instruction for simultaneously activating the plurality of arithmetic units. 5. A graphic display device, characterized in that the information processing device according to any one of claims 1 to 4 is provided with an external storage device and a display device.