JPH0225259B2 - - Google Patents
Info
- Publication number
- JPH0225259B2 JPH0225259B2 JP57048478A JP4847882A JPH0225259B2 JP H0225259 B2 JPH0225259 B2 JP H0225259B2 JP 57048478 A JP57048478 A JP 57048478A JP 4847882 A JP4847882 A JP 4847882A JP H0225259 B2 JPH0225259 B2 JP H0225259B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- resistor
- resistors
- resistance
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 41
- 239000004065 semiconductor Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 description 12
- 239000012535 impurity Substances 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は抵抗回路網を備えてなる半導体装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including a resistor network.
近年、半導体装置の応用分野の拡大はめざまし
いものがあり、従来個別部品、または調整技術を
用いて十分な精度が必要とされる分野への急速に
浸透している。 In recent years, the field of application of semiconductor devices has been expanding at a remarkable pace, and they are rapidly penetrating fields that require sufficient precision using conventional individual components or adjustment techniques.
このような一例として、アナログ信号をデジタ
ル信号に変換するアナログ・デジタル変換信号処
理の分野について考えてみると、アナログ信号の
如き時間連続信号をサンプリングすることに時間
離散信号(パルス振幅変調)となした後、振幅を
量子化することによりデジタル信号に変換するこ
とになる。このため、アナログ・デジタル変換回
路にしては当然サンプル・ホールド回路が必要と
なる。 As an example of this, consider the field of analog-to-digital conversion signal processing, which converts analog signals into digital signals. After that, it is converted into a digital signal by quantizing the amplitude. For this reason, an analog-to-digital conversion circuit naturally requires a sample-and-hold circuit.
アナログ信号をある周期でサンプル・ホールド
しデジタル信号に変換する際には、その変換系の
精度を確保するために折り返し歪防止用フイルタ
を用いて入力されるアナログ信号の帯域制限が必
要となる。 When an analog signal is sampled and held at a certain period and converted into a digital signal, it is necessary to limit the band of the input analog signal using an aliasing distortion prevention filter to ensure the accuracy of the conversion system.
例えば4KHzのアナログ信号をデジタル信号に
変換するときには、サンプリング定理により、サ
ンプリング周期は125μsec(サンプリング周波数
8KHzに相当)が最小周期となる。すなわち、折
り返し歪をさけるためには、入力されるアナログ
信号に対して帯域制限することが必要である。 For example, when converting a 4KHz analog signal to a digital signal, according to the sampling theorem, the sampling period is 125μsec (sampling frequency
(equivalent to 8KHz) is the minimum period. That is, in order to avoid aliasing distortion, it is necessary to band limit the input analog signal.
この目的のため、半導体装置として用いられて
きた技術は、多結晶シリコンまたは拡散抵抗を抵
抗体として用い、絶縁体を誘電体として用いた容
量により、半導体基板上にCRフイルタを構成す
るのが通常であつた。 For this purpose, the technology used for semiconductor devices is to construct a CR filter on a semiconductor substrate using polycrystalline silicon or a diffused resistor as a resistor and a capacitor using an insulator as a dielectric. It was hot.
CR時定数を大きくし、フイルタの動作周波数
を低周波領域まで拡げるためには、抵抗体の抵抗
値Rを大きくするが、容量Cを大きくするしかな
いことは明らかである。 In order to increase the CR time constant and extend the operating frequency of the filter to a low frequency range, the resistance value R of the resistor is increased, but it is clear that the only option is to increase the capacitance C.
従来、この目的のためには抵抗体の面積を大く
とり抵抗値を大きくするか、容量面積を大きくす
る等が考えられ、半導体面積を大きくすることが
必要であつた。これをさけるためには、多結晶シ
リコンに拡散する不純物量を少なくした抵抗体が
考えられるが、このような抵抗体のシート抵抗は
非常に大きな値となり、この変動を制御するのは
容易ではない。単位容量値を大きくすることは容
量誘電体の膜厚を薄くすれば可能であるが製造時
の誤差を考えればおのずから大きくすることに限
界があつた。 Conventionally, for this purpose, it has been considered to increase the area of the resistor to increase the resistance value, or to increase the capacitance area, and it has been necessary to increase the semiconductor area. To avoid this, it is possible to create a resistor that reduces the amount of impurities that diffuse into polycrystalline silicon, but the sheet resistance of such a resistor becomes a very large value, and it is not easy to control this variation. . Although it is possible to increase the unit capacitance value by reducing the film thickness of the capacitive dielectric, there is a limit to increasing it due to manufacturing errors.
また、CMOS等で使用されるPウエル、Nウ
エル等の領域を用した抵抗体も考えられるが、こ
れらの抵抗体は電圧対抵抗値の係数が大きいこ
と、また接合容量が大きいため、周波数特性が劣
化する欠点を有していた。 In addition, resistors using regions such as P-well and N-well used in CMOS etc. can be considered, but these resistors have a large coefficient of voltage vs. resistance value and a large junction capacitance, so the frequency characteristics had the disadvantage of deterioration.
本発明はかかる欠点のない、半導体面積を最小
となし、比精度の優れた抵抗体を複数の多結晶シ
リコンを単位抵抗体群を用いて構成することが可
能となり、半導体装置の応用分野の拡大に非常に
有効である半導体装置を提供することを目的とす
る。 The present invention does not have such drawbacks, minimizes the semiconductor area, and makes it possible to construct a resistor with excellent specific accuracy by using a plurality of polycrystalline silicon units as a unit resistor group, thereby expanding the field of application of semiconductor devices. The purpose of the present invention is to provide a semiconductor device that is very effective in the following.
本発明は、シリコン基板上に形成された絶縁膜
上の第1多結晶シリコンにより構成された第1抵
抗体群と、前記第1の多結晶シリコンと絶縁膜を
介して形成された第2の多結晶シリコンより構成
された第2抵抗体群を有し、第1抵抗体群の間に
それぞれ第2抵抗体群を形成したことを特徴とす
る半導体装置にある。 The present invention includes a first resistor group made of first polycrystalline silicon on an insulating film formed on a silicon substrate, and a second resistor group made of first polycrystalline silicon on an insulating film formed on a silicon substrate; A semiconductor device includes a second resistor group made of polycrystalline silicon, and each second resistor group is formed between the first resistor groups.
以下実施例を用いて本発明を詳細に説明する。 The present invention will be explained in detail below using Examples.
本発明は第1抵抗体層とするべき第1多結晶シ
リコンと、第2抵抗体層とするべき第2多結晶シ
リコンを組合せることにより半導体装置の面積を
大幅に減小すると伴に合成抵抗体の製造に対する
変動に対し感度を最小限にできることを特徴とす
るものであり、その第1の実施例の説明図を第1
図aおよびbに示す。第1図aは本発明の第1の
実施例の平面図、第1図bは第1図aにおけるX
−X′断面の断面図をそれぞれ示す。 The present invention significantly reduces the area of a semiconductor device by combining a first polycrystalline silicon to be used as a first resistor layer and a second polycrystalline silicon to be used as a second resistor layer, and the combined resistance It is characterized by being able to minimize sensitivity to variations in body manufacturing, and an explanatory diagram of the first embodiment is shown in Figure 1.
Shown in Figures a and b. FIG. 1a is a plan view of the first embodiment of the present invention, and FIG. 1b is a top view of the first embodiment of the present invention.
-X' cross-sectional views are shown respectively.
第1図において、シリコン基板10の上に熱酸
化等により形成された酸化膜8の上に形成された
第1多結晶シリコン単位抵抗5および第1多結晶
シリコン単位抵抗を写真触刻技術等を用いてパタ
ーン化し熱酸化等で酸化膜9を形成する。更に第
2多結晶シリコン単位抵抗を前記第1多結晶シリ
コン単位抵抗と同様に形成する。しかる後に、コ
ンタクト7を開け、引き出し導体1,2および3
と相互接続導体4により構成された2本の抵抗の
一実施例である。なお、第1図の説明において第
1および第2多結晶シリコンに不純物拡散を行う
との説明が省略してあるが、これは行なつても良
いし行なわなくても良い。ただし、CR時定数を
制御するためには不純物拡散を行うのが通常であ
る。 In FIG. 1, a first polycrystalline silicon unit resistor 5 formed on an oxide film 8 formed on a silicon substrate 10 by thermal oxidation or the like and a first polycrystalline silicon unit resistor are formed by photolithography or the like. The oxide film 9 is formed by patterning using a thermal oxidation method or the like. Furthermore, a second polycrystalline silicon unit resistor is formed in the same manner as the first polycrystalline silicon unit resistor. After that, open contact 7 and connect lead conductors 1, 2 and 3.
This is an example of two resistors constructed by an interconnection conductor 4 and an interconnection conductor 4. Although the description of FIG. 1 omits the explanation that impurity diffusion is performed in the first and second polycrystalline silicon, this may or may not be performed. However, in order to control the CR time constant, impurity diffusion is usually performed.
第1図の如き構成とすることにより、従来、多
結晶シリコンを写真触刻技術等を用いて形成する
際に多結晶シリコンのひげ等による短絡を防ぐた
めに必要とされる間隔が必要なくなり、半導体装
置の面積を大きくとる必要がないことは明らかで
ある。 By adopting the configuration shown in Fig. 1, the spacing that was conventionally required to prevent short circuits due to whiskers of polycrystalline silicon when forming polycrystalline silicon using photoengraving technology, etc. is no longer required, and the semiconductor It is clear that there is no need for the device to occupy a large area.
すなわち、第1多結晶シリコンを写真触刻技術
等で形成した後、酸化膜を形成し、第2多結晶シ
リコンを形成するため、第1多結晶シリコンと第
2多結晶シリコン間に電気的導通は生じず、この
ため、同一面積内に約2倍の抵抗を作ることが可
能となる。この説明のため第1図bがあり、第1
多結晶シリコンと第2多結晶シリコンの間には酸
化膜が介在するため、電気的導通は生じない。 That is, after forming the first polycrystalline silicon by photolithography or the like, an oxide film is formed to form the second polycrystalline silicon, so that electrical conduction is established between the first polycrystalline silicon and the second polycrystalline silicon. Therefore, it is possible to create approximately twice as much resistance within the same area. For this explanation, there is Figure 1b.
Since there is an oxide film between the polycrystalline silicon and the second polycrystalline silicon, no electrical conduction occurs.
更に、第1多結晶シリコンおよび第2多結晶シ
リコンにそれぞれ不純物を拡散したときを考えて
みても、不純物拡散の変動により生ずるそれぞれ
の層抵抗の変化は独立に生ずるものの、引き出し
導体1および2間に形成される合成抵抗の抵抗値
と、引き出し導体2および3間に形成される合成
抵抗の抵抗値との比は、それぞれの合成抵抗を形
成している第1および第2多結晶シリコンの単位
抵抗の本数がそれぞれ等しいため、層抵抗の変化
に対しても、抵抗値の比は一定に保たれることに
なる。 Furthermore, even if we consider the case where impurities are diffused into the first polycrystalline silicon and the second polycrystalline silicon, although the changes in the layer resistance caused by the fluctuations in impurity diffusion occur independently, the difference between the lead conductors 1 and 2 The ratio of the resistance value of the combined resistance formed between the lead conductors 2 and 3 to the resistance value of the combined resistance formed between the lead conductors 2 and 3 is determined by the unit of the first and second polycrystalline silicon forming each combined resistance. Since the number of resistors is the same, the ratio of resistance values remains constant even when layer resistance changes.
このため、第1および第2多結晶シリコンに拡
散する不純物量が第1多結晶シリコンと第2多結
晶シリコンで相異している場合においても、合成
抵抗の抵抗値比は一定に保たれるのは明らかであ
ろう。 Therefore, even if the amount of impurities diffused into the first and second polycrystalline silicon is different between the first polycrystalline silicon and the second polycrystalline silicon, the resistance value ratio of the combined resistance is kept constant. It should be obvious.
なお本発明の第1の実施例の説明図は一例とし
て示したものであり、それぞれの合成抵抗を形成
する第1および第2多結晶シリコンによる単位抵
抗が同数であれば第1および第2多結晶シリコン
単位抵抗の本数は何本であつても良い。 Note that the explanatory diagram of the first embodiment of the present invention is shown as an example, and if the number of unit resistors formed by the first and second polycrystalline silicon forming each composite resistance is the same, the first and second polycrystalline silicon will be the same. The number of crystalline silicon unit resistors may be any number.
第2図は本発明の第2の実施例の平面図による
説明図である。第2図は第1図と比較して合成抵
抗体間の抵抗値比を大きくするのに適したもので
ある。 FIG. 2 is an explanatory plan view of a second embodiment of the present invention. FIG. 2 is suitable for increasing the resistance value ratio between the composite resistors compared to FIG. 1.
第2図は引き出し導体11および12の間の合
成抵抗を第1多結晶シリコンの第1単位抵抗15
と第2多結晶シリコンの第1単位抵抗16を相互
接続導体とコンタクト19により相互接続したも
のと、第1多結晶シリコンの第2単位抵抗17と
第2多結晶シリコンの第2単位抵抗18をコンタ
クト20と相互接続導体14により引き出し導体
12および13の間に合成抵抗を構成した一例で
ある。 FIG. 2 shows the combined resistance between the lead conductors 11 and 12 as a first unit resistance 15 made of first polycrystalline silicon.
and a first unit resistor 16 of second polycrystalline silicon interconnected by an interconnect conductor and a contact 19, a second unit resistor 17 of first polycrystalline silicon, and a second unit resistor 18 of second polycrystalline silicon. This is an example in which a combined resistance is constructed between the lead conductors 12 and 13 by the contact 20 and the interconnection conductor 14.
本発明の第2の実施例は前記第1の実施例の利
点を受けづぐとともに、合成抵抗間の抵抗値比の
精度は若干低下するものの抵抗値比の大きな抵抗
を第1の実施例と比較して、より小さな面積に実
現できるものであり、抵抗値比の大きな抵抗が必
要な際に非常に有効な手段を提供するものであ
る。 The second embodiment of the present invention inherits the advantages of the first embodiment, and uses resistors with a large resistance value ratio compared to the first embodiment, although the accuracy of the resistance value ratio between the combined resistors is slightly lowered. In comparison, it can be realized in a smaller area and provides a very effective means when a resistor with a large resistance value ratio is required.
以上図面を用いて詳細に説明した如く、本発明
の実施例を用いれば、集積度の高く、比精度の優
れた半導体装置が実現でき半導体装置の応用分野
の拡大に有効である。 As described above in detail with reference to the drawings, by using the embodiments of the present invention, a semiconductor device with a high degree of integration and excellent relative accuracy can be realized, which is effective in expanding the field of application of semiconductor devices.
第1図aおよびbは本発明の第1の実施例の平
面説明図および断面説明図、第2図は本発明の第
2の実施例の平面説明図をそれぞれ示す。
1,2,3,11,12,13……引き出し導
体、4,14……相互接続導体、5……第1多結
晶シリコン単位抵抗、6……第2多結晶シリコン
単位抵抗、7,19,20……コンタクト、8,
9,21……酸化膜、10……シリコン基板、1
5……第1多結晶シリコンの第1単位抵抗、16
……第2多結晶シリコンの第1単位抵抗、17…
…第1多結晶シリコンの第2単位抵抗、18……
第2多結晶シリコンの第2単位抵抗。
1A and 1B show a plan view and a cross-sectional view of a first embodiment of the present invention, and FIG. 2 shows a plan view of a second embodiment of the present invention. 1, 2, 3, 11, 12, 13... Leading conductor, 4, 14... Interconnecting conductor, 5... First polycrystalline silicon unit resistance, 6... Second polycrystalline silicon unit resistance, 7, 19 ,20...Contact,8,
9, 21...Oxide film, 10...Silicon substrate, 1
5...First unit resistance of first polycrystalline silicon, 16
...First unit resistance of second polycrystalline silicon, 17...
...Second unit resistance of first polycrystalline silicon, 18...
a second unit resistance of second polycrystalline silicon;
Claims (1)
の多結晶シリコンにより形成された複数の第1抵
抗体と、前記絶縁層上にそれぞれ第2の多結晶シ
リコンにより形成された複数の第2抵抗体とを有
し、前記第1および第2の抵抗体は絶縁膜を介し
て交互に配置され、所定数の第1抵抗体とこれと
同数の第2抵抗体とでなる合成抵抗値を有する第
1の抵抗ならびに所定数の他の第1抵抗体とこれ
と同数の他の第2抵抗体とでなる合成抵抗値を有
する第2の抵抗が形成されていることを特徴とす
る半導体装置。1. Each first layer is placed on the insulating layer covering the silicon substrate.
a plurality of first resistors formed of polycrystalline silicon; and a plurality of second resistors each formed of second polycrystalline silicon on the insulating layer; The resistors are arranged alternately with insulating films interposed therebetween, and include a first resistor having a composite resistance value consisting of a predetermined number of first resistors and the same number of second resistors, and a predetermined number of other first resistors. 1. A semiconductor device characterized in that a second resistor is formed having a composite resistance value consisting of a resistor and the same number of other second resistors.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4847882A JPS58164257A (en) | 1982-03-25 | 1982-03-25 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4847882A JPS58164257A (en) | 1982-03-25 | 1982-03-25 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58164257A JPS58164257A (en) | 1983-09-29 |
JPH0225259B2 true JPH0225259B2 (en) | 1990-06-01 |
Family
ID=12804487
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4847882A Granted JPS58164257A (en) | 1982-03-25 | 1982-03-25 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58164257A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6060760A (en) * | 1997-08-13 | 2000-05-09 | Tritech Microelectronics, Ltd. | Optimal resistor network layout |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51150286A (en) * | 1975-06-18 | 1976-12-23 | Matsushita Electric Ind Co Ltd | Production method of semiconductor device |
-
1982
- 1982-03-25 JP JP4847882A patent/JPS58164257A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51150286A (en) * | 1975-06-18 | 1976-12-23 | Matsushita Electric Ind Co Ltd | Production method of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS58164257A (en) | 1983-09-29 |
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