JPS58207664A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58207664A JPS58207664A JP9061282A JP9061282A JPS58207664A JP S58207664 A JPS58207664 A JP S58207664A JP 9061282 A JP9061282 A JP 9061282A JP 9061282 A JP9061282 A JP 9061282A JP S58207664 A JPS58207664 A JP S58207664A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- oxide film
- resistor
- semiconductor device
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Analogue/Digital Conversion (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は抵抗回路網を備えてなる半導体装置に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including a resistor network.
近年、半導体装置の応用分野の拡大はめざましいものが
あり、従来個別部品、または調整技術を用いて十分な精
度が必要とされる分野へと急速に浸透している。In recent years, the field of application of semiconductor devices has been expanding at a remarkable rate, and they are rapidly penetrating into fields that require sufficient precision using conventional individual components or adjustment techniques.
このような−例として、アナログ信号をデジタル信号に
変換するアナログ・デジタル変換信号処理の分野につい
て考えてみると、アナログの如き時間連続信号をサンプ
リングすることに時間離散信号（パルス振幅変調）とな
しだ彼、振幅を劃−予信することＫよりデジタル信号に
変換することになる。このため、アナログ・デジタル変
換回路には当然サンプル・ホールド回路が必要となる。As an example, consider the field of analog-to-digital conversion signal processing, which converts analog signals to digital signals. However, by predicting the amplitude, it is converted into a digital signal. Therefore, the analog-to-digital conversion circuit naturally requires a sample-and-hold circuit.
アナログ信号をある周期でサンプル・ホールドしデジタ
ル信号に変換する際には、その変換系の精度を確保する
ために折り返し歪防止用フィルタを用いて入力されるア
ナログ信号の帯域制限が必要となる。When sampling and holding an analog signal at a certain period and converting it into a digital signal, it is necessary to limit the band of the input analog signal using an aliasing distortion prevention filter in order to ensure the accuracy of the conversion system.
例えば４ Ｋ、 Ｈｚのアナログ信号をデジタル信号に
変換するときには、サンプリング定理により、サンプリ
ング周期は１２５μｓｅｃ （サンプリング周波数８
Ｋ Ｈｚに相当）が最小周期となる。すなわち、折り返
し歪をさけるためには、入力されるアナログ信号に対し
て帯域制限することが必要である。For example, when converting a 4 K, Hz analog signal to a digital signal, the sampling period is 125 μsec (sampling frequency 8
kHz) is the minimum period. That is, in order to avoid aliasing distortion, it is necessary to band limit the input analog signal.
この目的のため、半導体装置として用いられてきた技術
は、多結晶シリコンまたは拡散抵抗を抵抗体として用い
、絶縁体をｉｔ体として用いた容量により、半導体基板
上に（、Ｒフィルタを構成するのが通常であった。For this purpose, the technology used for semiconductor devices is to use polycrystalline silicon or a diffused resistor as a resistor and an insulator as an IT body. was the norm.
ＣＲ時定数を太きクシ、フィルタの動作周波数を低周波
領域まで拡けるためには、抵抗体の抵抗値几を大きくす
るか、容量Ｃを大きくするしかないことは明らかである
。It is clear that the only way to increase the CR time constant and extend the operating frequency of the filter to a low frequency range is to increase the resistance value of the resistor or increase the capacitance C.
従来、この目的のためには抵抗体の面８Ｉを太くとり抵
抗値を太きぐするか、容′Ｍ、面積を大きくする等が考
えられ、半導体面積を大きくとることが多裂であった。Conventionally, for this purpose, it has been considered to increase the resistance value by increasing the resistance value by increasing the surface 8I of the resistor, or to increase the capacity and area, and increasing the semiconductor area has been considered.
これをさけるためには、多結晶シリコンに拡散する不純
物量を少なくした抵抗体が考えられるが、このような抵
抗体のノート抵抗は非常に大きな値となり、この変動を
制御するのは容易ではない。単位容重”値を大きくする
ことけ容通誘電体の膜厚を薄くすれは可能であるが製造
時の誤差を考えればおのずから太きぐすることに限界が
あった。To avoid this, a resistor with a reduced amount of impurities diffused into polycrystalline silicon can be considered, but the node resistance of such a resistor becomes a very large value, and it is not easy to control this fluctuation. . Although it is possible to increase the unit volume and reduce the thickness of the conductive dielectric, there is a limit to how thick it can be made considering manufacturing errors.
また、０ＭＯ８等で使用されるＰウェル、Ｎウェル等の
仙域を用した抵抗体も考えられるが、これらの抵抗体は
電圧対抵抗イ１への係数が大きいこと、捷た接合容針が
大きいため、周波数特性が劣化する欠点を有していた。In addition, resistors using sacrum regions such as P-well and N-well used in 0MO8 etc. are also considered, but these resistors have a large coefficient of voltage vs. resistance (1), and a broken junction capacitance needle. Because of its large size, it had the disadvantage of deteriorating frequency characteristics.
本発明はかかる欠点のない、半導体面積を最小となし、
比粘度の優れた朴抗体を複数の多結晶シリコンを用いて
構成することが可能となり、半導体装置の応用分野の拡
大に非常に有効である。The present invention is free from such drawbacks, minimizes semiconductor area,
It is now possible to construct a block antibody with excellent specific viscosity using multiple polycrystalline silicones, which is extremely effective in expanding the field of application of semiconductor devices.
本発明による半導体装置はシリコン基板上に形成された
絶縁膜上の第１多結晶ンリコンにより構成された第１だ
行抵抗体と、前記第１の多結晶シリコンと絶縁膜を介し
て形成された第２の多結晶シリコンにより構成された第
２のだ行抵抗体が、それぞれ直線部分で相互に隣接して
おり、だ行部分で絶縁膜を介して隼なることを特徴とす
る。A semiconductor device according to the present invention includes a first resistor made of a first polycrystalline silicon on an insulating film formed on a silicon substrate, and a first resistor formed by interposing the first polycrystalline silicon and the insulating film. The second stray resistors made of second polycrystalline silicon are adjacent to each other in their linear portions, and are separated at their stray portions with an insulating film interposed therebetween.
以下実施例を昂いて本発明の詳細な説明する。The present invention will be described in detail below with reference to Examples.
本発明は第１抵抗体層とするべき第１多結晶シリコンと
、第２抵抗体層とするべき第２多結晶シリコンを組合せ
ることにより半導体装置の面積を大幅に減小すると伴に
合成抵抗体の製造に対する変動に対し感度を最小限にで
きることを特徴とするものであり、その第１の実施例の
説明図を第１図（ａ）および（ｂ）に示す。第１図（ａ
）は本発明の第１の実施例の平面図、第１図（ｂ）は第
１図（ａ）におけるＸＸ′断面図をそれぞれ示す。The present invention significantly reduces the area of a semiconductor device by combining a first polycrystalline silicon to be used as a first resistor layer and a second polycrystalline silicon to be used as a second resistor layer, and the combined resistance The first embodiment is characterized by being able to minimize sensitivity to variations in body manufacturing, and FIGS. 1(a) and 1(b) are explanatory diagrams of a first embodiment thereof. Figure 1 (a
) shows a plan view of the first embodiment of the present invention, and FIG. 1(b) shows a sectional view taken along line XX' in FIG. 1(a).
第１図において、シリコン基板９の上に熱酸化等により
形成された酸化膜８の上に形成された第１多結晶シリコ
ン抵抗体６および第１多結晶シリコン折抗体を写真蝕刻
技術等を用いてパターン化し熱酸化等で酸化膜を形成す
る。更に第２多結晶シリコン抵抗体を前記第１多結晶シ
リコン担抗体と同様に形成する。しかる後に、コンタク
ト３および４を開け、引き出し導体１および２と相互接
続導体５により構成された抵抗の一実施例である。In FIG. 1, a first polycrystalline silicon resistor 6 and a first polycrystalline silicon folded body are formed on an oxide film 8 formed on a silicon substrate 9 by thermal oxidation or the like using photolithography or the like. pattern and form an oxide film by thermal oxidation or the like. Furthermore, a second polycrystalline silicon resistor is formed in the same manner as the first polycrystalline silicon carrier. Thereafter, contacts 3 and 4 are opened and an example of a resistor constituted by lead-out conductors 1 and 2 and interconnect conductor 5.
なお、第１図の説明において第１および第２多結晶シリ
コンに不純物拡散を行うとの説明が省略しであるが、こ
れは行なっても良いし行なわなくても良い。ただし、Ｃ
Ｒ時定数を制御するためには不純物拡散を行うのが通常
である。In the explanation of FIG. 1, the explanation that impurity diffusion is performed in the first and second polycrystalline silicon is omitted, but this may or may not be performed. However, C
In order to control the R time constant, impurity diffusion is usually performed.
第１図の如き構成とすることにより、従来、多結晶７リ
コンを写真蝕刻技術等を用いて形成する際に多結晶シリ
コンのひげ等による短絡を防ぐために必要とされる間隔
が必要なくなり、半導体装置の面積を大きくとる必要が
ないことは明らかである０
すなわち、第１多結晶シリコンを写真蝕刻技術等で形成
した稜、酸化膜を形成し第２多結晶シリコンを形成する
ため、第１多結晶シリコンと第２多結晶シリコン間に電
気的導通は生じず、このため、同一面積に約２倍の抵抗
を作ることができる。By adopting the configuration shown in Fig. 1, the spacing required to prevent short circuits due to whiskers of polycrystalline silicon when forming polycrystalline 7 silicon using photoetching technology is no longer necessary, and the It is clear that there is no need to increase the area of the device. No electrical conduction occurs between the crystalline silicon and the second polycrystalline silicon, and therefore approximately twice the resistance can be created in the same area.
この説明として第１図（ｂ）があり、第１多結晶シリコ
ンと第２多結晶シリコンの間には酸化膜１０が介在する
ため、電気的導通は生じない。As an explanation of this, FIG. 1(b) shows that since the oxide film 10 is interposed between the first polycrystalline silicon and the second polycrystalline silicon, no electrical conduction occurs.
なお本発明の第一の実施例の説明図においては、第１多
結晶／リコン抵抗体と第２の多結晶シリコン抵抗体の酸
化膜１０を介して５＋ｉなりあう部分が引出し導体１お
よび２の付近に位置しているが、このため本発明の第１
の実施例は比較的低周波数領域の使用に適している。と
いうのは、第１多結ｄ＾シリコン抵抗体と第２多結晶ン
リコン抵抗体は酸化膜１０を介した容量を持つためであ
る。In the explanatory diagram of the first embodiment of the present invention, the 5+i portions of the first polycrystalline/recon resistor and the second polycrystalline silicon resistor through the oxide film 10 correspond to the lead-out conductors 1 and 2. Although it is located nearby, this is why the first aspect of the present invention
The embodiment is suitable for use in the relatively low frequency range. This is because the first polycrystalline silicon resistor and the second polycrystalline silicon resistor have a capacitance via the oxide film 10.
第２図は本発明の第２の実施例の平面図による説明図で
ある。第２図において第１図（ａ）と同じ個所は同じ番
号を用いている。FIG. 2 is an explanatory plan view of a second embodiment of the present invention. In FIG. 2, the same parts as in FIG. 1(a) are designated by the same numbers.
第２図は第１図（ａ）における相互接続導体５および引
き出し導体２を変更したものである。FIG. 2 shows a modification of the interconnection conductor 5 and lead-out conductor 2 in FIG. 1(a).
第２図の如き接続を用いることにより、第１多結晶シリ
コンと第２多結晶シリコンの酸化膜１０を介した容量は
それぞれ引き出し導体１および２に対し等間隔で入るだ
め、第１の実施例と比較して、より高周波領域までの応
用に適している。By using the connection as shown in FIG. 2, the capacitances of the first polycrystalline silicon and the second polycrystalline silicon through the oxide film 10 can be applied to the lead-out conductors 1 and 2 at equal intervals. Compared to , it is suitable for applications up to higher frequency ranges.
ただし、第１および第２の実施例とも、多結晶シリコン
抵抗体はシリコン基板９と酸化膜８を介して分布容ｉｔ
が付加されるため、例えば１ＭＬ１ｚ以上の応用に対し
ては、シリコン基板との各州も考慮することが必要とな
るのは明らかであろう。However, in both the first and second embodiments, the polycrystalline silicon resistor has a distribution capacity it through the silicon substrate 9 and the oxide film 8.
It is obvious that, for example, for applications of 1ML1z or more, it is necessary to consider each state with the silicon substrate.
なお本発明の第１および第２の実施例において、第１多
結晶ンリコン抵抗体と第２多結晶シリコン抵抗体のだ行
数は７回で説明しであるが、本発明の実施に当っては形
状、だ行数によらず、第１多結晶シリコン抵拐体と第２
多結晶抵抗体を隣拌して形成することにあり、特に供用
波数領域の応用に熱しては、第１多結晶シリコン担抗体
と第２多結晶シリコン抵抗体が互に沖なり合うように形
成することも可能である。In the first and second embodiments of the present invention, the number of lines of the first polycrystalline silicon resistor and the second polycrystalline silicon resistor is described as seven times, but in implementing the present invention, The first polycrystalline silicon resistor and the second polycrystalline resistor are
The purpose of this method is to form polycrystalline resistors by mixing them next to each other, and especially for applications in the commercial wavenumber region, the first polycrystalline silicon carrier and the second polycrystalline silicon resistor are formed so as to be offset from each other. It is also possible to do so.
以上図面を用い−Ｃ詳細に説明し７た如く、本発明を用
いれば、第１および第２多結晶シリコン抵抗体をだ行（
７て用いることにより、集積度の高い、製造眼差の少な
い十梼体装（紅が実現でき、半導体装置の応用分野の拡
大に有効である。As described above in detail with reference to the drawings, if the present invention is used, the first and second polycrystalline silicon resistors can be
By using this method, it is possible to achieve a high degree of integration and a small manufacturing tolerance, which is effective in expanding the field of application of semiconductor devices.
第１図（ａ）および（ｂ）は本発明の第１の実施例の平
面説明図および断面説明図、第２図は本発明の第２の実
施例の平面説明図をそれぞれ示す。
１．２．１２・・・・引出し導体、３，４，１３゜１４
・・・・・・コンタクト、６・・・・・・第１多結晶シ
リコン抵抗体、７・・・・・・第２多結晶シリコン抵抗
体、５゜１５°°°・・・相互接続導体、８・・・・・
・酸化膜、９・・・・・・シリコン基板、１０・・・・
・酸化膜。
′・−二、ン、１
代理人 弁理士 内 原 ヨ １（イ）１
図 （ａ−）
第 １ 図 （ｂ）FIGS. 1A and 1B are a plan view and a cross-sectional view of a first embodiment of the present invention, and FIG. 2 is a plan view of a second embodiment of the present invention. 1.2.12...Output conductor, 3, 4, 13゜14
... Contact, 6 ... First polycrystalline silicon resistor, 7 ... Second polycrystalline silicon resistor, 5゜15°°゜ ... Interconnection conductor , 8...
・Oxide film, 9...Silicon substrate, 10...
·Oxide film. '・-2, n, 1 Agent Patent attorney Uchihara Yo 1 (a) 1
Figure (a-) Figure 1 (b)
Claims (1)
コンにより構成された第１だ行抵抗体と、前記第１の多
結晶シリコンと絶縁膜を介して形式された第２の多結晶
シリコンにより構成された第２のだ行抵抗体が、それぞ
、れ直線部分で相互に隣接１．ており、だ行部分で絶縁
膜を介してｌなることを特徴とする半導体装置。A first row resistor made of first polycrystalline silicon on an insulating film formed on a silicon substrate, and a second polycrystalline silicon formed through the first polycrystalline silicon and the insulating film. The second extending resistors configured by 1. 1. A semiconductor device characterized in that the diagonal portions are connected to each other with an insulating film interposed therebetween.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9061282A JPS58207664A (en) | 1982-05-28 | 1982-05-28 | Semiconductor device |
| US06/498,030 US4620212A (en) | 1982-05-28 | 1983-05-25 | Semiconductor device with a resistor of polycrystalline silicon |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9061282A JPS58207664A (en) | 1982-05-28 | 1982-05-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58207664A true JPS58207664A (en) | 1983-12-03 |
Family
ID=14003299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9061282A Pending JPS58207664A (en) | 1982-05-28 | 1982-05-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58207664A (en) |
-
1982
- 1982-05-28 JP JP9061282A patent/JPS58207664A/en active Pending
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