JPH0225100A - Method of wiring multilayer printed board - Google Patents
Method of wiring multilayer printed boardInfo
- Publication number
- JPH0225100A JPH0225100A JP17602488A JP17602488A JPH0225100A JP H0225100 A JPH0225100 A JP H0225100A JP 17602488 A JP17602488 A JP 17602488A JP 17602488 A JP17602488 A JP 17602488A JP H0225100 A JPH0225100 A JP H0225100A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- signal
- patterns
- board
- multilayer printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title abstract description 15
- 239000010410 layer Substances 0.000 abstract description 14
- 239000000919 ceramic Substances 0.000 abstract description 4
- 239000002344 surface layer Substances 0.000 abstract description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【発明の詳細な説明】
［概 要〕
各種電子機器に広く使用される多層プリント基板の配線
方法に関し、
それぞれの配線回路に複数本のパターンを設けて信号パ
ターンの断面積を大きくすることを目的とし、
一定の板厚に積層する信号層内部の指定経路に、〔産業
上の利用分野〕
本発明は、各種電子機器に広く使用される多層プリント
基板の配線方法に関する。[Detailed Description of the Invention] [Summary] Regarding the wiring method for multilayer printed circuit boards widely used in various electronic devices, the purpose is to increase the cross-sectional area of the signal pattern by providing multiple patterns in each wiring circuit. [Field of Industrial Application] The present invention relates to a wiring method for multilayer printed circuit boards widely used in various electronic devices.
最近特に、各種電算機等のプリント板に実装される半導
体チップは、ますます高集積化されて入出力端子が微小
ピッチで高密度に配列されるとともに高密度実装が要求
されており、それに伴ってプリント配線基板（以下基板
と略記する）は微細化された配線パターンを高密度に形
成されている。Recently, in particular, semiconductor chips mounted on printed circuit boards of various computers, etc., have become increasingly highly integrated, with input/output terminals arranged at minute pitches and densely arranged, and high-density mounting is required. A printed wiring board (hereinafter abbreviated as a board) has fine wiring patterns formed at high density.
そのため、配線パターンの直流抵抗が大きくなって伝送
する信号波形に悪影嘗を与えているので、配線パターン
の断面積を大きくして直流抵抗が少なくなる新しい多層
プリント基板の配線方法が必要とされている。As a result, the DC resistance of the wiring pattern increases, which has an adverse effect on the signal waveform being transmitted.Therefore, a new multilayer printed circuit board wiring method is needed that increases the cross-sectional area of the wiring pattern and reduces the DC resistance. ing.
従来広く使用されている多層プリント基板、第２図の断
面図に示すように信号用のパターン４−１を印刷したセ
ラミックを積層して板厚“Ｔ”例えば１．８Ｎに形成し
た信号層４の両面に、電源供給用のグランド層３ （以
下ＧＮＤ層と略記する）を介して表面層２を積層してい
る。A multilayer printed circuit board that has been widely used in the past includes a signal layer 4 formed by laminating ceramics printed with a signal pattern 4-1 to a thickness "T" of, for example, 1.8N, as shown in the cross-sectional view of Fig. 2. A surface layer 2 is laminated on both sides of the substrate with a ground layer 3 (hereinafter abbreviated as GND layer) for power supply interposed therebetween.
その基板の配線方法は、例えば第３図の平面図に示すよ
うに表面層２の主面中央部に半導体チップ等の電子部品
１に配設された入出力端子、或いはその電子部品１を装
着するｉＣソケットのリード端子と接合する接合パッド
２−１を配設して、基板の外周縁に外部と接続する接続
端子２−２を配列し、点線で示すパターン４−１と図示
していないＶＩＡにより接合バンド２−１と接続端子２
．２を接続している。The wiring method for the board is, for example, as shown in the plan view of FIG. A bonding pad 2-1 to be bonded to a lead terminal of an iC socket is arranged, and connection terminals 2-2 to be connected to the outside are arranged on the outer periphery of the board, and a pattern 4-1 shown by a dotted line and a pattern not shown (not shown) are arranged. Connecting band 2-1 and connecting terminal 2 by VIA
．． 2 is connected.
そのパターン４−１は、第２図の断面図に示すように幅
、Ｗ＝２００μｍｘ厚み、ｔ＝２０ｐｍＯ）導体で形成
され、その導体中心が信号層４の板厚中心面、即ち両面
のＧＮＤ層３より０．９鶴となる面に配線されて、導体
のインピーダンスが整合するように構成している。The pattern 4-1 is formed of a conductor (width: W=200 μm x thickness: t=20 pm), as shown in the cross-sectional view of FIG. The conductor is wired on a plane with an angle of 0.9 from layer 3, so that the impedance of the conductor is matched.
以上説明した従来の配線方法で問題となるのは、配線密
度が高密度化されるに従って接合パッドと導通ずるパタ
ーンの幅“Ｗ”がますます微細となり、それに伴ってパ
ターンの断面積が小さくなるので直流抵抗が大きくなる
ので、パターンにより伝送する信号パルスの立ち上がり
時間（ｒｉｓｅ ｔｉｍｅ）と立ち下がり時間（ｆａｌ
ｌ ｔｉｍｅ）が長くなって、伝送信号の特性が低下す
るという問題が生じる。The problem with the conventional wiring method described above is that as the wiring density increases, the width "W" of the pattern that conducts with the bonding pad becomes smaller and smaller, and the cross-sectional area of the pattern becomes smaller. Therefore, the DC resistance increases, so the rise time and fall time of the signal pulse to be transmitted depends on the pattern.
A problem arises in that the transmission signal characteristics (l time) become longer and the characteristics of the transmission signal deteriorate.
そのため、パターンの厚みを大きくして断面積を増加す
ることにより直流抵抗の増大を抑える方法が考えられる
が、製造プロセス上あまり厚くすることが不可能である
という問題が生じている。Therefore, a method of suppressing the increase in DC resistance by increasing the cross-sectional area by increasing the thickness of the pattern has been considered, but the problem arises that it is impossible to increase the thickness too much due to the manufacturing process.
本発明は上記のような問題点に鑑み、それぞれの配線回
路に複数本のパターンを設けて信号パターンの断面積を
大きくすることができる多層プリント基板の配線方法の
提供を目的とする。In view of the above-mentioned problems, the present invention aims to provide a wiring method for a multilayer printed circuit board that can increase the cross-sectional area of a signal pattern by providing a plurality of patterns in each wiring circuit.
本発明は、第１図に示すように一定の板厚に積層する信
号層１４内部の指定経路に、微細幅で断面図寸法が同一
の第一パターン１４−１と第二パターン１４−２を、板
厚の中心面に対して一定の間隔でそれぞれ対向するよう
に配線し、図示していないＶＩＡにより第一パターン１
４−１と第二パターン１４−２を接続して、基板主面に
配設して接合パッドおよび接続端子と導通するように形
成される。As shown in FIG. 1, the present invention provides a first pattern 14-1 and a second pattern 14-2 having a fine width and the same cross-sectional dimensions in a specified path inside the signal layer 14 which is laminated to a constant thickness. , are wired so as to face each other at a constant interval with respect to the center plane of the plate thickness, and the first pattern 1 is formed by a via (not shown).
4-1 and the second pattern 14-2 are connected and arranged on the main surface of the substrate so as to be electrically connected to the bonding pad and the connection terminal.
本発明では、信号層１４内部の指定経路に断面図寸法が
同一の第一パターン１４−１と第二パターン１４−２を
、板厚の中心面に対して一定の間隔でそれぞれ対向する
ように配線しているので、１本の信号回路に２本のパタ
ーンが形成されてその断面積を大きくなり、それに伴っ
てそれぞれの信号回路の直流抵抗が小さくなって伝送す
る信号の特性を高くすることが可能となる。In the present invention, the first pattern 14-1 and the second pattern 14-2, which have the same cross-sectional dimensions, are arranged in a designated path inside the signal layer 14 so as to face each other at a constant interval with respect to the center plane of the plate thickness. Because it is wired, two patterns are formed in one signal circuit, increasing its cross-sectional area, and as a result, the DC resistance of each signal circuit decreases, improving the characteristics of the transmitted signal. becomes possible.
以下図面に示した実施例に基づいて本発明の詳細な説明
する。The present invention will be described in detail below based on embodiments shown in the drawings.
第１図は本実施例による多層プリント基板の配線方法の
断面図を示し、図中において、第２図と同一部材には同
一記号が付しであるが、その他の１４は信号伝送用のパ
ターンを形成する信号層である。FIG. 1 shows a cross-sectional view of the wiring method for a multilayer printed circuit board according to this embodiment. In the figure, the same members as in FIG. 2 are given the same symbols, and the other 14 are patterns for signal transmission. This is the signal layer that forms the
本発明の配線方法は、第１図に示すように従来と同一断
面図寸法、即ち幅：Ｗ＝２００μｍ、厚さ： ｔ＝２
０ｐｍの第一パターン１４−１を、第３図で示す指定経
路で印刷したセラミックよりなる薄板と、同じ（第二パ
ターン１４−２を印刷したセラミック薄板を、第一パタ
ーン１４−１と第二パターン１４２が積層する板厚の中
心面に対して一定間隔；Ｄ＝１５０μｍとなるようにそ
れぞれ対向させて、一定の板厚９例えばＴ ＝ １．８
璽ｍの積層して信号層１４を形成することにより各指
定経路に第一パターン１４−１と第二パターン１４−２
を配線している。As shown in FIG. 1, the wiring method of the present invention has the same cross-sectional dimensions as the conventional one, that is, width: W = 200 μm, thickness: t = 2.
A ceramic thin plate printed with a first pattern 14-1 of 0 pm in the specified path shown in FIG. The patterns 142 are arranged to face each other at a constant interval D = 150 μm with respect to the center plane of the laminated plates, so that the pattern 142 has a constant plate thickness 9, for example, T = 1.8.
By stacking the seals m to form the signal layer 14, a first pattern 14-1 and a second pattern 14-2 are formed on each designated route.
is being wired.
そして、従来と同様に上記信号層１４の両面にＧＮＤｉ
Ｊ３を介して表面Ｎ２を積層し、第３図に示す基板主面
に配設して接合パッドおよび接続端子と、第一パターン
１４−１と第二パターン１４−２を図示していないＶＩ
Ａにより導通するように形成される。Then, as in the conventional case, GNDi is installed on both sides of the signal layer 14.
The surface N2 is laminated via J3, and the bonding pads and connection terminals are arranged on the main surface of the substrate shown in FIG.
It is formed to be electrically conductive by A.
その結果、１本の信号回路に第一パターン１４−１と第
二パターン１４−２を配線しているので、信号用のパタ
ーン断面積を大きくなって直流抵抗が小さくなり、その
パターンで伝送する信号の特性を高くすることができる
。As a result, since the first pattern 14-1 and the second pattern 14-2 are wired in one signal circuit, the cross-sectional area of the signal pattern is increased, the DC resistance is reduced, and transmission is performed using that pattern. Signal characteristics can be improved.
以上の説明から明らかなように本発明によれば極めて簡
単な配線方法で、配線パターンの断面積を大きくなって
直流抵抗が小さくなり、それに伴って伝送する信号の波
形を崩さない等の利点があり、著しい特性向上の効果が
期待できる多層プリント基板の配線方法を提供すること
ができる。As is clear from the above explanation, according to the present invention, the wiring pattern is extremely simple, the cross-sectional area of the wiring pattern is increased, the DC resistance is reduced, and the waveform of the transmitted signal is not distorted. Therefore, it is possible to provide a wiring method for a multilayer printed circuit board that can be expected to significantly improve characteristics.
第１図は本発明の一実施例による多層プリント基板の配
線方法を示す断面図、
第２図は従来の配線方法を示す断面図、第３図は多層プ
リント基板を示す平面図である。
図において、
２は表面層、
３はＧＮＤｉ。
１４は信号層、
１４−１は第一パターン、
１４−２は第二パターン、
を示す。
渉砲月セ丸培例ＩＶｊう層ア！／ ＞ｈ耘ｐａｌ線オ斌
を求ず斯狛図第１図
う屑アワシト」（８乙を７−１斗イ狛の第３図
ヅｒ）丸偽舊乙、む辷オ迂を末丁跡旬０り第２図FIG. 1 is a sectional view showing a wiring method for a multilayer printed circuit board according to an embodiment of the present invention, FIG. 2 is a sectional view showing a conventional wiring method, and FIG. 3 is a plan view showing a multilayer printed circuit board. In the figure, 2 is the surface layer and 3 is GNDi. 14 is a signal layer, 14-1 is a first pattern, and 14-2 is a second pattern. Wandering gun moon semarupai example IVj layer a! ／ ＞H 耘pal line Obin, the first picture of the map is a waste of space.'' Atoshun0ri Figure 2
Claims (1)
に、少なくとも２本の微細幅パターン（１４−１，１４
−２，・・１４−ｎ）がそれぞれ対向するように一定の
間隔で配線し、ＶＩＡにより該パターン（１４−１，１
４−２，・・１４−ｎ）を接続して基板主面と導通する
ことを特徴とする多層プリント基板の配線方法。At least two fine width patterns (14-1, 14
-2, .
4-2, . . . 14-n) to establish conduction with the main surface of the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17602488A JP2580727B2 (en) | 1988-07-13 | 1988-07-13 | Wiring method of multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17602488A JP2580727B2 (en) | 1988-07-13 | 1988-07-13 | Wiring method of multilayer printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0225100A true JPH0225100A (en) | 1990-01-26 |
| JP2580727B2 JP2580727B2 (en) | 1997-02-12 |
Family
ID=16006391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17602488A Expired - Lifetime JP2580727B2 (en) | 1988-07-13 | 1988-07-13 | Wiring method of multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2580727B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5768109A (en) * | 1991-06-26 | 1998-06-16 | Hughes Electronics | Multi-layer circuit board and semiconductor flip chip connection |
| JP2009212116A (en) * | 2008-02-29 | 2009-09-17 | Oki Printed Circuits Co Ltd | Multilayer printed wiring board |
| CN111328185A (en) * | 2020-03-04 | 2020-06-23 | 惠州Tcl移动通信有限公司 | Printed circuit board structure and terminal equipment |
-
1988
- 1988-07-13 JP JP17602488A patent/JP2580727B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5768109A (en) * | 1991-06-26 | 1998-06-16 | Hughes Electronics | Multi-layer circuit board and semiconductor flip chip connection |
| JP2009212116A (en) * | 2008-02-29 | 2009-09-17 | Oki Printed Circuits Co Ltd | Multilayer printed wiring board |
| CN111328185A (en) * | 2020-03-04 | 2020-06-23 | 惠州Tcl移动通信有限公司 | Printed circuit board structure and terminal equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2580727B2 (en) | 1997-02-12 |
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