JPH02249257A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPH02249257A JPH02249257A JP7000289A JP7000289A JPH02249257A JP H02249257 A JPH02249257 A JP H02249257A JP 7000289 A JP7000289 A JP 7000289A JP 7000289 A JP7000289 A JP 7000289A JP H02249257 A JPH02249257 A JP H02249257A
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- mounting
- bonding
- package
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000919 ceramic Substances 0.000 claims abstract description 23
- 239000008188 pellet Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 abstract 1
- 238000007790 scraping Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 abstract 1
- 239000002994 raw material Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 102000004190 Enzymes Human genes 0.000 description 1
- 108090000790 Enzymes Proteins 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000003909 pattern recognition Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15157—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、マイクロ波帯の半導体装置用パッケージに利
用され、特に、ディスクリートデバイス用中空セラミッ
クパッケージである半導体装置用パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is utilized for a microwave band semiconductor device package, and particularly relates to a semiconductor device package that is a hollow ceramic package for a discrete device.
本発明は、セラミック基板上に、ペレットを取り付ける
ペレット部と、このマウント部を挟んで相対向する四つ
のボンディング部とが設けられた半導体装置用パッケー
ジにおいて、
前記マウント部を、前記セラミック基板の前記ボンディ
ング部の内端の内側を四角錐状に削りとった四角錐状凹
部の内部に設けることにより、マウント位置精度の向上
と、ボンディング部へのマウントロー材の流出の防止を
図ったものである。The present invention provides a package for a semiconductor device in which a pellet portion for attaching a pellet to a ceramic substrate and four bonding portions facing each other with the mount portion in between are provided, wherein the mount portion is connected to the bonding portion of the ceramic substrate. By providing it inside a square pyramid-shaped recess that has been cut into a square pyramid shape from the inside of the inner end of the bonding part, it is possible to improve the mounting position accuracy and prevent the mounting raw material from flowing into the bonding part. .
従来、この種の半導体装置用パッケージは、第５図（ａ
）およびら）に示す構造を有しており、セラミック基板
１上にボンディング部３およびマウント部２がメタライ
ズされ、さらに、周囲部にセラミックの側壁５が設けら
れており、ボンデ・イング部３およびマウント部２は、
セラミック基板１上の同一平面に設けられていた。なお
４はリード端子である。Conventionally, this type of semiconductor device package is shown in Fig. 5 (a).
) and ra), in which a bonding part 3 and a mounting part 2 are metallized on a ceramic substrate 1, and a ceramic side wall 5 is provided around the periphery. The mount part 2 is
They were provided on the same plane on the ceramic substrate 1. Note that 4 is a lead terminal.
前述した従来の半導体装置用パッケージでは、本発明の
対象となるマイクロ波帯半導体装置の特−質により、パ
ッケージの外形寸法が制限され、２ｍｌ１１程度の小さ
なものとなるため、ペレットのマウントの際に、作業者
の目測誤り、または、自動マウンターのパターン認識の
ズレにより、マウント位置ズレを起こしたり、マウント
位置のバラツキによるインピーダンスのバラツキを引き
起こしたりしやすい欠点がある。In the conventional semiconductor device package described above, the external dimensions of the package are limited due to the characteristics of the microwave band semiconductor device that is the object of the present invention, and the package is as small as 2 ml11. However, there is a drawback that the mount position may be misaligned due to an operator's visual measurement error or a misalignment in pattern recognition by the automatic mounter, or impedance variation may occur due to variation in the mount position.
さらに、パッケージのマウント部とボンディング部が同
一平面上に形成されであるため、マウント時に、マウン
トロー材のボンディング部への付着を起こしやすい欠点
がある。Furthermore, since the mounting portion and the bonding portion of the package are formed on the same plane, there is a drawback that mounting raw material tends to adhere to the bonding portion during mounting.
本発明の目的は、前記の欠点を除去することにより、マ
ウント位置精度の向上と、ボンディング部へのマウント
ロー材の流出の防止を図った半導体装置用パッケージを
提倶することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a package for a semiconductor device that improves mounting position accuracy and prevents mounting raw material from flowing into a bonding portion by eliminating the above-mentioned drawbacks.
〔問題点を解決するための手段〕
本発明は、セラミック基板上に、ペレットを取り付ける
マウント部と、このマウント部を挟んで相対向する四つ
のボンディング部とが設けられた半導体装置用パッケー
ジにおいて、前記マウント部を、前記セラミック基板の
前記ボンディング部の内端より内側を四角錐状に削りと
った四角錐状凹部の内部に設けたことを特徴とする。[Means for Solving the Problems] The present invention provides a package for a semiconductor device in which a mount portion for attaching a pellet to a ceramic substrate and four bonding portions facing each other across the mount portion are provided. The mount portion is provided inside a quadrangular pyramid-shaped concave portion formed by cutting an inner side of the bonding portion of the ceramic substrate into a quadrangular pyramid shape.
マウント部は、四つのボンディング部の内端より内側を
、四角錐状に削りとった四角錐状凹部の内部に設けられ
る。The mount portion is provided inside a quadrangular pyramid-shaped concave portion formed by cutting the inner side of the four bonding portions into a quadrangular pyramid shape.
従って、前記マウント部にペレットをマウントロー材に
より固着する場合には、ペレットは四角錐の面によりそ
の位置が制限されマウント位置精度が向上される。また
マウントロー材はボンディング部より低い凹部にあるの
で、ボンディング部へ流出することがない。Therefore, when a pellet is fixed to the mount portion by the mounting row material, the position of the pellet is restricted by the square pyramid surface, and the mounting position accuracy is improved. Further, since the mounting raw material is located in the recessed portion lower than the bonding portion, it does not flow out to the bonding portion.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第１図（ａ）は本発明の第一実施例を示す平面図、およ
び第１図（ｂ）はそのＡ−Ａ’断面図である。FIG. 1(a) is a plan view showing a first embodiment of the present invention, and FIG. 1(b) is a sectional view taken along the line AA'.
本実−実施例は、セラミック基板ｌａ上に、ぺ・レフト
を取り付けるＡｕメタライズされたマウント部２ａと、
マウント部２を挟んで相対向する四つのＡｕメタライズ
されたボンディングｆ１３と、このボンディング部３に
Ａｕメタライズ層を介してそれぞれ接続されセラミック
基板１ａの裏面にロー付けされた四つのリード端子４と
、マウント部２とボンディング部３を取り囲んでセラミ
ック基板１上に設けられたセラミックからなる側壁５と
を備えた中空型の半導体装置用パッケージにおいて、マ
ウント部２ａを、セラミック基板１ａのボンディング部
３の内端より内側を四角錐形状に削りとった四角錐状凹
部６の内部に設けである。This practical example includes an Au metalized mount portion 2a for attaching the P-Left on a ceramic substrate la;
Four Au metallized bondings f13 facing each other with the mount part 2 in between; four lead terminals 4 connected to the bonding parts 3 via Au metallized layers and soldered to the back surface of the ceramic substrate 1a; In a hollow semiconductor device package that includes a mount portion 2 and a side wall 5 made of ceramic and provided on a ceramic substrate 1 surrounding the bonding portion 3, the mount portion 2a is placed inside the bonding portion 3 of the ceramic substrate 1a. It is provided inside a square pyramid-shaped recess 6 whose inner side from the end is cut into a square pyramid shape.
本発明の特徴は、第１図（ａ）およびら）に右いて、マ
ウント部２ａをセラミック基板１ａの四角錐状凹部６の
内部に設けたことにある。A feature of the present invention, as shown in FIGS. 1(a) and 1(a), is that the mount portion 2a is provided inside the quadrangular pyramidal recess 6 of the ceramic substrate 1a.
第２図（ａ）およびら）は第１図（ａ）およびら）に示
した第一実施例におけるペレットのマウント済パッケー
ジ本体の平面図および断面図である。マウントロー材７
によりペレット８をマウント部２ａ上にマウントしであ
る。FIGS. 2(a) and 2(a) are a plan view and a sectional view of the pellet mounted package body in the first embodiment shown in FIGS. 1(a) and 1(a). mount low material 7
The pellet 8 is then mounted on the mount portion 2a.
第３図は第２図ら）のマウント部分の拡大断面図であり
、この四角錐状凹部６の底面の形状は、マウントするペ
レット８の底面と相似の形状を有するように形成されて
おり、結果としてペレットをこの四角錐状凹部６上のマ
ウント部２ａにマウントすると、ペレット８表面と、セ
ラミック基板１表面とは平行に保たれることとなり、し
かも、マウント位置は、上方よりの適切な力により、常
に決まった位置となるため、マウント位置精度の向上が
容易となる。FIG. 3 is an enlarged cross-sectional view of the mount part of FIG. When a pellet is mounted on the mount section 2a on the quadrangular pyramidal recess 6, the surface of the pellet 8 and the surface of the ceramic substrate 1 are kept parallel, and the mounting position can be adjusted by an appropriate force from above. , since the position is always fixed, it is easy to improve the mounting position accuracy.
また、この四角錐状凹部６の斜面により、マウント時の
ペレット８をマウント部に押しつけたときの余分なマウ
ントロー材７のボンディング部３への流出を防止するこ
とが容易となる。Further, the slope of the quadrangular pyramidal recess 6 makes it easy to prevent excess mounting raw material 7 from flowing out into the bonding section 3 when the pellet 8 is pressed against the mounting section during mounting.
さらに、本実−実施例においては、マウント済のベレッ
ト８０表面とボンディング部３表面との段差を、従来構
造よりも少なくすることができ、ボンディング作業が容
易となり、しかも、ボンディング線を短くできることに
より、インダクタンスの低減をはかることができる。Furthermore, in this embodiment, the difference in level between the surface of the mounted bullet 80 and the surface of the bonding part 3 can be reduced compared to the conventional structure, making the bonding work easier, and furthermore, the bonding line can be shortened. , it is possible to reduce inductance.
この四角錐状凹部６およびマウント部２ａの寸法は、マ
ウントロー材７の流出防止のため、平面図において、ペ
レット底面の一辺のそれぞれ２倍および１．３倍程度が
適切と考えられる。また、四角錐状凹部６の水平方向に
対する角度は、小さすぎるとマウント位置精度が悪くな
り、大きすぎると、セラミック基板１の衝撃に対する強
度が弱くなるため、３０度程度が適切と考えられる。In order to prevent the mount row material 7 from flowing out, the dimensions of the quadrangular pyramidal recess 6 and the mount portion 2a are considered to be approximately twice and 1.3 times, respectively, one side of the bottom surface of the pellet in a plan view. Furthermore, if the angle of the quadrangular pyramidal recess 6 with respect to the horizontal direction is too small, the mounting position accuracy will deteriorate, and if it is too large, the strength of the ceramic substrate 1 against impact will be weakened, so it is considered appropriate to set the angle to about 30 degrees.
第４図（ａ）は本発明の第二実施例を示す平面図、およ
び第４図（ｂ）はそのＢ−Ｂ’断面図である。FIG. 4(a) is a plan view showing a second embodiment of the present invention, and FIG. 4(b) is a sectional view thereof taken along line BB'.
本第二実施例は、第１図（ａ）および（ｂ）に示した第
一実施例において、セラミック基板１ｂのボンディング
部３の内端より内側の部分に、段状凹部９を設けたもの
である。The second embodiment differs from the first embodiment shown in FIGS. 1(a) and 1(b) in that a stepped recess 9 is provided in a portion inside the inner end of the bonding portion 3 of the ceramic substrate 1b. It is.
本第二実施例では、第一実施例のマウント位置精度およ
び、マウントロー材のボンディング部３への流出防止は
そのまま確保でき、ボンディング作業の容易さ、インダ
クタンスの低減をさらに向上させることができる。In the second embodiment, the mounting position accuracy and prevention of the mounting raw material from flowing into the bonding portion 3 of the first embodiment can be maintained as is, and the ease of bonding work and the reduction of inductance can be further improved.
以上説明したように、本発明は、パッケージ本体の四つ
のボンディング部の内端より内側を、四角錐状に削りと
って四角錐状凹部を形成し、その四角錐状凹部の内部に
マンウド部を設けることにより、マウント位置精度の向
上、およびマウントロー材のボンディング部への流出の
防止に効果がある。As explained above, in the present invention, the inner side of the four bonding parts of the package body is cut into a square pyramid shape to form a square pyramid shaped recess, and the mandrel part is placed inside the square pyramid shaped recess. By providing this, it is effective to improve the mounting position accuracy and prevent the mounting raw material from flowing out to the bonding part.
さらに、マウント部がボンディング部よりも少し低いた
め、結果としてボンディング部とベレット表面との段差
が、従来よりも少なくでき、ボンディングワイヤーが短
くなることによるインダクタンスの低減、および段差が
少ないためのボンディング作業が容易になる効果も得ら
れる。Furthermore, since the mount part is a little lower than the bonding part, the difference in level between the bonding part and the surface of the pellet can be reduced compared to conventional methods, which reduces inductance by shortening the bonding wire, and reduces bonding work because there is less difference in level. It also has the effect of making it easier.
第１図（ａ）および（ｂ）はそれぞれ本発明の第一実施
例を示す平面図およびそのＡ−Ａ’断面図。
第２図（ａ）およびら）はそれぞれ本発明の第一実施例
のベレットマウント済状態を示す平面図およびそのＡ−
Ａ’断面図。
第３図は第２図（ｂ）のマウント部分の拡大断面図。
第４図（ａ）および（ｂ）はそれぞれ本発明の第二実施
例を示す平面図およびそのＢ−Ｂ’断面図。
第５図（ａ）およびら）は従来例を示す平面図およびそ
のｃ−ｃ’断面図。
１．１ａ、１ｂ・・・セラミック基板、２．２ａ・・・
マウント部、３・・・ボンディング部、４・・・リード
端子、５・・・側壁、６・・・四角錐状凹部、７・・・
マウントロー材、８・・・ペレット、９・・・段状凹部
。
（０）平面図
（ｂ）Ａ−Ａ′Ｆｔｒ２［ｆｆ１
９（シｒ〕
（Ｑ）
平面図
（ｂ） Ａ −Ａ’断面図
？へ −笑に６例 （へ・レットＡ≧＋：ｎｉｔ＞肩
２ 回
（０）平面図
ｃｂ）Ｂ −ｄ Ｉ！Ｔ面図
不二夷Ｒ例のａ威
菖 ４ 回
革−災厨例
肩 ３ 図
（へ６し・ｌトマウント酵分）
（ａ）平面口
（＋））
Ｃ−Ｃ’！１７面図
随来例の鷹べ
に ５ 口FIGS. 1(a) and 1(b) are a plan view and an AA' cross-sectional view, respectively, showing a first embodiment of the present invention. FIGS. 2(a) and 2(a) are a plan view showing the first embodiment of the present invention in a bullet-mounted state, and its A-
A' sectional view. FIG. 3 is an enlarged sectional view of the mount portion of FIG. 2(b). FIGS. 4(a) and 4(b) are a plan view and a BB' cross-sectional view, respectively, showing a second embodiment of the present invention. FIGS. 5(a) and 5(a) are a plan view and a sectional view taken along line cc' of the conventional example. 1.1a, 1b...ceramic substrate, 2.2a...
Mount part, 3... Bonding part, 4... Lead terminal, 5... Side wall, 6... Square pyramidal recess, 7...
Mount low material, 8... pellet, 9... stepped recess. (0) Plan view (b) A-A'Ftr2 [ff1 9 (Sir)] (Q) Plan view (b) A-A' sectional view? To - 6 examples (to Let A≧+:nit ＞Shoulder
2 times (0) Plan view cb) B - d I! T view Fujii R example's a-Irisho 4 times leather-disaster example shoulder 3 figure (Here 6 and l tomount enzyme) (a) Plane mouth (+)) C-C'! 5 mouths of takabe as usual in 17-page drawing
Claims (1)
ト部と、このマウント部を挟んで相対向する四つのボン
ディング部とが設けられた半導体装置用パッケージにお
いて、 前記マウント部を、前記セラミック基板の前記ボンディ
ング部の内端より内側を四角錐状に削りとった四角錐状
凹部の内部に設けた ことを特徴とする半導体装置用パッケージ。[Claims] 1. A package for a semiconductor device including a mount portion for attaching a pellet on a ceramic substrate, and four bonding portions facing each other across the mount portion, wherein the mount portion is A package for a semiconductor device, characterized in that the package is provided inside a quadrangular pyramid-shaped concave portion formed by cutting an inner side of the bonding portion of the ceramic substrate into a quadrangular pyramid shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7000289A JPH02249257A (en) | 1989-03-22 | 1989-03-22 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7000289A JPH02249257A (en) | 1989-03-22 | 1989-03-22 | Package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02249257A true JPH02249257A (en) | 1990-10-05 |
Family
ID=13418969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7000289A Pending JPH02249257A (en) | 1989-03-22 | 1989-03-22 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02249257A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6402281B1 (en) * | 2017-05-19 | 2018-10-10 | 新電元工業株式会社 | Electronic module, method for manufacturing connector, and method for manufacturing electronic module |
-
1989
- 1989-03-22 JP JP7000289A patent/JPH02249257A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6402281B1 (en) * | 2017-05-19 | 2018-10-10 | 新電元工業株式会社 | Electronic module, method for manufacturing connector, and method for manufacturing electronic module |
| WO2018211683A1 (en) * | 2017-05-19 | 2018-11-22 | 新電元工業株式会社 | Electronic module, production method for connector body, and production method for electronic module |
| US11437340B2 (en) | 2017-05-19 | 2022-09-06 | Shindengen Electric Manufacturing Co., Ltd. | Electronic module, method of manufacturing connector, and method of manufacturing electronic module |
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