JPS60226142A - Module structure - Google Patents
Module structureInfo
- Publication number
- JPS60226142A JPS60226142A JP8170484A JP8170484A JPS60226142A JP S60226142 A JPS60226142 A JP S60226142A JP 8170484 A JP8170484 A JP 8170484A JP 8170484 A JP8170484 A JP 8170484A JP S60226142 A JPS60226142 A JP S60226142A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- sealing
- metallization
- brazing
- module structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、ＬＳＩ等を実装したノ・イブリッドＩＣに係
り、特に封止構造体取付は部の小型化に適するモジュー
ル構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a no-brid IC mounted with an LSI or the like, and in particular to a module structure suitable for miniaturization of a part in which a sealing structure is attached.
第１図にＬＳＩを搭載した従来のノーイブリッドＩＣの
断面図を示す。１けセラミクス基板で、その中には、Ｗ
、Ｎｏなどの導体による配線層が形成されている。４け
ＬＳＩチップで、ワイアボンド、テープキャリア、ＣＣ
Ｂなどの方法で基板１の配線と接続されている。３は基
板１にろう接された入出力ピンである。このよりなノ・
イブリッドＩ Ｃ’では、通常、ＬＳＩやワイア。FIG. 1 shows a cross-sectional view of a conventional no-brid IC equipped with an LSI. It is a single ceramic substrate with W inside it.
, No., and the like are formed. 4-chip LSI chip, wire bond, tape carrier, CC
It is connected to the wiring of the board 1 by a method such as B. 3 is an input/output pin soldered to the board 1. More than this
Hybrid IC' is usually LSI or wire.
配線等を外部と遮断し腐蝕等金防ぐたみに、封止を行な
う。図において、５は封止用の金属製キャップで、通常
、４２アロイ、コバール々とが用いられている。このキ
ャップ５け基板表面の周日に施されたメタライズ２の上
にはんだ、ＡＬＬＳｎ銀ろうなどによりろう付されてい
る。第２図は他の従来例で、封止、あるいは冷却体の保
持、あるいはモジュール全取付ける手段としての金属製
フランジ７？セラミツク基板１の裏面に取付けたもので
ある。図でわかるように、従来例では、このろう付する
メタライズが配線基板の主平面に位置している。その結
果、第１図の例ではチップ搭載領域が減じ、第２図の例
では入出力ピン領域が減じるとともに、外部に出たフラ
ンジ７はこのハイブリッドＩＣｆマザーボードに密に実
装するのを妨げている。従って、従来例ではチップ搭載
部の実装密度に対してモジュール全体でみた場合の実装
密度は低くなるという欠点があった。Sealing is performed to isolate wiring, etc. from the outside and prevent metal corrosion. In the figure, 5 is a metal cap for sealing, and 42 alloy or Kovar is usually used. This cap 5 is soldered onto the metallization 2 applied on the circumference of the substrate surface using solder, ALLSn silver solder, or the like. FIG. 2 shows another conventional example, in which a metal flange 7 is used for sealing, holding a cooling body, or as a means for attaching the entire module. It is attached to the back side of the ceramic substrate 1. As can be seen in the figure, in the conventional example, the metallization to be brazed is located on the main plane of the wiring board. As a result, the chip mounting area is reduced in the example shown in Fig. 1, and the input/output pin area is reduced in the example shown in Fig. 2, and the external flange 7 prevents dense mounting on this hybrid ICf motherboard. . Therefore, the conventional example has a drawback that the packaging density of the entire module is lower than the packaging density of the chip mounting section.
本発明の目的は、上記従来の欠点をなくし、高密度実装
が可能な、従って小型化に適したハイブリッドＩＣ用モ
ジュール構造を提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a module structure for a hybrid IC that eliminates the above-mentioned conventional drawbacks, allows high-density packaging, and is therefore suitable for miniaturization.
本発明では、上記目的全達成するため、配線基板の主平
面ではなく、端面にメタライズを施すことにより、密度
會下げることなく、封止用等のろう付に供するようにな
したことを特徴とする。In order to achieve all of the above objects, the present invention is characterized in that metallization is applied not to the main plane of the wiring board, but to the end face, so that it can be used for brazing for sealing, etc., without reducing the density. do.
第３図に本発明の一実施例の断面図を示す。 FIG. 3 shows a sectional view of an embodiment of the present invention.
図に示すように、封止用メタライズ２は、配線基板１の
端面に施され、ろう材６により金属製キャップ５にろう
接される。ろう接部の拡大図を第４図に示す。この図で
は、ろう材がけんだ端面に濡れ、また金属キャップ５に
も濡れてフィレットを形成している。As shown in the figure, the sealing metallization 2 is applied to the end surface of the wiring board 1 and soldered to the metal cap 5 using a brazing material 6. An enlarged view of the soldered part is shown in Fig. 4. In this figure, the brazing material wets the soldered end face and also wets the metal cap 5, forming a fillet.
第５図は、本発明の他の実施例の拡大断面図である。こ
こでは、メタライズ２は端面だけでなく、これに接する
主平面上にも設けられている。その結果、第４図のもの
に比較して、ろう接面積が増し、かつ、基板１に対する
ろう材の濡れ角度を小さくできるため、ろう接の強度。FIG. 5 is an enlarged sectional view of another embodiment of the invention. Here, the metallization 2 is provided not only on the end face but also on the main plane in contact with the end face. As a result, compared to the one shown in FIG. 4, the soldering area is increased and the wetting angle of the brazing material with respect to the substrate 1 can be made smaller, thereby increasing the strength of the soldering.
信頼性の向上をはかることができる。Reliability can be improved.
第６図、第７図は各々主平面の一方の周辺にのみメタラ
イズ２を施こした例である。尚、これら周辺のメタライ
ズ２Ｆｉ、第８図に示すように基板１の通常四辺にそっ
て等巾で形成される。FIGS. 6 and 7 each show an example in which metallization 2 is applied only to one periphery of the main plane. Incidentally, the metallization 2Fi around these is generally formed with the same width along the four sides of the substrate 1, as shown in FIG.
このように、本実施例では、ろう接のための主たる部分
を基板の端面としているため、ろう接部に基板の主平面
の面積を多くとられず、その結果、従来のものより小型
化が可能となる。例えば、１０ｃｍ角基板に対し、ろう
付するため５Ｍ巾だけ基板音大きくした場合、その面積
比は、（１１０／１００）２＝１．２１ 、すなわち２
１％も大きくなる。In this way, in this embodiment, since the main part for soldering is the end face of the board, a large area of the main plane of the board is not taken up for the soldering part, and as a result, the size can be reduced compared to the conventional one. It becomes possible. For example, if a 10cm square board is made louder by 5M width for brazing, the area ratio is (110/100)2=1.21, that is, 2
It will increase by 1%.
これに対し、基板の（例えば５Ｍ厚の）端面を利用する
と、全く配線基板のサイズはかわらない。また、基板が
従来例より小型になる効果は、基板の製造歩留り、材料
コストにも有利となる。On the other hand, if the end face of the board (for example, 5M thick) is used, the size of the wiring board does not change at all. Furthermore, the effect of making the substrate smaller than the conventional example is advantageous in terms of manufacturing yield and material cost of the substrate.
上記の実施例は、封止キャップを基板に直接ろう付する
場合について述べられているが、封止用０リングをつけ
る、あるいは冷却用構造体をつケル、あるいけモジュー
ルの取付用等のフランジをろう付する場合についても、
同様の効果を有する。The above embodiment describes the case where the sealing cap is brazed directly to the board, but it is also possible to attach a sealing O-ring, a cooling structure, or a flange for mounting a module. Also when brazing
Has a similar effect.
以上述べた如く、本発明によれば、基板端面を有効に利
用しているため、従来に較べ、基板の小型化がはかれる
。したがって、実効の実装密度向上、基板材料コスト低
減、製造歩留向上に寄与することができる。As described above, according to the present invention, since the end face of the substrate is effectively utilized, the size of the substrate can be reduced compared to the conventional method. Therefore, it is possible to contribute to an effective increase in packaging density, a reduction in substrate material costs, and an improvement in manufacturing yield.
第１図、第２図は従来例の側断面図、第３図は、本発明
の実施例の側断面図、第４図から第７図は本発明を用い
たろう接部の拡大断面図、第８図はメタライズの一例を
示す基板の斜視図である。
１・・・配線基板 ２ メタライズ
３・・・入出力ピン ４・・、ＬＳＩ
５・封止キャップ ６・・・ろう材
代理人弁理士 高 橋明 夫
−１図
物３凶
男６図 １７−
第８図1 and 2 are side sectional views of a conventional example, FIG. 3 is a side sectional view of an embodiment of the present invention, and FIGS. 4 to 7 are enlarged sectional views of a soldered part using the present invention, FIG. 8 is a perspective view of a substrate showing an example of metallization. 1... Wiring board 2 Metallization 3... Input/output pin 4..., LSI 5, Sealing cap 6... Brazing material agent Patent attorney Akio Takahashi-1 Figure 3 Bad guy 6 Figure 17- Figure 8
Claims (1)
該メタライズに対し金属接合によシ封止構造体を取り付
けたことを特徴とするモジュール構造。 ２、 上記多層配線基板の主平面上で端面に接する部分
にもメタライズ１に施し、上記接合材料が主平面上にフ
ィレット全形成するように構成したことを特徴とする特
許請求の範囲第１項記載のモジュール構造。[Claims] 1. Metallizing the end faces of the four sides of the multilayer wiring board,
A module structure characterized in that a sealing structure is attached to the metallization by metal bonding. 2. The metallization 1 is also applied to a portion of the main plane of the multilayer wiring board that is in contact with the end face, so that the bonding material forms a fillet entirely on the main plane. Modular structure as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8170484A JPS60226142A (en) | 1984-04-25 | 1984-04-25 | Module structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8170484A JPS60226142A (en) | 1984-04-25 | 1984-04-25 | Module structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60226142A true JPS60226142A (en) | 1985-11-11 |
Family
ID=13753766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8170484A Pending JPS60226142A (en) | 1984-04-25 | 1984-04-25 | Module structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60226142A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63318758A (en) * | 1987-06-22 | 1988-12-27 | Toyo Commun Equip Co Ltd | Structure of airtight package |
| DE4110373A1 (en) * | 1990-03-30 | 1991-10-10 | Hitachi Ltd | ELECTRONIC CIRCUIT DEVICE AND METHOD FOR PRODUCING THE SAME |
| EP0779657A3 (en) * | 1995-12-13 | 1998-11-11 | Oki Electric Industry Co., Ltd. | Surface-mounted semiconductor package and its manufacturing method |
-
1984
- 1984-04-25 JP JP8170484A patent/JPS60226142A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63318758A (en) * | 1987-06-22 | 1988-12-27 | Toyo Commun Equip Co Ltd | Structure of airtight package |
| DE4110373A1 (en) * | 1990-03-30 | 1991-10-10 | Hitachi Ltd | ELECTRONIC CIRCUIT DEVICE AND METHOD FOR PRODUCING THE SAME |
| EP0779657A3 (en) * | 1995-12-13 | 1998-11-11 | Oki Electric Industry Co., Ltd. | Surface-mounted semiconductor package and its manufacturing method |
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