JPH04159762A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04159762A JPH04159762A JP28621290A JP28621290A JPH04159762A JP H04159762 A JPH04159762 A JP H04159762A JP 28621290 A JP28621290 A JP 28621290A JP 28621290 A JP28621290 A JP 28621290A JP H04159762 A JPH04159762 A JP H04159762A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- semiconductor device
- mounting
- lead
- alternately bent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 229920005989 resin Polymers 0.000 abstract description 5
- 239000011347 resin Substances 0.000 abstract description 5
- 238000000465 moulding Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置に関するものであり、特にそのリ
ード形状の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor devices, and particularly to improvements in the shape of their leads.
従来の技術
近年、半導体装置は、機能の拡大による半導体チップの
大型化、逆に高密度実装を目的とした半導体装置の小型
化が行なわれている。2. Description of the Related Art In recent years, semiconductor chips have been made larger due to expansion of functions, and conversely, semiconductor devices have been made smaller for the purpose of high-density packaging.
以下に従来の半導体装置について説明する。A conventional semiconductor device will be explained below.
従来のワイヤ方式による１個の半導体チップの実装方法
とは、第３図の平面図に示すように、リードフレーム１
のアイランド部２上に半導体デツプ３をＡｕ／Ｓｉ接合
、ブルーイング材、或は半田付によりマウント後、半導
体チップ３の端子とリート端子間をワイヤ４で接続し、
その後、エポキシ樹脂等を用いた樹脂モールド層５によ
って封止し、その後、リードフレーム１の所要箇所を切
断（リートカット〉、リート６を単一方向へ折り曲げ（
リードフォーミング）、最終的に第４図に示すような半
導体装置を（ｑるものであった。なお、第４図は完成し
た半導体装置の側面図である。The conventional method for mounting one semiconductor chip using the wire method is to mount a lead frame 1 as shown in the plan view in FIG.
After mounting the semiconductor depth 3 on the island portion 2 of the semiconductor chip 3 by Au/Si bonding, bluing material, or soldering, the terminals of the semiconductor chip 3 and the lead terminals are connected with wires 4,
After that, the lead frame 1 is sealed with a resin mold layer 5 made of epoxy resin or the like, and then the lead frame 1 is cut at required points (leat cut), and the lead frame 6 is bent in a single direction (leat cut).
(lead forming), and finally produced a semiconductor device as shown in FIG. 4. FIG. 4 is a side view of the completed semiconductor device.
発明が解決しようとする課題
しかしながら、従来のリード形状をもつ半導体装置では
、リートの高ピツチ化にともない、半導体装置の実装工
程において、実装基板上のランドにリードピッチと同程
度の位置合わせ精度で実装しなければならないという問
題がある。これは、リー１ぐピッチが高密度になったた
め、半導体装置の実装機がリードピッチと同程度の位置
合わぜ精度を有していないと、実装基板上の誤ったラン
ドに実装してしようためである。Problems to be Solved by the Invention However, in semiconductor devices with conventional lead shapes, as the pitch of the leads becomes higher, it is difficult to align the lands on the mounting board with the same level of accuracy as the lead pitch in the semiconductor device mounting process. There is a problem that needs to be implemented. This is because the lead pitch has become denser, and if the semiconductor device mounting machine does not have the same level of alignment accuracy as the lead pitch, it may end up being mounted on the wrong land on the mounting board. It is.
本発明はかかる点に鑑みてなされたもので、半導体装置
のり一ドピッチよりも低い位置合わせ精度で実装が可能
な半導体装置を提供することを１」的としている。The present invention has been made in view of this point, and has an object of the present invention to provide a semiconductor device that can be mounted with alignment accuracy lower than the semiconductor device gluing pitch.
課題を解決するだめの手段
」１記問題点を解決するため、本発明の半導体装置は、
異なる２つ以」１の面に実装可能なように交互に折り曲
げたリードを有している。In order to solve the problem described in 1. "Means for Solving the Problem", the semiconductor device of the present invention has the following features:
It has leads that are alternately bent so that two or more different leads can be mounted on one surface.
作用
本発明によれば、上記したようにリードを、単一方向で
はなく、いくつかの方向にリートフォーミングすること
により、リードピッヂよりも低い位置合わせ精度で実装
基板に実装することが可能となる。According to the present invention, as described above, by forming the leads not in a single direction but in several directions, it is possible to mount the leads on the mounting board with lower alignment accuracy than with lead pitch.
実施例 本発明の一実施例を図面を参照しながら説明する。Example An embodiment of the present invention will be described with reference to the drawings.
第１図は、本発明の一実施例における半導体装置の側面
図を示すものである。FIG. 1 shows a side view of a semiconductor device in one embodiment of the present invention.
リードフォーミング時にリード６を交互に上下方向に折
り曲げることにより、実質的に単一の実装基板への実装
の位置合わせ精度が低くても実装ができる。また実装は
」１下の実装基板に対して行なうことから、電気的によ
り近い距離で信号のやりとりができるという効果もある
。By alternately bending the leads 6 in the vertical direction during lead forming, it is possible to perform mounting on a substantially single mounting board even if the alignment accuracy is low. Furthermore, since the mounting is performed on the mounting board below 1, there is also the effect that signals can be exchanged electrically at a closer distance.
発明の効果
本発明は樹脂モールド層から引出されたリードを、手記
樹脂モールド層の異なる２つの面に向けて交互に折り曲
げたものであるから、リートピッヂよりも低い位置合わ
せ精度で実装基板に実装することができる。Effects of the Invention In the present invention, the leads pulled out from the resin mold layer are bent alternately toward two different sides of the resin mold layer, so the lead can be mounted on the mounting board with lower positioning accuracy than the lead pidge. be able to.
第１図は本発明の一実施例における半導体装置の側面図
、第２図は第１図と直交する方向から見た半導体装置の
側面図である。第３図は従来の半導体装置の組立て時の
平面図、第４図はぞの組立て後の側面図である。
］・・・・・・１−１’フレーム、２・・・・・・アイ
ランド部、３・・・・・・半導体デツプ、４・・・・・
・１ツイヤ、５・・・・・・樹脂モールド層、６・・・
・・・リ−１・。
代理人の氏名 弁理士小鍜治明 ほか２名１＝Ｌ
Ｌｌ”） 匂
ζ へ Ｃ）外 も （FIG. 1 is a side view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a side view of the semiconductor device viewed from a direction perpendicular to FIG. FIG. 3 is a plan view of a conventional semiconductor device when it is assembled, and FIG. 4 is a side view of it after assembly. ]...1-1' frame, 2...Island part, 3...Semiconductor depth, 4...
・1 gloss, 5...resin mold layer, 6...
...Lee-1. Name of agent: Patent attorney Haruaki Ogata and 2 others 1=L Ll”）
Claims (1)
装置。A semiconductor device having leads that can be mounted on two or more different surfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28621290A JPH04159762A (en) | 1990-10-23 | 1990-10-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28621290A JPH04159762A (en) | 1990-10-23 | 1990-10-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04159762A true JPH04159762A (en) | 1992-06-02 |
Family
ID=17701426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28621290A Pending JPH04159762A (en) | 1990-10-23 | 1990-10-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04159762A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130020695A1 (en) * | 2011-07-20 | 2013-01-24 | Hanjoo Na | "L" Shaped Lead Integrated Circuit Package |
| US8569913B2 (en) | 2011-05-16 | 2013-10-29 | Unigen Corporation | Switchable capacitor arrays for preventing power interruptions and extending backup power life |
-
1990
- 1990-10-23 JP JP28621290A patent/JPH04159762A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8569913B2 (en) | 2011-05-16 | 2013-10-29 | Unigen Corporation | Switchable capacitor arrays for preventing power interruptions and extending backup power life |
| US20130020695A1 (en) * | 2011-07-20 | 2013-01-24 | Hanjoo Na | "L" Shaped Lead Integrated Circuit Package |
| US9601417B2 (en) * | 2011-07-20 | 2017-03-21 | Unigen Corporation | “L” shaped lead integrated circuit package |
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