JPH02248986A - Portable electronic timetable - Google Patents

Abstract

PURPOSE:To display timetables by stations on the same display screen by using an electrically rewritable nonvolatile semiconductor memory(EEPROM), writing timetable data which are inputted from outside, and reading and displaying timetable data on a specified station. CONSTITUTION:When the CPU 25 in the electronic timetable 11 sends out a timetable version name transmission request to a timetable data base 13 through a transmitting circuit 22 and an antenna 21, the timetable data base 13 sends out data indicating the timetable version name, which is received by the electronic timetable 11. The electronic timetable 11 writes the timetable data which are decoded by a decoder 24 on the EEPROM 27 through the CPU 25. Then when a user inputs a timetable data display instruction through an input part 26, the CPU 25 finds the departure time and destination of a starting train among the timetable data in the EEPROM 27 according to data on the current time and displays them on a display part 29. Consequently, a desired timetable is displayed on the same display screen.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a portable electronic timetable.

(Prior art) Portable timetables for trains, buses, airplanes, etc. are available in the form of books sold at station kiosks and bookstores;
There is also a simplified format for each station that is distributed free of charge at stations. The former has a large amount of information, but the boarding station is always the same for commuting or commuting.
Most of the information is unnecessary for commuters, so not only is it difficult to find the information they need, but it is also too large and inappropriate.

The latter is for commuting to work or school, but the timetables are separate for the boarding station for going there and the station for returning, and even for the same station, weekday and holiday schedules are listed on different sides. The reality is that it is extremely difficult to use.

Furthermore, with conventional printed timetables, it is difficult to immediately recognize, for example, the departure time of the next train when there is a possibility of catching the train on time, for example, on the way to the station.

(Problem to be solved by the invention) As mentioned above, the conventional book-format timetable is not suitable for commuting to work or school, and the simplified-format timetable for each station requires separate timetables for going and returning. It is extremely difficult to use as weekday and holiday schedules are listed on separate pages.

Furthermore, conventional timetables have a problem in that it is difficult to immediately recognize the next departure time in conventional printed timetables.

An object of the present invention is to provide a portable electronic timetable that can display timetables for each station and for weekdays and days on the same display screen.

Another object of the present invention is to provide a portable electronic timetable that can display information such as the next departure time that can be immediately recognized.

[Structure of the Invention] (Means for Solving the Problems) A portable electronic timetable according to the present invention uses an electrically rewritable non-volatile semiconductor memory (EEFROM) to read timetable data input from the outside. The timetable data for the specified station can be written and read out and displayed.

Furthermore, when displaying timetable data for a specified station and direction based on the contents of a non-volatile semiconductor memory, it is possible to display departure times immediately after the current time to be distinguished from other departure times. More desirable.

(Function) Once the timetable data of several desired stations have been written into the EEFROM, when the user specifies the name of the station or direction he or she wants to ride in, the corresponding timetable data is selectively read out and displayed. be done. Therefore, the user can easily see the timetable of the train he or she is currently using, and can clearly recognize the next train departure time.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram for explaining the outline of an embodiment of the present invention, in which a portable electronic timetable 11 according to the present invention and a timetable database 13 installed on a timetable board 12 on a platform of a railway station are shown. This shows the status of communicating with.

Through this communication, the timetable database 1
The timetable data transmitted from 3 is received by the electronic timetable 11 and stored in an internal electrically rewritable nonvolatile semiconductor memory (EEFROM).

FIG. 2 shows the detailed configuration of the portable electronic timetable 11, which includes an antenna 21, a transmitting circuit 22, a receiving circuit 23 for communicating with the timetable database 13, and decoding of received timetable data. A decoder 24 and a CPU (
an arithmetic processing circuit) 25, an input section 26 such as a keyboard,
It includes an EEFROM 27, a clock circuit 28, and a display section 29 such as a liquid crystal display.

E E F ROM 27 is a NAND type E in this embodiment.
EFROM is used. It is assumed that the clock circuit 28 has a calendar function.

Figure 3 shows the NAND cell type EEPR used in this example.
FIG. 2 is a block diagram showing the configuration of OM.

Chip-enable terminal CE is used as an external control signal terminal.
, has an output enable terminal OE and a write enable terminal WE, and has 18 address signal terminals A.
0~A+s, 8 data input/output terminals 1100~! 10
7 and has power supply terminals Vcc and Vss. In this embodiment, the memory cell array 1 has a capacity of 4 Mbits and is made up of four memory cells collectively configured in a NAND type, as will be described later. Bit line BL of memory cell array 1
I-BLm (m-2048) is a sense amplifier/
It is connected to the day latch circuit 5. Selection gate line 5
G1n, 5G2n and word lines WLln to WL4
n (n −512) is connected to the row decoder 3. The address signal is input to a row decoder 3 and a column decoder 4 via an address buffer 2, thereby selecting an address. During reading, the data output to the bit lines BLI to BL■ is amplified and latched by the sense amplifier/data latch circuit 5, and outputted to the outside from the input/output terminals I10° to I107 via the output buffer 6. When writing data, input/output terminal 110°~
Data input from I/Ot is taken into the sense amplifier/data latch circuit 5 via the input buffer, and then written into the memory cell at the selected address.

8 is a control logic circuit that generates an internal control signal from an external control signal.

FIG. 4 is an equivalent circuit showing the configuration of the memory cell array 1. The memory cell MIJ is a FETMOS type in which a floating gate and a control gate are stacked over the entire channel region with a thin gate insulating film interposed therebetween. For example, in the case of an n-channel, the operation of moving the threshold in the negative direction by applying a positive high voltage to the control gate and releasing electrons from the floating gate to the substrate by F-N tunneling corresponds to data erasing. ,・Compatible with data writing by keeping the control gate at “L” level and applying a positive high voltage to the drain to inject electrons into the floating gate by F-N tunneling to move the threshold in the positive direction. let The high voltage used for data writing and erasing is applied to the row decoder 3. in FIG. It is generated by a booster circuit in the column move coater 4. These memory cells constitute a so-called NAND cell in which four memory cells are connected in series to form one block, with their sources and drains shared by adjacent cells. One end of the NAND cell is connected to the bit line BL via the selection gate Qsl, and the other end is connected to the selection gate Qs2.
It is connected to the source line Vs via. The memory cells are arranged in a matrix as shown, and the control gates of the memory cells in the row direction are commonly connected to the word line WL.

FIG. 5 is a timing chart during reading. Chip Φ enable terminal CE and output enable terminal OE are set to “L” level, and write enable terminal W is set to “L” level.
By changing the address with E as the "H" level, eight memory cell data are obtained via the sense amplifier/data latch circuit 5 on the input/output lines 110o to 110f.

FIG. 6 is a timing chart during writing. Set chip enable terminal CE to “L level, output
By setting the enable terminal OE to 'H' level and toggling the write enable terminal WE in synchronization with the address signal, the data input from the human output lines I10° to I10□ is sent to the sense amplifier/data via the human output line buffer. The data is latched by the latch circuit 5 and sequentially written to selected addresses.

In such a NAND cell type EEPROM, multiple memory cells are connected together to the bit line, so the number of contacts with the bit line is significantly smaller than when each memory cell is connected to the bit line. It has the advantage of being extremely densely integrated.

FIG. 7 is an example of displaying timetable data on the display unit 29 in FIG. This is an example. In this case, the displayed content is the same as the conventional simplified timetable for each station, but if the current time is around 5:10, the next departure time is 5:10.
By flashing the hour 25 minute display, the user can immediately know the departure time of the next train he or she can board, without having to compare the clock with the timetable. Such a display is possible on the product because the electronic timetable 11 has a built-in clock circuit 28.

FIG. 8 shows another display example of timetable data on the display unit 29, in which a user who is going from Kawasaki Station to the Tokyo area,
This is an example in which the boarding station and desired destination name are input via the input unit 26.

As shown in the figure, the departure time, line, and destination of trains departing after the current time (for example, around 10 o'clock),
The line number (platform number) etc. will be displayed.

FIG. 9 is a flowchart showing a procedure for importing timetable data in the electronic timetable 11. This process is started by the user of the electronic timetable 11 pointing the antenna 21 at the timetable database 13 and performing an operation to start importing timetable data via the input unit 26.

When this process starts, first, in step 101, a timetable version name transmission request is issued from the CPU 25 in the electronic timetable 11, and is transmitted to the timetable database 13 via the transmitting circuit 22 and antenna 21. The 82 people on the timetable barge is data indicating the "version" of the timetable that will be changed due to the timetable revision.

Upon receiving the timetable barge run name transmission request, the timetable database 13 transmits data indicating this timetable version name, which is received by the electronic timetable 11. Electronic timetable 1
1, the timetable virgin name received via the antenna 21 and the receiving circuit 23 and decoded by the decoder 24 is checked by the CPU 25, and is stored in the EEFRO.
It is checked whether the version name is the same as the version name of the timetable data stored in M27 (steps 102 and 103).
At this time, if the timetable data is not yet stored in the EEFROM 27, it is determined that the 12 barge members do not match. If it is determined in step 103 that the timetable verge names match, there is no need to newly import timetable data, and the timetable data importing process ends.

If the 82 timetable barges do not match in step 103, a timetable data transmission request is issued from the CPU 25 in the electronic timetable 11, and the transmission circuit 22 and antenna 2
1 to the timetable database 13 (step 104). Upon receiving this timetable data transmission request, the timetable database 13 transmits the timetable data,
This is received by the electronic timetable 11.

In the electronic timetable 11, timetable data received via the antenna 21 and the receiving circuit 23 and decoded by the decoder 24 is sent to the EEFROM via the CPU 25.
27.

After this writing is completed, a timetable data reception completion confirmation signal is sent back to the timetable database 13 (step 106), and the timetable data import process is completed.

Here, the timetable data is data for each station, and the EEF
The timetable data stored in the ROM 27 includes at least the departure time for each direction (up/down) and the name of the destination station, and more preferably includes the train line, platform track, etc. Furthermore, if there is a weekday schedule and a holiday schedule, timetable data for both schedules shall be written to the EEFROM 27.

FIG. 10 is a flowchart showing the procedure for displaying timetable data in the electronic timetable 11. This timetable time data display process is performed by the user of the electronic timetable 11 using the input unit 2.
The process starts by inputting a timetable data display command via 6. When this process starts, first in step 201 it is checked whether the user has specified the boarding station and route (direction and line). Once the boarding station and route are specified, they are identified in step 202, and then the corresponding timetable data is stored in the EEFROM2.
7 is stored (step 20).
3). In this case, if the corresponding timetable data is not stored, this display process is canceled.

If the corresponding timetable data is stored in the EEFROM 27, the process advances to step 204, and current time data is read from the clock circuit 28 into the CPU 25. CPU2
5, based on this current time data, EEFROM
From the timetable data in 27, the departure time and destination of the next train to depart are found (step 205). Then, on the display unit 29, the timetable data related to the boarding station and route previously specified by the user is displayed as shown in FIG. 7, so that only the next departure time is displayed blinking under the control of the CPU 25. (step 206). This display continues until the user inputs a display stop command.

In the above embodiment, the timetable database 13 is installed on the timetable board 12 as shown in FIG. 1, and the portable electronic timetable 11 and the timetable database 13 are connected wirelessly (
Although the case where communication is carried out via radio waves or optical transmission) has been described, the timetable database may be installed anywhere within the station, or in some cases may be located outside the station. Further, the timetable database and the portable electronic timetable may be connected via a connector to communicate with each other.

Further, the user may use the input unit 26 or the like to edit and rewrite the timetable data from the timetable database written in the EEFROM 27 into a form that is easy for the user to use.

In addition, although the embodiment describes a train timetable, it goes without saying that it can also be used as a timetable (travel schedule) for buses, airplanes, ships, etc.

Furthermore, the present invention can be implemented by incorporating the functions of a portable electronic timetable into a so-called electronic notebook.

【Effect of the invention〕

According to the present invention, a desired timetable can be displayed on the same display screen by simply specifying the station name, direction, etc., without having to search for the desired page unlike conventional timetables. Furthermore, by devising a display format, it is possible to easily know the next departure time from the current time, which is extremely effective in practical use.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the outline of an embodiment of the present invention,
FIG. 2 is a block diagram showing the internal structure of the portable electronic timetable according to the same embodiment, FIG. 3 is a block diagram showing the structure of the EEFROM used in the same embodiment, and FIG. 4 is the memory in FIG. 3. 305 and 6 are timing diagrams for explaining the operation of the EEFROM. FIGS. 7 and 8 are diagrams showing examples of timetable display in the same embodiment. The figure is a flowchart for explaining the procedure for timetable data import processing in the same embodiment, and FIG. 10 is a flowchart for explaining the procedure for timetable data display processing in the same embodiment. DESCRIPTION OF SYMBOLS 11... Portable electronic timetable, 12... Timetable board, 13... Timetable database, 21... Antenna, 22... Transmission circuit, 23... Receiving circuit, 24...
・Decoder, 25...CPU, 26...Input section, 2
7...EEPROM, 28...Clock circuit, 29...
・Display section. Applicant's agent Patent attorney Takehiko Suzue 2nd animal map 2nd memorial map

Claims (2)

[Claims] (1) An electrically rewritable nonvolatile semiconductor memory, means for writing timetable data input from the outside into the nonvolatile semiconductor memory, and reading specified timetable data from the nonvolatile semiconductor memory. 1. A portable electronic timetable, comprising: means for displaying read timetable data; and means for displaying read timetable data. (2) an electrically rewritable non-volatile semiconductor memory; a means for writing timetable data input from the outside into the non-volatile semiconductor memory; and a timetable for a designated station and direction from the non-volatile semiconductor memory. A portable electronic device comprising: means for reading table data; and means for displaying the read timetable data so that departure times immediately after the current time are distinguished from other departure times. time table.