TW565847B - Gate-split flash memory cell array capable of accessing data by a byte and its peripheral circuit - Google Patents

Abstract

In the gate-split flash memory cell array, each element is composed of memory cells of one byte, and each byte has a first driving circuit and a second driving circuit. The first driving circuit of each element has an output connected to the control gate of the byte memory cell. The second driving circuit of each element has an output connected to the source of the byte memory cell. In addition, each row of elements has a global word line connected to the input of the first driving circuit of the same row. Each row of elements also has a global source line connected to the input of the second driving circuit of the same row. The first driving circuits of the same column use the same power terminal and grounding terminal. The second driving circuit also uses the same power terminal and grounding terminal. Therefore, the above split-gate flash memory cell array is such a split-gate flash memory cell array capable of taking one byte data as an access unit.

Description

565847 V. Description of the invention (1) Field of the invention: The present invention relates to an open flash memory cell array, in particular to an open flash memory cell array that can use a byte as a data access unit and its peripheral circuits. Background of the invention:

Flash memory system A new storage system with low power consumption, high access speed, and shock-resistant, mobile-resistant, high-stability safety data access conditions. Information can be stored in the memory section more efficiently (b 1 ocks ) Way to record (or eliminate), not as slowly as sequential recording by byte. In addition, once the data is stored in the flash memory, no power is needed to retain the data. Generally speaking, with the current technology, the stored data can be retained for at least ten years even after the power is turned off. This advantage has eclipsed other portable storage systems, so compared to other storage media, flash memory is extremely competitive. Stance of a full tomorrow star. Not only digital cameras, notebook computers, handheld electronic notebooks, mobile phones and other electronic products, the demand for flash memory is even more inseparable. Generally speaking, the most typical application of flash memory is to make flash memory cards to provide portable electronic consumer products. For example, for a flash drive, voice recorder, MP3, smartphone, or digital camera

Page 4 565847 V. Description of the invention (2) CF (compact memory card) card, MMC (multimedia memory card) card, MS (me.mory stick card) card or SMC (smart memo [y card) card. These memory cards are often overwritten to update data. In other words, flash memory cells can not only provide data reading after data writing, but also need to update data frequently. Therefore, in addition to the block update method, if the byte update method is available: Yes, it is necessary. However, the current open-memory cell array, because [Rain columns are mostly source-facing, so when

^ ^ When the Tianweiwu * group is updated, the content of the data saved by Chiang ’s ‘W L’ neighboring bytes. "How to achieve shirt ringtones can be updated with the simplest circuit, but not for other bytes, and it is an early bit. This is the problem to be overcome by the present invention. There is already inherent interference, and in view of this, the present invention will provide a solution to the above-mentioned problems to be overcome. 2. The flash memory cell array architecture is summarized by the invention: The program of memory cell can be used for the memory of tuples. Another object of the present invention is to improve and read this time. And body wiping method.

565847 V. Description of the invention (3) The present invention discloses a flash memory cell array that can use byte data as an access unit. In the flash memory cell array, each element is composed of a one-byte memory cell, and each byte has a first driving circuit and a second driving circuit. The output of the first drive circuit of each element is connected to the control gate of the byte memory cell, and the output of the second drive circuit of each element is connected to the source of the byte memory cell. A wide area word line is connected to the input terminal of the first driving circuit in the same column. Each column element also has a wide-area source line, and is connected to the input terminal of the second driving circuit in the same column. The first drive circuits in the same row use the same power terminal and ground terminal, and the second drive circuits also use the same power terminal and ground terminal. Since the memory cells of each element can be controlled separately, the above-mentioned open flash memory array is a open flash memory array that can use byte data as an access unit. Detailed description: In view of the fact that a typical flash memory cell cannot be accessed in bytes, however this function is necessary. Therefore, the present invention will provide a switch in bytes Flash memory cell array. The main concept of the present invention is that each byte is added with a word line switch, and the source line is also added with a switch. In addition, even-numbered columns and odd-numbered columns are separated to prevent mutual interference. Another design is to increase a bias condition to reduce the impact on high-voltage components. Another special point is that the basic element of the array is a primary array (sub- array), each time the array consists of 8 rows, each

565847 V. Description of the invention (4) Each line is given a power source. For convenience, please refer to the first figure. Shown is an array of 2 bytes x 2 bytes. That is, there are four elements. Bytes (1, 1) and Bytes (2, 1) of the elements in the first row are typical flash memory cell arrays with opposite source gates by bit line β L < 0: 7 > Eight bit lines are connected to the drain of eight memory cells (only one is shown in the picture) of the byte (1, 1) and eight memory cells (only one of the picture is drawn) A) constituted by the drain. The (n, m) above indicates the m th byte in the n th column. The control gate connection of 8 memory cells of byte (1, 1). The domain sub-line LWL < l > (local word line for row 1) is not directly connected to the wide-area word line GWL < 1 > (global word 1 ine for row 1), but as the output terminal of the inverter driving circuit ii A 'is controlled by an inverter driving circuit 1 1 a composed of a CMOS transistor. Similarly, the area word line LWL < 2 > of the control gate connection of the eight memory cells of the byte (2,1) is not directly connected to the wide area word line GWL < 2 > of the second column, but As the output terminal of the inverter driving circuit 21, it is controlled by an inverter driving circuit 21 composed of a CMOS transistor. The drive circuit 1 1 A and the drive circuit 2 1 A in the first row are powered by a transistor ZVDD < 1 >. ≪ 1 > in ZVDD < 1 > represents the i-th row array element. AGND is a reference potential terminal with a lower voltage relative to the power source ZVDD < 1 >. If ZVDD < 1 > is connected to the VDD voltage and GAND is the voltage coupled to vcc, the following output result is obtained: When GWL < 1 > is connected to VSS, LWL < 1 > voltage

Page 7 565847 V. Description of the invention (5) is VDD. When GWL < 1 > is connected to VDD, the voltage of LWL < 1 > is VCC. It is also worth noting that the first row of elements: the bytes (1, 1) do not share the common source line with the bytes (2, 1). Instead, the respective regional common source lines 1 ^ 1 < 1 > and 1 ^ 12 are connected to the wide-area source lines GSL < 1 > and GSL < 2 > via drive circuits 116 and 216, respectively. The driving circuits 11B and 21B are powered by the power supply VSHV < 1 > for crystal operation, while the same AGND provides relatively low power for transistor operation. As in the first row of memory cell array elements: bytes (1, 1) and bytes (2, 1), the second row of memory cell array elements: bytes (1, 2) and bytes (2 2) There are also respective driving circuits 1 2 A and 2 2 B. The wide-area word line GW < 1 > is an input terminal of the drive circuits 1 1 A and 12 A connected to elements in the same row of the memory cell array. The wide-area source line GSL < 1 > is connected to the input terminals of the drive circuits 1 1 B and 1 2 B of the memory cell array element. The wide area word line GW < 2 > is connected to the input terminals of the drive circuits 21 A and 2 2 A of the memory cell array element. The wide-area source line GSL < 2 > is connected to the input terminals of the drive circuits 2 1 B and 2 2 B of the memory cell array element. In addition, the driving circuit 1 2 A and the driving circuit 2 2 A of the elements in the second row are powered by a power source ZVDD < 2 > for transistor operation. Therefore, < 2 > in ZVDD < 2 > represents the first row of elements. The driving circuit 12 B and the driving circuit 2 2 B are powered by a power supply VSHV < 2 >. ≪ 2 > in VSHV < 2 > represents the second line element.

565847

Because the wide-area word line GWL &lt; n &gt; and the wide-area source line 651 &lt; 1 ^ in the above-mentioned memory cell array are based on-columns as the basic operation unit. The bit line 81 ^ <〇: 7 &gt; or,] ^ <8: 1 / &gt; uses the bit 7G line as the basic operation unit. Therefore, no matter whether the data is read f or written data (ie, stylized) or data is erased, in the same row /, a byte must be selected, and the wide-area word line yWL & lt containing the byte η &gt; The unselected bytes are all applied to the same voltage. The wide area source line GSL &lt; n &gt; is also the same. However, the regional word lines and regional source lines are not necessarily the same, depending on reading, writing, or erasing. The table in Figure 2 shows that the selected byte, in this case, is the n-th column of the m-th byte. When performing a read operation, "the same column but not the selected byte (that is, the n-th column of the m-th column) Bytes other than bytes) / different columns and no bytes are selected (that is, any column other than the nth column) "The voltage state that must be applied to each of the above lines. Therefore, the result according to the table in Figure 2 is: the wide-area word lines in column 11 are connected to VSS 'wide-area word lines other than column η are connected to ν j) D power supply, all wide-area source lines are connected to VDD, and in addition to column η All other wide-area word lines are connected to the VDD power supply, and all ZVDD and VSHV are connected to VDD, AGND is connected to VSS, and the bit line of the mth byte is connected to a voltage of 0.8 V, except for the mth byte. Bit lines are connected to vg ς. The above text is illustrated in figures as shown in Figures 2A to 2C. Figure 2 shows the flashing of the opening circuit. § When referring to the description of the cell system, the control gate is applied with V D D voltage, and the source is applied with VSS reference voltage (0 volt or ground). Figure 2 shows the same column but not the selected byte, and the drain voltage is vSS. Figure 2c is a schematic diagram of a memory cell in a different column and no byte is selected and the voltage applied to it.

Page 9 565847 V. Description of the invention (7) Figure 3 shows the table "Selected Bytes" for stylized operation, "" The same column but not the selected byte / different column and no byte is selected & quot The state of the voltage that must be applied to each line. Therefore, according to the table in Figure 3, the wide-area word line in column 0 is connected to VSS, all wide-area word lines except in the n-th column are connected to VDD power, and the ^ -th column The wide-area source line is connected to VSS, the wide-area source lines other than the ^ th column are connected to 10 volts, all VDDs are connected to 1 · 8 V, except for the m-th row, V s Η V is connected to 10 volts, all other In the line, VSHV is connected to VDD, all AGND is connected to vss, and the bit line to be programmed among the 8 bit lines of the m-th byte is connected to the voltage 0.6 V. The above text is illustrated in the figure as shown in Figures 3A to 3 C. As shown in Figure 3a, when the flash memory cell is opened, the control gate is applied with a voltage of 8 V and the source is applied with 10 V. The bit line is 0.6. v. Please note that at this time, LSLη &lt; m &gt; is provided by the output of the drive circuit (the mth byte) of the power supply VSΗV &lt; η &gt; at 10 V, and LWLn &lt; m &gt; It is provided by the power zVDD &lt; n &gt; for the output terminal of the driving circuit of 18V. It is in the same row as the electric diagram III B but not the selected byte. The drain voltage and source power are both VDD. It is 1 · 8 volts. Therefore it will not be stylized. Figure 3c shows a diagram of a memory cell and its applied voltage in different columns without bytes. Although the control gate and drain are There is a voltage difference, but the control gate voltage is vsf voltage. So it will not be programmed. Figure 4 shows the π selected byte. When performing data erasing operation, the same row but not the selected byte / Different columns without right ^, a α depending on the selected state of the voltage that must be applied to each line. Therefore, according to the figure, the results of 砉 0 and 仏 lun

Page 10 565847 V. Description of the invention (8) Yes: the wide-area word lines in the n-th column are connected to V s S, and all the wide-area word lines except the n-th column are connected to 1 3 V 'all the wide-area source lines are connected to ν DD. Except for the z V D D line of the m-th line connected to 1 3 V, the z V D D line of all the other lines is connected to V D D. All G A N D are connected to V D D, Sri Lanka wide-area source line GSL is connected to VDD, all VSHV lines are connected to VDD, and all bit lines are connected to voltage VSS. The above text is illustrated with figures, as shown in Figures 4A to 4c. Figure 4A shows that when the flash memory data of the open gate is erased, the control gate is applied with a “voltage” and the source and end are connected to the vss reference potential. Please note that the AGND of the drive circuit is not connected at this time. To VSS, it is VDD, and LWLn &lt; m &gt; is provided by the round end of the drive circuit of the power supply ZVDDjn ^ 13V. Figure 4B is the same column but not the selected byte. The drain voltage and source power are both VDD, and the control gate is connected to VDD. This voltage cannot generate data erasure. Figure 4 C is a schematic diagram of a memory cell with different columns and no bytes selected and its applied voltage. Although GWL = 13 volts, but at this time the driving circuit is turned on, so the output terminal LWLn &lt; m> is equal to the voltage, that is, VDD. Therefore, the same as above, data erasure will be performed. As can be seen from the above, the separate memory of the present invention The advantages of the cell unit are: 1. Each word group is added with a word line switch, and the source line is also increased = OFF. In addition, even and odd columns are separated. For this reason, only f each Data can be read out from the selected byte by the electrode given a proper voltage Normalization and data erasing. 565847 V. Description of the invention (9) 2. When operating on any byte, adjacent bytes will not have data to prevent mutual interference. The above description uses the preferred embodiment The present invention is described in detail, but not to limit the scope of the present invention, and those skilled in the art will understand that appropriate changes and adjustments will still not lose the essence of the present invention, nor depart from the spirit and scope of the present invention. range.

Page 12 565847 Simple illustration of the diagram Simple illustration of the diagram The description of the figure is to connect the electric memory cell, the electric cell, the electric cell, the electric cell, the electric cell, the electric cell, the electric cell, and the electric cell. Connect the three tables as the voltage to indicate the poles to connect the memory cells and each of the four cells to the voltages. The electrodes are connected to one memory cell and one memory cell. Figure Number Description: Drive circuit 1 1 A Wide area source line Wide area word line t The 2 × 2 flash memory cell array of the Mingshiyuan example shows the voltage applied to each electrode in the nth column and the _th tuple of the nth column and the mth byte in the nth column. The electrodes Θ j Figure 2 B is a schematic diagram of a voltage other than the mth byte in the nth column, and FIG. 2C is a schematic diagram of a voltage other than the nth column. ^ When the mth byte in the ηth column is stylized, each electrode is two. Figure 2A is a schematic diagram of the memory f of one of the mth byte in the thirteenth column, and Figure 3B is the mth byte in the nth column. Therefore, the electrode is connected to the voltage, and FIG. 3C is a schematic view of the electrode connected to the nth column.

When erasing the bit-line data of the n-th column of the n-th column, each electric = figure, Fig. 4A is the intention to record private pressure in one of the n-th column of the n-th column, and Fig. 4B is the n-th column Schematic diagram of the voltages connected to the electrodes of the mth byte group. Figure 4C is a schematic diagram of the voltages connected to the electrodes of the nth column Q

HB, 12A, 12B, 21A, 21B, 22A, 22B

GSL bit line BL

GWL drive circuit power supply ZVDD, VSHV repair

Page 13 565847

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Claims (1)

565847 6. Scope of patent application Patent scope: 1. A flash memory cell array that can access byte data includes at least: a plurality of sub memory arrays (sub-in em, oryarray), each time The memory cell array is an element of the gated flash memory cell array, and each element includes the number of memory cells constituting a byte, and has a regional word line connected to the control gate of the memory cell of the byte, and a region. A source line byte is connected to the source of the memory cell of the byte; first driving circuits of the same number as the element are arranged in rows and columns with the element, and each output terminal is connected to a word line of the region; and The second driving circuit with the same element / solid number is arranged in rows and columns with the element, and each output terminal is connected to a source line of the region; the elements of each column include a wide-area word line (g 1 〇ba 1 w 〇 rd 1 ine), each wide-area word line is connected to the input end of the first drive circuit in the same column; the elements of each column include a wide-area source line (g 1 〇ba 1 s urce 1 ine), each wide-area word line Domain source line Connect the input terminals of the second drive circuits in the same row; the first drive circuits in the same row use the same first power line and ground line, and each first power line provides power supply for all the first drive circuits in the entire row, Each ground line provides the relatively low voltage output of the first drive circuit. The second drive circuit of the same row uses the same second power line and ground line. Each second power line provides all the second drive circuits of the entire line. Page 15 565847 6. Power supply for patent application 'Each ground wire provides the relatively low voltage output of the second driving circuit. 2. The winter-opened flash memory cell array according to item 1 of the scope of the patent application, wherein the first driving circuit and the second driving circuit are CMOS transistors. 3. The gated flash memory cell array as described in item 1 of the scope of the patent application, wherein each of the above elements has a memory cell number of 1x8. 4 · The split flash memory cell array as described in item 1 of the scope of patent application, wherein when the mth byte of the nth column is read, the wide area word line of the nth column is connected to VSS. The wide-area word lines outside the n-th column are connected to VDD power, all the wide-area source lines are connected to VDD, all the wide-area word lines outside the n-th column are connected to VDD power, and all the first and second power lines are connected VDD, the ground line is connected to v § S, the 8 bit lines of the m-th byte are connected to the voltage VBL, and the bit lines other than the m-th byte are connected to VSS, where VDD &gt; VBL &gt; VSS. 5. The open flash memory cell array as described in item 1 of the scope of the patent application, wherein when the mth byte of the nth column is programmed, the wide area word line of the 11th column is connected to VSS All wide-area word lines other than the n-th column are connected to VDD power, the wide-area source lines of the n-th column are connected to VSS, the wide-area source lines other than the n-th column are connected to VS, and all first power lines are connected to the ν program. Except for the second power line of the m-th row connected to VS, the second power line of all the other lines is connected to VDD, and all ground lines are connected to the bit lines to be programmed among the eight bit lines of the VSS 'm-th byte. Voltage 565847 6. Scope of patent application VBL, other bit lines are connected to VDD, where VS &gt; VDD &gt; V program &gt; VBL &gt; VSS. _ 6. The flash memory cell array as described in item 1 of the scope of the patent application, when the m-th byte of the n-th column above is erased by the data, the wide-domain word of the n-th column Lines are connected to VSS, all wide-area word lines except the n-th column are connected to V erase, and all the wide-area source lines are connected to VDD, except for the first power line in the m-th row connected to V erase, all other lines One power line is connected to VDD, all ground lines are connected to VDD, all wide-area source lines are connected to VDD, all second power lines are connected to VDD, and all bit lines are connected to voltage VSS, where V wipes &gt; VDD &gt; VSS. Page 17