201227742 六、發明說明： 【發明所屬之技術領域】 本發明係關於-種半導體記憶體之設計，更特別的是 關於種反或型快閃S己憶體之區域字元線驅動II及其快閃 記憶體陣列裝置。 八、 【先前技術】 半導體記憶體之核心包括用來儲存資訊的記憶體陣 列，而記憶體陣列則是以半導體、磁性或鐵電性記憶細胞 為基礎。-般而言，所述的記憶體陣列是由許多記憶細胞 構成的二維陣列，每一個記憶單元可由一組相互垂直的字 疋線與位7〇線加以定址。傳統的字元線選擇列係用以啟動 記憶單元，而位元線選擇攔係用以存取（即讀取或寫入） »己憶單元。當字元線與位元線皆被啟動時，則代表選取了 電性連接至字元線與位元線的記憶單元。201227742 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to the design of a semiconductor memory, and more particularly to the area word line driver II of a reverse or flash type S memory. Flash memory array device. 8. [Prior Art] The core of semiconductor memory includes a memory array for storing information, and the memory array is based on semiconductor, magnetic or ferroelectric memory cells. In general, the memory array is a two-dimensional array of memory cells, each of which can be addressed by a set of mutually perpendicular word lines and bit lines. The conventional word line selection column is used to activate the memory unit, and the bit line selection block is used to access (i.e., read or write) the memory unit. When both the word line and the bit line are activated, it means that the memory unit electrically connected to the word line and the bit line is selected.
Pic著半導體製程能力的提升，記憶單元之尺寸越做越 小，連帶的總體記憶體陣列的尺寸也越做越小。然而，當 記憶體陣列的面積縮小時，對於用來控制寫入或是讀取記 憶體陣列資料的周邊電路’其面積相對於總面積的比例就 會大幅提高。例如，用來驅動字元線的驅動電路係被安排 在記憶陣列的周邊區域，該驅動電路位於字元線的尾端以 接收電壓。其中，驅動電路的電晶體排列方式相較於記憶 陣列内的記憶單元排列方式來說，電晶體的排列方式通常 是非常寬鬆的。因而，隨著記憶體陣列尺寸的微縮，傳統 F ς· 1 201227742 的驅動電路占用整個記憶體電路的面積比率就大幅提高。 第1圖係習知反或型快閃記憶體之一區域字元線驅動 器的電路圖。習知之每一區域字元線驅動器100包含— PMOS電晶體QA、一第一 NMOS電晶體qb及一第二 NMOS電晶體QC，該PMOS電晶體QA串聯耦接於第一 NMOS電晶體QB，而第二NM0S電晶體Qc並聯耦接於 PMOS電晶體QA。PMOS電晶體QA之閘極係耦接至第一 NMOS電晶體QB之閘極，並耦接至一控制端GN。pM〇s 電晶體QA之汲極係耦接至施加電壓之汲極控制端D，而 源極則耦接至第一 NMOS電晶體QB之汲極與第二NM〇s 電晶體QC之源極’並耦接至記憶體陣列之一區域字元線 WL。第一 NMOS電晶體QB之汲極端係耦接第二NM〇s 電晶體QC之源極，以及耦接該區域字元線WL。第—NM〇s 電晶體QB之源極則輕接至源極控制端s。第二電 晶體QC之閘極則耦接另一控制端GP。利用此電路係可分 別提供讀取、程式化或抹除偏壓至一字元線。 因此，習知利用三顆M0S電晶體來組成一區域字元線 驅動器的方式會在整體電路中占用過多的面積。隨著記憶 晶胞陣列尺寸的微縮化，占用過多面積的字元線驅動器是 不被樂見的。 【發明内容】 有鑑於S知技術的缺點，本發明之一目的在於提供一 種區域字元線驅動器及其快閃記憶體陣列裝置，其可減少 201227742 字元線驅動器於電路上占用的面積。 為達上述目的及其他目的，本發明提供之區域字元線 驅動器其係用於驅動反或型快閃記憶體的記憶體陣列中一 區段内之' —區域字元線’該區域字元線驅動裔具有之電晶 體數量係為兩個，係由下列串聯之二電晶體組成：一第一 電晶體，係為NMOS電晶體，其閘極端用於接收一全域字 元線解碼器之第一控制訊號，其汲極端耦接一汲極控制端 用於接收一汲極控制訊號，其源極端則耦接該區域字元 線；及一第二電晶體，係為NMOS電晶體，其閘極端用於 接收該全域字元線解碼器之第二控制訊號，其汲極端耦接 該第一電晶體之源極端以及耦接該區域字元線，其源極端 耦接一源極控制端用於接收一源極控制訊號；其中，該反 或型快閃記憶體的記憶體陣列中，同一行上的每一區域字 元線驅動器係共用該汲極控制端，亦即，同一行上，每一 區域字元線驅動器之第一電晶體的汲極端皆耦接至同一汲 極控制端。 於本發明之一實施例中，該全域字元線解碼器具有分 別耦接該第一電晶體及該第二電晶體之一第一控制端及一 第二控制端。 為達上述目的及其他目的，本發明之快閃記憶體陣列 裝置，其包含：一記憶體陣列，係包含多個記憶單元，該 等記憶單元區分為複數個區塊，每一區塊具有複數個區 段，每一區段具有複數條區域字元線；複數個區域字元線 驅動器，各耦接至對應之區域字元線，每一區域字元線驅 201227742 動器具有之電晶體數量係為兩個，其係由串聯之一第一電 晶體及一第二電晶體組成，且皆為NMOS電晶體，其中， 同一行上，每一區域字元線驅動器之第一電晶體的汲極端 皆耦接至同一汲極控制端；及複數個全域字元線解碼器， 係對應於每一區段並各耦接至對應區段内之所有區域字元 線驅動器。 於本發明之一實施例中，同一區塊内且同一行之相鄰 兩區域字元線驅動器中’該第一電晶體及該第二電晶體排 列之順序係為相反。 藉此，本發明將習知技術使用之電晶體數量減少為兩 個，並利用電路上之特殊安排以縮小晶片尺寸（die size)並 節省更多的面積來供記憶體單元使用。 【實施方式】 為充分暸解本發明之目的、特徵及功效，茲藉由下述 具體之實施例，並配合所附之圖式，對本發明做一詳細說 明，說明如後： 本發明中敘及之「行」於圖式中係指直向的方向，而 敘及之「列」於圖式中係指橫向的方向。 首先請參閱第2圖，係本發明於一實施例中區域字元 線驅動器之電路圖。該區域字元線驅動器200具有之電晶 體數量係為兩個，即第2圖中之第一電晶體QD及第二電 晶體QE，該二電晶體皆為NMOS電晶體且係以串聯之方 式相互連接。 201227742 該第一電晶體QD，其閘極端用於接收一全域字元線解 馬器（圖未式）之控制端Gp所傳遞之第一控制訊號。其汲 極柒耦接一汲極控制端D，用於接收一汲極控制訊號。其 源極端則麵接一區域字元線Wl，用於提供讀取、程式化或 抹除偏壓至該區域字元線WL。 同時’本發明於實施時，在反或型快閃記憶體的記憶 體陣列中’於每-區段且同—行之區域字元線驅動器共用 該汲極控制端D ’其將於後續第3A及3B圖有詳細說明。 接下來將以表一說明本發明實施例中區域字元線驅動 器在各種條件下之操作條件。Pic's ability to process semiconductors has increased, and the size of memory cells has become smaller and smaller, and the size of the associated memory array has become smaller. However, when the area of the memory array is reduced, the ratio of the area to the total area of the peripheral circuit used to control the writing or reading of the memory array data is greatly increased. For example, a driver circuit for driving word lines is arranged in a peripheral region of the memory array, the driver circuit being located at the tail end of the word line to receive a voltage. Among them, the arrangement of the transistors of the driving circuit is generally very loose compared to the arrangement of the memory cells in the memory array. Therefore, as the size of the memory array is reduced, the area ratio of the driving circuit of the conventional F ς 1 201227742 to the entire memory circuit is greatly increased. Figure 1 is a circuit diagram of a regional word line driver of one of the conventional inverse or flash memories. Each of the conventional word line driver 100 includes a PMOS transistor QA, a first NMOS transistor qb, and a second NMOS transistor QC. The PMOS transistor QA is coupled in series to the first NMOS transistor QB. The second NMOS transistor Qc is coupled in parallel to the PMOS transistor QA. The gate of the PMOS transistor QA is coupled to the gate of the first NMOS transistor QB and coupled to a control terminal GN. The drain of the pM〇s transistor QA is coupled to the drain control terminal D of the applied voltage, and the source is coupled to the drain of the first NMOS transistor QB and the source of the second NM〇s transistor QC. 'Coupled to one of the memory word array area word lines WL. The first NMOS transistor QB is coupled to the source of the second NM〇s transistor QC and coupled to the regional word line WL. The source of the first-NM〇s transistor QB is lightly connected to the source control terminal s. The gate of the second transistor QC is coupled to the other control terminal GP. This circuit can be used to provide read, program or erase bias to a word line. Therefore, the conventional method of using three MOS transistors to form an area word line driver will occupy too much area in the overall circuit. As the size of the memory cell array is reduced, word line drivers occupying too much area are not appreciated. SUMMARY OF THE INVENTION In view of the shortcomings of the prior art, it is an object of the present invention to provide an area word line driver and a flash memory array device thereof that can reduce the area occupied by the 201227742 word line driver on the circuit. To achieve the above and other objects, the present invention provides an area word line driver for driving a 'region word line' in a sector of a memory array of an inverse or type flash memory. The line driver has two transistors, which are composed of the following two transistors: a first transistor, which is an NMOS transistor, and a gate terminal for receiving a global word line decoder. a control signal is coupled to a drain control terminal for receiving a drain control signal, and a source terminal is coupled to the region word line; and a second transistor is an NMOS transistor. The second control signal is used to receive the second control signal of the global word line decoder, and is coupled to the source terminal of the first transistor and the word line of the first transistor, and the source terminal is coupled to the source control terminal. Receiving a source control signal; wherein, in the memory array of the inverse type flash memory, each area word line driver on the same line shares the gate control terminal, that is, on the same line, Each area word line driver A drain terminal of the transistor are all coupled to the same drain control terminal. In one embodiment of the present invention, the global word line decoder has a first control end and a second control end coupled to the first transistor and the second transistor, respectively. For the above purpose and other purposes, the flash memory array device of the present invention comprises: a memory array comprising a plurality of memory cells, the memory cells being divided into a plurality of blocks, each block having a plurality of blocks Segments, each segment having a plurality of region word lines; a plurality of region word line drivers each coupled to a corresponding region word line, each region word line drive 201227742 actuator having a number of transistors There are two, which are composed of a first transistor in series and a second transistor, and both are NMOS transistors, wherein, on the same row, the first transistor of each region of the word line driver The extremes are all coupled to the same drain control terminal; and a plurality of global word line decoders are associated with each segment and each coupled to all of the regional word line drivers in the corresponding segment. In an embodiment of the invention, the order of the first transistor and the second transistor in the adjacent two-region word line driver in the same block is reversed. Thus, the present invention reduces the number of transistors used in the prior art to two and utilizes special arrangements on the circuit to reduce the die size and save more area for use by the memory unit. DETAILED DESCRIPTION OF THE INVENTION In order to fully understand the objects, features and advantages of the present invention, the present invention will be described in detail with reference to the accompanying drawings. The word "row" in the drawing refers to the direction of the straight direction, and the "column" in the drawing refers to the direction of the transverse direction. Referring first to Figure 2, there is shown a circuit diagram of a regional word line driver in accordance with one embodiment of the present invention. The area word line driver 200 has two transistors, that is, the first transistor QD and the second transistor QE in FIG. 2, both of which are NMOS transistors and are connected in series. Connected to each other. 201227742 The first transistor QD has a gate terminal for receiving a first control signal transmitted by a control terminal Gp of a global word line decoder (not shown). The 柒 pole is coupled to a drain control terminal D for receiving a drain control signal. The source terminal is connected to an area word line W1 for providing a read, program or erase bias to the area word line WL. At the same time, when the present invention is implemented, in the memory array of the inverse or flash memory, the word line driver in the per-segment and the same-line area word line driver shares the bungee control terminal D' which will be followed by 3A and 3B are detailed. Next, the operating conditions of the area word line driver in various embodiments of the present invention will be described with reference to Table 1.
Read(s) Read(u) Read(u) PGM(s) PGM(u) PGM(u) ER(s) ER(u) D Vread Vread Vss Vpp Vpp Vss Vss Vss S Vss Vss Vss Vss Vss Vss Vng Vss GP VH Vss VH VHP Vss VHP Vng Vss GN Vss Vcc Vss Vss Vcc Vss Vss Vss WL Vread Vss Vss Vpp Vss Vss Vng float 表一 當區域字元線驅動器被選擇時，即（s)狀態，於讀取模 式下Read (s) ’控制端GP傳遞具有高電壓位準之第一控制 訊號(VH)至第一電晶體QD之閘極端，以打開該第一電晶 體QD，使得該汲極控制端D傳遞之汲極控制訊號（此時 為Vread)可傳遞至該區域子元線WL ’使對應之記惊體單 元進行讀取程序。其中，讀取模式下，控制端GN傳遞至 第二電晶體QE之第二控制訊號係為低電壓位準vss，於串 201227742 聯方式下，並不會打開該第二電晶體QE，因此，透過源極 控制端S而施加於第二電晶體QE源極端之低電壓位準vss 就不會傳遞至該區域字元線WL。 同樣地’在區域字元線驅動器被選擇時，於編程模式 下PGM(s) ’控制端GP傳遞之具有高電壓位準之第一控制 訊號(VHP)會打開該第一電晶體QD，使得該汲極控制端d 傳遞之〉及極控制訊號（此時為Vpp)可傳遞至該區域字元 線WL ’使對應之記憶體單元進行編程程序。而在抹除模式 下ER(s)，控制端GP傳遞具有負電壓位準之第一控制訊號 (Vng)至該第一電晶體QD之閘極端，控制端Gn則傳遞具 有低電壓位準之第二控制訊號(Vss)至該第二電晶體QE之 閘極端’此二電晶體於本發明之串聯方式下，即可打開該 第二電晶體QE，使得該源極控制端s傳遞之源極控制訊號 (此時為Vng)可傳遞至該區域字元線WL，使對應之記憶 體單元進行抹除程序。 當區域字元線驅動器未被選擇時，即（u)狀態，表中的 一讀取模式Read (u)及一編程模式pgm(u)亦對該第一電晶 體QD及第二電晶體QE施加相反於選擇模式下之不同位準 之電壓，以控制區域字元線驅動器200施加於區域字元線 WL之電壓訊號。其中，未被選擇時，表中之第二個讀取模 式Read(u)可透過沒極控制端d傳遞之電壓訊號來控制區 域子兀線驅動器2 0 0之輸出。 於區域字元線驅動器未被選擇且位於抹除模式ER(u) 下時’可使第一及第二電晶體QD、QE皆接收到相同之低 201227742 電壓位準訊號Vss，使區域字元線驅動器200之輸出係為浮 動（floating)。 表一之操作狀態僅為一種示例，仍有其他的操作狀態 可應用於本發明之區域字元線驅動器中，並可達到相同之 目的。例如：未被選擇且位於抹除模式下時，該源極控制 端S傳遞之源極控制訊號可為浮動（floating)。 接著請同時參閱第3A及3B圖，係根據第2圖之區域 字元線驅動器應用於整體字元線驅動器結構上的左部分及 右部分之平面圖，其中整體字元線驅動器結構於圖式的表 示上被分割為左部分及右部分，其拼合在一起即為整體之 電路平面圖。整體字元線驅動器結構包含對應記憶體陣列 中之記憶體單元之複數個區塊Block 1〜k，每一區塊具有複 數個區段Sector 11〜jk(j, kEA〇，而每一區段具有複數條字 元線以及具有驅動該等字元線之複數個區域字元線驅動器 200。同一行下之所有區段具有對應之全域字元線解碼器 202j(jeA〇,該全域字元線解碼器202j具有一第一控制端 GP與一第二控制端GN，以分別送出第一控制訊號及第二 控制訊號至相耦接之第一電晶體QD及第二電晶體QE (請 同時參閱第2圖）。同時，參閱圖式可知，同一行（例如： 行11)上之區域字元線驅動器200的第一電晶體QD的汲 極端皆耦接至同一汲極控制端D (例如：D11 )，亦即，該 汲極控制端D之控制線會橫跨記憶體陣列並驅動位於同一 行之區域字元線驅動器200。 於一實施例中，該全域字元線解碼器202j係包含一第 ί \· 201227742 一驅動器202a與一第二驅動器202b，並分別對應該第一控 制端GP與該第二控制端GN。第一驅動器202a受一外部 信號VP所控制，而第二驅動器202b係可為一反向器 (inverter)。每一全域字元線解碼器202j係由對應之解碼訊 號DECj(jeA〇所控制，並藉由第一驅動器202a與第二驅動 器202b輸出特定電壓（請參閱表一）予第一電晶體QD及 第二電晶體QE。 於第3A及3B圖之實施例中，在一區塊内，由於同一 行（例如：行11)上之區域字元線驅動器200的第一電晶 體QD的汲極端皆耦接至同一汲極控制端D (例如：D11)。 因此，同一區塊内且同一行之相鄰兩區域字元線驅動器 中，第一電晶體QD及第二電晶體QE排列之順序係恰好相 反（請參閱第3A及3B圖），同樣地，對應之第一驅動器 202a與第二驅動器202b亦為如此，如此可減少電路面積。 如第3A及3B圖所示，相鄰二區段（如sector 21及sector 31)間係分別共用汲極控制端Dll、D12、Dln、Dkl、Dk2、 Dkn 等。 此外’在編程模式下’由於區域字元線需要之電壓接 近10伏特，而第一電晶體QD的導通（以將汲極控制端之 電壓減去電晶體内之臨限電壓值Vth後傳遞至字元線）需要 使閘極端接收之電壓（由該外部信號VP的電壓而來）大於 没極控制端之電壓，為了盡量最小化該外部信號VP的電 壓，每一局部字源線驅動器中之第一電晶體會採用具有較 低臨限電壓值之電晶體。 201227742 綜上所述，本發明於一局部字源線驅動器中使用之電 晶體數量及種類僅為兩個NMOS電晶體，其可縮小晶片尺 寸（die size)以及節省更多的面積來供記憶體單元使用。 本發明在上文中已以較佳實例揭露’然熟習本項技術 者應理解的是，該實施例僅用於描繪本發明，而不應解讀 為限制本發明之範圍。應注意的是，舉凡與該實施例等效 之變化與置換，均應設為涵蓋於本發明之範疇内。因此， 本發明之保護範圍當以申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖為習知反或型快閃記憶體之一區域字元線驅動 器的電路圖。 第2圖為本發明於一實施例中區域字元線驅動器之電 路圖。 第3A圖為根據第2圖之區域字元線驅動器應用於整體 字元線驅動器結構上的左部分平面圖。 第3B圖為根據第2圖之區域字元線驅動器應用於整體 字元線驅動器結構上的右部分平面圖。 【主要元件符號說明】 100 區域字元線驅動器 102 全域字元線解碼器 200 區域字7G線驅動 202a 第一驅動器 201227742 202b 第二驅動器 202j(jEA〇 全域字元線解碼器 QA PMOS電晶體 QB 第一 NMOS電晶體 QC 第二NMOS電晶體 QD 第一電晶體 QE 第二電晶體 Dkn(k，nEA〇 汲極控制端 GN 控制端 GP 控制端 Sjk(j,keA〇 源極控制端 WLjkn (j,k,n^N) 區域字元線 VP 外部信號 Block 1 〜k 區塊 Sector jk(j,ke N) 區段 DECj(jeA〇 解碼訊號 12Read(s) Read(u) Read(u) PGM(s) PGM(u) PGM(u) ER(s) ER(u) D Vread Vread Vss Vpp Vpp Vss Vss V Vss Vss Vss Vss Vss Vng Vss GP VH Vss VH VHP Vss VHP Vng Vss Vccs Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vngs Table 1 When the area word line driver is selected, ie (s) state, in read mode Read (s) 'the control terminal GP transmits a first control signal (VH) having a high voltage level to the gate terminal of the first transistor QD to open the first transistor QD, so that the gate control terminal D transmits The bungee control signal (in this case, Vread) can be passed to the region sub-line WL' to cause the corresponding stunner unit to perform the reading process. Wherein, in the read mode, the second control signal transmitted from the control terminal GN to the second transistor QE is a low voltage level vss, and in the series connection mode 201227742, the second transistor QE is not opened, therefore, The low voltage level vss applied to the source terminal of the second transistor QE through the source control terminal S is not transferred to the region word line WL. Similarly, when the regional word line driver is selected, the first control signal (VHP) having a high voltage level transmitted by the PGM(s) 'control terminal GP in the programming mode turns on the first transistor QD, so that The drain control terminal d and the pole control signal (in this case, Vpp) can be transferred to the region word line WL ' to cause the corresponding memory unit to program. In the erase mode ER(s), the control terminal GP transmits a first control signal (Vng) having a negative voltage level to the gate terminal of the first transistor QD, and the control terminal Gn transmits a low voltage level. The second control signal (Vss) to the gate terminal of the second transistor QE, in the series mode of the present invention, the second transistor QE can be opened, so that the source of the source control terminal s is transmitted The pole control signal (in this case, Vng) can be transferred to the area word line WL, so that the corresponding memory unit is erased. When the regional word line driver is not selected, that is, the (u) state, a read mode Read (u) and a programming mode pgm(u) in the table also apply to the first transistor QD and the second transistor QE. A voltage opposite the different levels in the select mode is applied to control the voltage signal applied by the regional word line driver 200 to the regional word line WL. Wherein, when not selected, the second read mode Read(u) in the table can control the output of the regional sub-wire driver 200 by the voltage signal transmitted by the gateless control terminal d. When the regional word line driver is not selected and is in the erase mode ER(u), the first and second transistors QD and QE can receive the same low 201227742 voltage level signal Vss, so that the area character is The output of line driver 200 is floating. The operational state of Table 1 is merely an example, and other operational states are still applicable to the regional word line driver of the present invention and can achieve the same purpose. For example, when not selected and in the erase mode, the source control signal transmitted by the source control terminal S may be floating. Please also refer to Figures 3A and 3B at the same time, which is a plan view of the left and right portions of the overall word line driver structure according to the area word line driver of Figure 2, wherein the overall word line driver structure is in the figure The representation is divided into a left part and a right part, which are put together to form an overall circuit plan. The overall word line driver structure includes a plurality of blocks Block 1 to k corresponding to the memory cells in the memory array, each block having a plurality of sectors Sector 11 to jk (j, kEA〇, and each segment Having a plurality of word line lines and having a plurality of area word line drivers 200 driving the word lines. All sectors under the same line have corresponding global word line decoders 202j (jeA〇, the global word lines) The decoder 202j has a first control terminal GP and a second control terminal GN for respectively sending the first control signal and the second control signal to the coupled first transistor QD and second transistor QE (please refer also to Fig. 2) At the same time, referring to the figure, the 汲 extremes of the first transistor QD of the area word line driver 200 on the same row (e.g., line 11) are all coupled to the same drain control terminal D (for example: D11), that is, the control line of the drain control terminal D will span the memory array and drive the word line driver 200 in the same row. In an embodiment, the global word line decoder 202j includes One ί \· 201227742 a drive 202a and a first The second driver 202b corresponds to the first control terminal GP and the second control terminal GN. The first driver 202a is controlled by an external signal VP, and the second driver 202b can be an inverter. A global word line decoder 202j is controlled by the corresponding decoding signal DECj (jeA〇, and outputs a specific voltage (refer to Table 1) to the first transistor QD and the first by the first driver 202a and the second driver 202b. Dimorph QE. In the embodiment of Figures 3A and 3B, the first transistor QD of the regional word line driver 200 on the same row (e.g., row 11) is coupled in a block. Connected to the same bucker terminal D (for example: D11). Therefore, in the same block of the same row, the order of the first transistor QD and the second transistor QE is exactly the same. On the contrary (please refer to FIGS. 3A and 3B), similarly, the corresponding first driver 202a and second driver 202b are also the same, so that the circuit area can be reduced. As shown in FIGS. 3A and 3B, adjacent two segments ( For example, sector 21 and sector 31) share the same bungee control Terminals D11, D12, Dln, Dkl, Dk2, Dkn, etc. Also in 'programming mode' because the voltage required for the area word line is close to 10 volts, and the first transistor QD is turned on (to turn the voltage of the drain terminal) Subtracting the threshold voltage value Vth in the transistor and transmitting it to the word line) needs to make the voltage received by the gate terminal (from the voltage of the external signal VP) larger than the voltage of the gateless control terminal, in order to minimize the externality The voltage of the signal VP, the first transistor in each local word line driver will use a transistor with a lower threshold voltage value. 201227742 In summary, the number and types of transistors used in a local word line driver are only two NMOS transistors, which can reduce the die size and save more area for the memory unit. use. The invention has been described above by way of a preferred example. It should be understood that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be within the scope of the invention. Therefore, the scope of protection of the present invention is defined by the scope of the patent application. [Simple description of the drawing] Fig. 1 is a circuit diagram of a region word line driver of a conventional inverse type or flash memory. Figure 2 is a circuit diagram of an area word line driver in an embodiment of the present invention. Figure 3A is a left side plan view of the area word line driver applied to the overall word line driver structure in accordance with Figure 2. Figure 3B is a plan view of the right portion of the area word line driver applied to the overall word line driver structure in accordance with Figure 2. [Main component symbol description] 100 area word line driver 102 global word line decoder 200 area word 7G line driver 202a first driver 201227742 202b second driver 202j (jEA 〇 global word line decoder QA PMOS transistor QB An NMOS transistor QC a second NMOS transistor QD a first transistor QE a second transistor Dkn (k, nEA 控制 gate GN control terminal GP control terminal Sjk (j, keA 〇 source control terminal WLjkn (j, k, n^N) area word line VP external signal Block 1 ~ k block sector jk (j, ke N) section DECj (jeA 〇 decoding signal 12