200837762 七、 指定代表圖： (一) 本案指定代表圖為：第（四）圖。 (二) 本代表圖之元件符號簡單說明： 1〇字元線驅動器200837762 VII. Designation of representative representatives: (1) The representative representative of the case is: (4). (2) A brief description of the component symbols of this representative figure: 1〇字线线驱动器
Ml電晶體 M2電晶體 八、 if若有化學式時，請揭#最能顯示發明特徵的化學 (無） 九、 發明說明： 【發明所屬之技術領域】 本發明係關於-種轉體記憶體，尤指—樹_記憶體之 字元線驅動器改進設計。 心一 【先前技術】 按，最被廣泛使用於半導體積體電路以及非揮發性記憶體 之記憶體矩陣結構係為N0R(反或)型。在此類型結構之°中二同 為一列之圮憶體晶胞的閘極端係為共連，同為一行之記憶體晶 胞的及極端係為共連，而其源極端係為在—區段内之所有晶胞 所共旱。第一圖揭示美國專利公告第6515911號所描述習知之 NOR型矩陣圖，其每一記憶體晶胞位置係藉由一選定的行以及 4 200837762 所蚁’故選定的行以及選定的列之交會處即為記 二曰1之位置。每—記憶體晶胞均包含有汲極端、源極端以 妒2端’如習知技術所述’其源極端、没極端以及閘極端係 根據執行觀、程式化献抹_操作來施加偏麼。 〜非揮發性記紐其巾之—的舰就是錢將儲存於其内之 貧料騎群崎除，而嫌難是唯―需要麵極端施加偏壓 的，程’由於所有記憶體晶胞之源極端為共連，因此晶胞可以 被單獨的以或是讀取，但是必為同時地被抹除。 寺另i疋决閃^己丨思體，其抹除過程是經由複數個區段來完 成’且所有源極端(線)共連之記憶體晶胞必定同時被抹除。在 非㈣性峨體矩_，各區段可織成複數顺複數行的 型式。在__射’區段之大顿由其包含之觸數量來 決定，且此敏髓龍的結構絲據 效率以及可靠度來設計出適合的區段數量及大小。吏用面積 、由於汲極應力gainst·)的關係’通常單一位元線是無法 被所有的區段所制’因此，各區段均被配置包含有—複數行 的特別群組’即為局部字元線(1〇cal bit Hne)。區域字元線係經 由一傳遞閘(pass gate)與獨立的一主位元線(main阶㈣連 接，各區段亦配置有-傳遞電晶體的局部群組，其通常是位於 位址區段内’且均保持關閉的狀態。因此，其他區段之晶胞並 不會透過汲極應力(drain stress)而互相影響。 200837762 電路公告第6515911號中揭示習知的- /、料非揮發性記憶體矩陣的習知結構，且其 係被組織朗型。記憶體 , 同為，胞之所有 ^ 各區段均具有—_之列解碼II，而全體行解奶 亦於此被提供。此_結構相域每—區段提供—列 以及複數局部行解碼器來避免汲極應力的現象，而佔據非^ 的電路面積。 佩非吊夕 /第三圖亦同為朗專利公告第65刪號中揭示習知的一 電路圖/、係將轉發性記鋪_喊為㈣。在此結構中， 所有區㈣各狀行方向料共連，可使各位元線之寄生電容 相對較低，_在讀取離勸料，提供難⑽益。此外， =:可為數個區段所共用，可節省電路之面積。雖然此結 構具有柄優點’但其主要缺點係絲次在—晶胞定址時，位 於同-列上之其他晶胞，亦會被施力姻，造成所謂的閘極應力 (gate stress) 〇 有宴於習知結構之缺慽，美國專利公告第65臟號提出了 -種階層柳⑽㈣)的列解碼方式，在其一實施例中，閣述 了-種可實·解碼之階層式方柄電路裝置，並可應用於且 有記憶體晶胞矩陣且其g係組織成行_轉發性半導體記 憶裝置。記㈣之每-區段均具有—區域字元線騎定群組， 200837762 其均獨立的與所有列共連區段之主字元線連接。在美國專利公 告第6515911號中描述了一種三電晶體結構來實現階層式 (hierarchical)的列解碼。 當驅動器週邊電晶體在設計時，因為必須要能夠承受後續 偏的此加而無法與晶胞尺寸成比例的縮小來降低其尺寸時， 用於NOIU吉才冓列解碼器之字元線驅動器設計係顯得愈來愈重 要。^此’當晶胞尺指小時，字元線軸H將佔據整體電路 中非常大的佈局(lay〇uy)面積。儘管美國專利公告第化㈣隱 所述之階層式(hie_hie_ _碼方式具有數概點，但亦會 佔據非常多受重視的面積，因此難以堪稱實用。 有鑑於上述字元線驅動器之缺憾，本發明人有感其未至漆 完善，遂竭盡心智，悉心研究克服，憑從事_產業多年之經 以 驗累積，進而研發出一種反或快閃記憶體之字元線驅動器 達到縮小尺寸之功效者。 【發明内容】 ，是，本發明之主要目的，即在於提供 體之字元線鶴H，可_削、尺寸之魏者。反⑽閃此 為達上述目的，本發明之技術實現如下： 各區段具有-與魏局部字 二之4體S日胞’且 線，、Α 5之主字元線。該各局部字 200837762 元線係分靡由-局部字元線鶴電路無主字元線減，該 局部字元_動f路主要係nM0S (金氧半）電晶體 ，及-第二MQS (金氧半）電晶體所組成，該第—M〇s (金 氧半）電晶體_胁其對應之該主字元、_及該局部字元線 之間’且該第二MOS (金氧半）電晶體係祕於其對應之該 局部字元線以及一第一偏壓端之間。 “為讓本發明之上述和其它目的、特徵和優點能更明顯易 懂’下文特舉健實酬，並配合所賴式，作詳細說明如下。 【實施方式】 =元線驅動态電路係用以提昇被選到字元線的電塵至一目 標電壓，亦可提供被選到晶胞之位址的最後解碼，且每一字元 線均伴隨著有-字元線驅動II電路。隨著佈局以及製程技術的 改進，δ己丨思體陣列中的晶胞間距係被佈局的更加細窄，而當字 元線也愈來愈靠近的同時，字元線驅動器電路的尺寸亦可以隨 之的縮小。本發明字元線驅動器之設計係藉由限制字元線驅動 ，内的操作元件數量來縮小其尺寸，而於本發明中所揭示之偏 壓狀態係為本發明之字元線驅動器操作能力的一例。 第八圖係為平行式(parallel)快閃記憶體晶胞陣列與串列式 (serial)快閃記憶體晶胞陣列之比較圖，如圖所示··在平行式 (parallel)快閃記憶體晶胞陣列中，各區段並沒有共用一p井，各 區段通常被分成64千位元組(KB)個部份，且抹除過程係經由區 段來執行。在串列式(serial)快閃記憶體晶胞陣列中，其陣列係 被組織成複數區塊，每一區塊含有16個區段，且每一區段具有4 200837762 千位元組(KB)的圮彳思體容量，而每一區塊内之各區段係共用一 p井，但與其他區塊之P井則並未共用。 第六圖係為本發明平行式快閃記憶體裝置之字元線驅動器 組織方塊圖，如圖所示：雖然圖中僅顯示二區塊(〇，丨），但眾所 周知，一般平行式快閃記憶體包含有16個區段(8MB，g卩8〇〇萬 位元組）、32個區段(16MB)、64個區段(32MB)、128(64MB)或是 256個區段(128MB)，且每一區段包含64千位元組(KB)的記憶體 ，罝，並經由16條主字元線(mainw〇rdl㈣MWLn[〇:1习施加偏 壓。每一條主字元線係分別經由其對應的16個局部字元線驅動 口口 wldrv[0.15]而與 16條局部字元線(i〇cai w〇r(j iine)LWLn依序 耦接，故每一區段均含有256條局部字元線LWLn[0:255]。 第七圖係為本發明串列式快閃記憶體裝置之字元線驅動器 組織方塊圖，如圖所示：雖然圖中僅顯示二區塊(〇，!），但眾所 周知，一般串列式快閃記憶體裝置包含有16個區塊，每一區塊 包含64千位元組(KB)的記憶體容量，而區塊内之各區段係分別 經由其對應之16條主字元線MWLn[0:15]來進行存取的操作，且 每一區段包含4千位元組(KB)的記憶體容量。每一條主字元線 係分別經由其對應的16個局部字元線驅動器wldrv[〇:15]而與16 條局部字元線(local word line)LWLn依序耦接，故每一區塊均含 有256條局部字元線LWLn[0:255]。 ”第四圖與第五圖係為本發明利用二電晶體組成字元線驅動 器，並應用於非揮發性反或型快閃記憶體陣列區段組織成行型 或其他型式之實施電路圖，如圖所示··本發明之二電晶體字元 線驅動器特別適合於連接記憶體矩陣結構來使用，而此記憶體 9 200837762 矩陣之每一區段均包含有一主字元線以及複數局部字元線，且 各區段係分別經由如第四圖或第五圖中的字元線驅動器丨〇、 10A而與主字元線耦接。 對NMOS晶胞的結構而言，於抹除過程中，ρ井的偏壓會被 拉升，而被選擇到的字元線會被施加負電壓。對串列式快閃記 憶體而言，在進行區段抹除(同相對之區塊抹除)時，在被選擇 到區塊内的未被選擇區段，會經由被選擇到區段且與其共連之 晶胞的Ρ井偏壓而遭受抹除干擾，而本發明係著重於降低此 除干擾。 第四圖揭示本發明二電晶體字元線驅動器10之實施例圖， 與習知技術很類似地，本發明之每一局部字元線包含2048個 nor(反或)晶胞。供每條局部字元線使用之字元線驅動器⑺主 要係由：MOS電晶體]VQ、M2所組成，而複數局部字元線係分 別共用一條由訊號MWLn[m]施加偏壓的主字元線。電晶體]^1 係為一PMOS電晶體，其源極端係耦接訊號]^评£11[111]，其汲極 端係搞接至NMOS電晶體M2之汲極端，且此_之汲極端係可 分別提供讀取、程式化或是抹除偏壓1；^1^[111]至各局部字元 線。NMOS電晶體M2之源極端係耦接於偏壓訊號，而 NMOS電晶體M2與PMOS電晶體M1之本體(bulk)係各自與其源 極端耦接。電晶體Ml之閘極端係接收控制訊號GMn[m]，而電 晶體M2之閘極端係接收控制訊號GNn[m]。 本發明實施例於程式化期間時，未被選擇的局部字元線係 被施加ον(伏特）之偏壓，甚至是被施加負電壓，如_〇5¥或 -1.0V，用崎低未被選擇晶胞共祕元線義電流機會。 200837762 下列表中揭示當本發明字元線驅動器i 0應用於平行式快閃 記憶體之一區段一區段抹除時的操作偏壓狀態，且記憶體之各 區段並未共用ρ井(參閱第八圖）。下列表中揭示三種偏壓狀態： ⑻局部字元線LWL0[0]被讀取時，⑼局部字元線LWLO[〇；J被程 式化時，以及(c)區段0被枝险日矣Ml transistor M2 transistor VIII, if if there is a chemical formula, please uncover # chemistry that can best show the characteristics of the invention (none) IX. Description of the invention: [Technical field of the invention] The present invention relates to a kind of swivel memory, In particular, the tree-memory word line driver is improved. Heart One [Prior Art] The memory matrix structure that is most widely used in semiconductor integrated circuits and non-volatile memory is N0R (reverse or) type. In this type of structure, the gate terminal of the memory cell is a co-join, and the memory cell and the extremity of the same row are co-connected, and the source extremity is in-region. All the unit cells in the segment are altogether. The first figure reveals a conventional NOR-type matrix diagram as described in U.S. Patent Publication No. 6515911, in which each memory cell position is intersected by a selected row and the selected row and selected column of 4 200837762 The location is the location of the second. Every memory cell contains a 汲 extreme, and the source is 妒 2 end 'as described in the prior art'. The source extreme, no extreme, and the gate extremity are biased according to the execution view, stylized devote . ~ The non-volatile record of the towel - the ship is the money that will be stored in the poor material riding in the group, and the suspicion is only the need to face extreme bias, Cheng 'since all memory cells The source terminals are connected in common, so the unit cells can be read individually or in the same way, but must be erased at the same time. The temple is also a flash, and the process of erasing is done through a plurality of segments, and the memory cells of all source terminals (lines) must be erased at the same time. In the non-(four) sex body moment _, each segment can be woven into a complex number of complex numbers. The size of the __shot section is determined by the number of touches it contains, and the structure of the Mindosaurus is designed to fit the number and size of segments according to efficiency and reliability. The area of the 、, due to the relationship of the buckling stress gains·) 'usually a single bit line cannot be made by all the sections'. Therefore, each section is configured to contain a special group of -multiple rows'. Word line (1〇cal bit Hne). The area word line is connected to a separate main bit line (main stage (4) via a pass gate, and each section is also configured with a local group of transfer transistors, which is usually located in the address section The inner cells are kept in a closed state. Therefore, the cells of the other segments do not interact with each other through the drain stress. The conventionally disclosed - /, material non-volatile is disclosed in the circuit publication No. 6515911 The conventional structure of the memory matrix, and its structure is organized. The memory, the same, all the cells of the cell have a -_ column of decoding II, and all the milk is also provided here. _Structure phase domain provides a column and a complex local row decoder for each segment to avoid the phenomenon of the buckling stress, and occupy the circuit area of the non-^. The peony eve/third figure is also the 65th In the number, a circuit diagram is disclosed, and the forwarding property is screamed as (4). In this structure, all the regions (4) are connected in a row direction, so that the parasitic capacitance of each element line is relatively low, _ In reading from the persuasion, it provides difficulty (10) benefits. In addition, =: can be several segments Sharing, can save the area of the circuit. Although this structure has the advantage of the handle 'but its main disadvantage is that the cell is located at the same time, the other unit cells located on the same column will also be applied, resulting in the so-called Gate stress has the drawback of accommodating the conventional structure. The US Patent Publication No. 65 has proposed a column decoding method for the hierarchical layer (10) (four). In one embodiment, the species is described. A hierarchical block circuit device that can be decoded and decoded, and can be applied to a memory cell matrix and its g system is organized into a row-transit semiconductor memory device. Each of the segments (4) has a regional word line riding group, 200837762 which is independently connected to the main character lines of all column co-connected segments. A three-crystal structure is described in U.S. Patent No. 6,515,911 to achieve hierarchical column decoding. When the driver peripheral transistor is designed, it must be able to withstand the subsequent bias and cannot be scaled down to reduce the size of the cell. The word line driver design for the NOIU The department is becoming more and more important. ^This's when the cell ruler is small, the word spool H will occupy a very large layout (lay〇uy) area of the overall circuit. Although the United States Patent Announcement (4) implicitly described the hierarchical style (hie_hie_ _ code method has a number of points, but it will occupy a very large area of attention, so it is difficult to be practical. In view of the above-mentioned word line driver's shortcomings, The inventor has felt that he has not perfected the paint, exhausted his mind, carefully studied and overcome it, and developed a kind of reverse or flash memory word line driver to achieve the effect of reducing the size by engaging in the accumulation of years of experience in the industry. [Invention] The main purpose of the present invention is to provide a character line crane H, which can be cut and dimensioned. The inverse (10) flash is the above purpose, and the technical realization of the present invention is as follows : Each section has - the main character line of the four-body S-day cell of the Wei-local word two and the line, and the main character line of the Α 5. The local word 200837762 yuan line system is divided by the - local word line crane circuit without the main word The main line is reduced, and the local character_moving f is mainly composed of nM0S (gold oxide half) transistor, and - second MQS (gold oxide half) transistor, the first M?s (gold oxide half) electricity The crystal_the corresponding main character, _ and the local character Between the lines 'and the second MOS (gold oxide half) transistor system is between its corresponding local word line and a first bias terminal. "To achieve the above and other objects, features and features of the present invention The advantages can be more obvious and easy to understand. 'The following special health rewards, and with the dependent style, are described in detail below. [Embodiment] = Elementary line drive state circuit is used to enhance the electric dust selected to the word line to one The target voltage can also provide the final decoding of the address selected to the cell, and each word line is accompanied by a word-line driven II circuit. With the improvement of layout and process technology, The cell pitch in the array is more narrowly laid out, and as the word lines are getting closer together, the size of the word line driver circuit can be reduced accordingly. The design of the word line driver of the present invention is By limiting the number of operating elements within the word line drive, the size is reduced, and the bias state disclosed in the present invention is an example of the operation capability of the word line driver of the present invention. (parallel) flash memory cell array and Comparison of serial flash memory cell arrays, as shown in the figure... In a parallel flash memory cell array, each segment does not share a p-well, each segment It is usually divided into 64 kilobytes (KB) parts, and the erasing process is performed via sections. In a serial flash memory cell array, its array is organized into complex areas. Block, each block contains 16 segments, and each segment has a volume of 4 200837762 kilobytes (KB), and each segment in each block shares a well. However, it is not shared with the P wells of other blocks. The sixth figure is a block diagram of the character line driver of the parallel flash memory device of the present invention, as shown in the figure: although only two blocks are shown in the figure ( 〇,丨), but as we all know, the general parallel flash memory contains 16 segments (8MB, g卩8 million bytes), 32 segments (16MB), 64 segments (32MB) 128 (64MB) or 256 segments (128MB), and each segment contains 64 kilobytes (KB) of memory, 罝, and via 16 main word lines (mainw〇rdl(4)MWLn[ 〇: 1 applies bias. Each of the main character lines is sequentially coupled to the 16 local word lines (i〇cai w〇r(j iine)LWLn via their corresponding 16 local word line drive ports wldrv[0.15], respectively. Therefore, each segment contains 256 local word lines LWLn[0:255]. The seventh figure is a block diagram of the character line driver of the in-line flash memory device of the present invention, as shown in the figure: Only two blocks (〇, !) are shown in the figure, but it is well known that a general tandem flash memory device includes 16 blocks, each block containing a memory capacity of 64 kilobytes (KB). And each segment in the block is accessed by its corresponding 16 main character lines MWLn[0:15], and each segment contains 4 kilobytes (KB) of memory. Capacity: Each main character line is sequentially coupled to 16 local word lines LWLn via its corresponding 16 local word line drivers wldrv[〇:15], so each area The blocks each contain 256 local word lines LWLn[0:255]. The fourth and fifth figures are the present invention using a two-transistor to form a word line driver and applied to non-volatile The reverse-type flash memory array segment is organized into a row or other type of implementation circuit diagram, as shown in the figure. The second transistor word line driver of the present invention is particularly suitable for use in connection with a memory matrix structure, and this memory Each segment of the matrix 9 200837762 includes a main word line and a plurality of local word lines, and each segment is respectively connected via a word line driver 丨〇, 10A as in the fourth or fifth figure. The main word line is coupled. For the structure of the NMOS cell, during the erasing process, the bias of the p well is pulled up, and the selected word line is applied with a negative voltage. In the case of flash memory, when performing segment erase (with the opposite block erase), the unselected segments selected in the block are selected and connected to the segment. The cell's well bias is subject to erase interference, and the present invention focuses on reducing this interference. The fourth figure reveals an embodiment of the two-diodian word line driver 10 of the present invention, similar to the prior art. Each local word line of the present invention contains 2048 nor (reverse) crystals The word line driver (7) for each local word line is mainly composed of: MOS transistor]VQ, M2, and the plurality of local word lines respectively share a bias voltage applied by the signal MWLn[m] The main character line. The transistor]^1 is a PMOS transistor, the source terminal is coupled to the signal]^££[111], and the 汲 extreme is connected to the 汲 terminal of the NMOS transistor M2, and this The _ extremes can provide read, program, or erase bias 1; ^1^[111] to each local word line. The source of the NMOS transistor M2 is coupled to the bias signal, and The bulk of the NMOS transistor M2 and the PMOS transistor M1 are each coupled to their source terminals. The gate terminal of the transistor M1 receives the control signal GMn[m], and the gate terminal of the transistor M2 receives the control signal GNn[m]. In the embodiment of the present invention, during the stylization period, the unselected local character line system is applied with a bias of ον (volts), or even a negative voltage is applied, such as _〇5¥ or -1.0V, with a low level. The unit cell is selected as the common source of the current line. 200837762 The following table discloses the operation bias state when the word line driver i 0 of the present invention is applied to a segment of a parallel flash memory, and the segments of the memory do not share the p well. (See Figure 8). The following three types of bias states are disclosed in the following table: (8) When the local word line LWL0[0] is read, (9) the local word line LWLO[〇; J is programmed, and (c) the sector 0 is in danger.
下列表中揭示當本發明字元線驅動器ίο應用於平行式快跑7 憶？(如第六圖⑽及串列歧閃記碰(如第七圖)的操作壓 狀悲。此外’下列表巾魄塊抹除狀態可應驗串 憶體的區塊抹除或是平行式_記憶體祕段抹除，而區= 除狀態則可顧於串列式快閃記㈣的區段抹除。域 11 200837762 讀取 程式 程式化- 區塊抹 區段抹 軟程式 軟程式 化-1 2 除 除 化-1 化-2 MWL0[0】 5V 8V 8V -7.5V -7.5V vcc VCC MWL0[1:15] ov OV -0.5V -7.5V 2.5V vcc vcc MWLn[0:15] vcc vcc VCC VCC VCC vcc vcc GM0[0] -2V -2V 8V->0V -10V -10V vcc vcc GN0[0] OV OV 8 V —OV -10V -10V vcc vcc GM0[1:15] 5V 8V 8V -10V -10V vcc vcc GN0[1:15] 5V 8V 8V -10V -10V vcc vcc GMn[0:15] VCC VCC VCC vcc vcc vcc vcc GNn[0:15] vcc VCC VCC vcc vcc vcc vcc VNEG[0】 ov OV -0.5V -7.5V -7.5V -0.5V ov VNEG[n] ov ov OV ov ov ov ^ ov LWL0[0] 5V 8V 8V -7.5V -75V -0.5V ov LWL0[1:15] ov OV -0.5V -7.5V -7.5V -0.5V ov LWL0[16:255] ov OV -0.5V -7.5V 2.5V -0.5V ov LWLn[0:255] ov ov OV OV OV OV ov 上列二表揭示二種被稱為程式化-1以及程式化-2之交替的 (程式化狀態，軟程式化狀態亦被揭示。在局部字元線LWL0[0] 的程式化期間，未被選擇的字元線(LWL0[1:255]以及 LWLn[0:255])係被施加〇V(接地)的偏壓(程式化_1的狀態）。在程 式化-2的狀態時，被選擇到的區段〇之局部字元線LWL0[1:255] 係被施加如-0.5V或-L0V的負電壓，用以降低未被選擇字元線 中共用位元線晶胞的漏電流機會。對GM0[0]以及GN0[0]來 說，”8V^0V”代表一開始的8V係用於傳遞-0.5V至所有的字元 線，隨後變成0V則代表傳遞8V至被選擇到的字元線，而上述之 12 200837762 狀恶係假設NMOS電晶體的的臨限電虔大於〇·5ν而言。 在上述表中，除了主字元線MWL〇[1:15]及其相關之局部字 元線LWL〇[16:255]的偏壓外，串列式快閃記憶體的區塊抹除與 串列式快閃記憶體的區段抹除所施加的偏壓均為相同。在串列 式快閃記憶體進行區段抹除的期間，未被選擇的區段係於其字 元線上施加一如2,5V的正電壓，用以降低抹除干擾，而N〇R晶 胞的P井一般則會被施加6λ^|]8ν的電壓。字元線上的正偏壓係 可降低從Ρ井到未選擇字元線的電壓降，因此可降低抹除干擾。 眾所周知，軟程式化具有在抹除過程之後修正過度抹除晶 胞的功能，在軟程式化的過程中，字元線電壓並不會被設定在 8V ’而疋會被设定在〇ν或是如_〇·5γ或-1·〇ν的負電壓。 由於在抹除以及當程式化_2以及軟程式化_ 1之偏壓狀態均 利用一負電壓訊號VNEG，因此NMOS電晶體M2最好為一具有 二井(triple well)之NMOS電晶體，且此NMOS電晶體之本體必 需施被加最大的負偏壓。若欲使用一般2NM〇s電晶體，則其 本體必須為P型且其電位為VSS。 第五圖揭示本發明二電晶體字元線驅動器丨〇A應用於平行 式快閃記憶體(如第六圖）以及串列式快閃記憶體(如第七圖）的 之實施例圖，如圖所示：本發明供每條局部字元線1^^1^[111]使 用之字元線驅動器10A主要係由二MOS電晶體M3、M4所組成， 其係耦接於其各自的主字元線(MWLn[m])以及標示為VNEG[n] 的端點之間。 下列表中揭示第五圖施加偏壓的狀態，此偏壓狀態係可應 用於使用本發明雙NOMS字元線驅動器10A的串列式以及平行 13 200837762 式快閃記憶體陣列。此外，下列表中的區塊抹除狀態可應用於 串列式快閃5己憶體的區塊抹除或是平行式快閃記憶體的區段抹 除，而區段抹除狀態則可應用於串列式快閃記憶體的區段抹 除。在此處程式化的過程中，會將未被選擇的局部字元線 (LWL0[1:255]以及 LWLn[0:255])設定為 0V 或是如 _〇ϋ 或 _1〇v 的負電壓。As shown in the following table, when the character line driver ίο of the present invention is applied to the parallel run 7 memory? (As shown in Figure 6 (10) and serial strobe flash (as shown in Figure 7), the operation of the following table can be used to eliminate the block erase or parallel _ memory. The secret segment is erased, and the area = except the state can be considered for the segment erase of the serial flash (4). Domain 11 200837762 Read program stylization - block erase segment software soft program -1 2 Divide-1 -2 MWL0[0] 5V 8V 8V -7.5V -7.5V vcc VCC MWL0[1:15] ov OV -0.5V -7.5V 2.5V vcc vcc MWLn[0:15] vcc vcc VCC VCC VCC vcc vcc GM0[0] -2V -2V 8V->0V -10V -10V vcc vcc GN0[0] OV OV 8 V —OV -10V -10V vcc vcc GM0[1:15] 5V 8V 8V -10V -10V vcc vcc GN0[1:15] 5V 8V 8V -10V -10V vcc vcc GMn[0:15] VCC VCC VCC vcc vcc vcc vcc GNn[0:15] vcc VCC VCC vcc vcc vcc vcc VNEG[0] ov OV -0.5V -7.5V -7.5V -0.5V ov VNEG[n] ov ov OV ov ov ov ^ ov LWL0[0] 5V 8V 8V -7.5V -75V -0.5V ov LWL0[1:15] ov OV -0.5V -7.5V -7.5V -0.5V ov LWL0[16:255] ov OV -0.5V -7.5V 2.5V -0.5V ov LWLn[0:255] ov ov OV OV OV OV ov Listed above Reveal two kinds of being called The stylized -1 and stylized - 2 alternates (stylized state, soft stylized state is also revealed. During the stylization of the local word line LWL0[0], the unselected word line (LWL0[1 :255] and LWLn[0:255]) are applied with a bias voltage of 〇V (ground) (state of stylized_1). In the state of stylized-2, the local word of the selected segment The line LWL0[1:255] is applied with a negative voltage such as -0.5V or -L0V to reduce the leakage current of the common bit line cell in the unselected word line. For GM0[0] and GN0 [0], "8V^0V" means that the first 8V is used to pass -0.5V to all the word lines, and then to 0V means that 8V is passed to the selected word line, and the above 12 200837762 The system assumes that the threshold power of the NMOS transistor is greater than 〇·5ν. In the above table, in addition to the bias of the main word line MWL 〇 [1:15] and its associated local word line LWL 〇 [16: 255], the block erase of the tandem flash memory and The bias voltage applied to the segment erase of the tandem flash memory is the same. During the segment erase of the tandem flash memory, the unselected segment is applied with a positive voltage of 2,5 V on its word line to reduce the erase interference, while the N〇R crystal The P well of the cell is generally applied with a voltage of 6λ^|8v. A positive bias on the word line reduces the voltage drop from the well to the unselected word line, thus reducing erase interference. As we all know, the soft stylization has the function of correcting the excessive erasing of the unit cell after the erasing process. During the soft programming process, the word line voltage is not set at 8V' and the 疋 will be set at 〇ν or It is a negative voltage such as _〇·5γ or -1·〇ν. Since the negative voltage signal VNEG is utilized in the erase and when the bias state of the program_2 and the soft programming_1 is utilized, the NMOS transistor M2 is preferably an NMOS transistor having a two-well (triple well), and this The body of the NMOS transistor must be applied with the largest negative bias. If a typical 2NM〇s transistor is to be used, its body must be P-type and its potential is VSS. FIG. 5 is a view showing an embodiment of a two-transistor word line driver 丨〇A of the present invention applied to a parallel flash memory (such as the sixth figure) and a tandem flash memory (such as the seventh figure). As shown in the figure, the word line driver 10A for use in each local word line 1^^1^[111] is mainly composed of two MOS transistors M3 and M4, which are coupled to their respective The main character line (MWLn[m]) and the endpoint labeled VNEG[n]. The state in which the fifth figure applies a bias voltage is disclosed in the following table, which is applicable to the tandem type of the dual NOMS word line driver 10A of the present invention and the parallel 13 200837762 type flash memory array. In addition, the block erase state in the following list can be applied to the block erase of the tandem flash 5 memory or the sector erase of the parallel flash memory, and the segment erase state can be Segment erase applied to tandem flash memory. During the stylization process, the unselected local word lines (LWL0[1:255] and LWLn[0:255]) are set to 0V or negative as _〇ϋ or _1〇v Voltage.
在第九圖中，若快閃記憶體晶胞需要15V來進 則串列式快閃記憶體中-區段—區段的抹_相對 一區塊抹除)會對未被選擇的區段造成贈的接面偏壓及5V^ 井干擾’而未被獅區段的局部字元線電_取決於接面偏壓 14 200837762 以及P井干擾之間的_。^日日胞僅需要低電麗即可 除，接面偏壓造成的p井干擾就會降低。若此為重點，則 之控制閘接與浮置祕間的輕合因子愈高以及穿隨氧化^ (umnel _e)的厚度㈣，抹除電_會愈低。這種方式亦^ 用於字元線驅動器10、10A。 與習知利用三個或三個以上電晶體所組成之字元線驅動器 ίί起來，，本發明彻二個電晶體所組成之字元線驅動器確實 節省了非常大的佈局面積。在程式化綱，NM〇s電晶體的間 極端係被施加1G.5V的·GM_，此麟大於主字元線電^ MWL0[0](通常為8V)，因此，全部的主字元線電壓均可以被傳 遞至局部字it線。NMOS電晶體M3之臨限電壓為Vth，局部字 70線LWL0[0]會根據主字元線的電壓而被施加最大為GM〇[〇] 減去Vth的偏壓。若主字元線電壓小於此偏壓的最大值，則全部 的電壓都可以被傳遞至局部字元線。故偏壓〇]^〇[〇]必須至少是 Vth加MWL0[0](主字元線電壓)以上，但這對pM〇s電晶體被選 到用來傳遞電壓時，並沒有類似的問題。PM〇s電晶體的閘極 端係被施加-2V的負偏壓GM0[0]或是接地電壓，用以傳遞全部 的主字元線電壓。在雙NMOS電晶體的實施例中，一分離之電 壓電路係用以提供一超過主字元線電壓值的電壓訊號，但此電 壓訊號係為一全體的訊號。習知技術中亦揭露非常多種的電路 來提供上述之電壓訊號，故於此不再詳述。就像其他高於vcc 的電壓，此電壓訊號可經由電荷泵以及調整器電路來產生，如 美國公告第5793679號專利以及美國公開第2〇〇5〇2〇7236號專利 均是。 15 200837762 —ϊί=ί發明之字元線鷄器係為被组織成具有肋⑽ 二，二 (包含控制邏輯、位址解竭電路、列及行解 馬裔或一般其他類似的模組)的積體電路。 标把啸料酬揭露如上，糾並_以限定 口本發明之字元線驅動器可用於串列式、 、他種類之轉發性記憶體，任何 ^ ，、4乾圍§視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 ^圖圖係為美國專利公告第6515911號所描述習知之N〇R型矩 美國專利公告第6515911號中揭示習知的—電路圖。 方塊圖 =五圖係為本發明二電晶體字元_騎之另—實施例圖。 弟六圖係為本發日胖行式朗記憶置之字元_動器組織 第七圖係為本發㈣狀㈣記憶《置之字元線鶴器組織 方塊圖。 第八圖係為平行式'_記憶體晶胞_與㈣式快閃記憶體晶 胞陣列之比較圖。 16 200837762 第九圖係為本發明施加偏壓之示意圖。 【主要元件符號說明】 10字元線驅動器 10A字元線驅動器 M1-M4電晶體 十、申請專利範圍： 1二觀或快閃記憶體之字樣_器，其係與—記憶體陣列 的《亥疏體陣列係具有若干組成為複數區段之記憶體晶 各區段具有與複數局部字元線組合之主料線，該 ° ^字7G線係分顺由—局部字元線驅純路與該主字元 線耦接，其特徵在於： 該字元線驅動電路主要係由一第 =:斤組成’該第-電晶體係_於其對應之該主她 字元線之間’且該第二電晶體係搞接於其對應之該局 4子疋線以及一弟一偏壓端之間。 2、★根據請求項i之反或快閃記憶體之字元線驅動器，其中，該 3字元_動器共連。 樹U項1之反或，_記憶體之字元線軸器，其中，該 弟一電晶體係為一 NMOS電晶體。 4、根據請求項3之反或快閃記憶體之字元線鶴器，其中，該 NMOS電晶體係為-具有三井之電晶體。 17In the ninth figure, if the flash memory cell needs 15V to enter, the in-line flash memory-segment-segment wipe_relative block erase will be unselected. The resulting junction bias and 5V^ well interference 'is not the local word line of the lion segment _ depends on the junction bias 14 200837762 and the _ between the P well interference. ^The day and the day only need low battery, the p-well interference caused by the junction bias will be reduced. If this is the point, the higher the lightness factor of the control gate and the floating secret, and the thickness of the oxide (umnel _e) (4), the lower the eraser _ will be. This method is also used for the word line drivers 10, 10A. With the conventional word line driver composed of three or more transistors, the word line driver composed of the two transistors of the present invention does save a very large layout area. In the stylized class, the inter-extremity of the NM〇s transistor is applied with 1G.5V·GM_, which is larger than the main word line circuit ^ MWL0[0] (usually 8V), therefore, all the main word lines The voltage can be passed to the local word it line. The threshold voltage of the NMOS transistor M3 is Vth, and the local word 70 line LWL0[0] is applied with a bias voltage of up to GM 〇 [〇] minus Vth according to the voltage of the main word line. If the main word line voltage is less than the maximum value of this bias, then all of the voltage can be passed to the local word line. Therefore, the bias voltage 〇]^〇[〇] must be at least Vth plus MWL0[0] (main word line voltage), but there is no similar problem when the pM〇s transistor is selected for transmitting voltage. . The gate terminal of the PM〇s transistor is applied with a negative bias of -2V GM0[0] or a ground voltage to deliver all of the main word line voltages. In an embodiment of the dual NMOS transistor, a separate voltage circuit is used to provide a voltage signal that exceeds the value of the main word line voltage, but the voltage signal is an overall signal. A wide variety of circuits are also disclosed in the prior art to provide the above described voltage signals and will not be described in detail herein. As with other voltages above vcc, this voltage signal can be generated via a charge pump and a regulator circuit, as disclosed in U.S. Pat. No. 5,793,679 and U.S. Patent No. 2,512,237. 15 200837762 —ϊί=ίInvented the word line chicken is organized into ribbed (10) 2, 2 (including control logic, address depletion circuits, columns and lines of solutions or other similar modules) Integrated circuit. The standard whistle remuneration is disclosed above, and the word line driver can be used for the serial type, and the forwarding memory of his type. Any ^, 4 dry § The scope is defined. BRIEF DESCRIPTION OF THE DRAWINGS The figure is a conventional circuit diagram disclosed in U.S. Patent Publication No. 6515911, which is hereby incorporated by reference. Block Diagram = Five Diagrams is a diagram of an embodiment of a two-transistor character_ride of the present invention. The sixth figure is the character of the fat-line type of memory. The seventh picture is the block diagram of the figure (4). The eighth figure is a comparison of parallel '_memory cell_and (iv) type flash memory cell arrays. 16 200837762 The ninth diagram is a schematic diagram of the application of a bias voltage according to the present invention. [Major component symbol description] 10 word line driver 10A word line driver M1-M4 transistor ten, patent application scope: 1 second or flash memory type _ device, its system and - memory array of "hai The body array has a plurality of memory crystals composed of a plurality of segments, and each segment has a main material line combined with a plurality of local word lines, and the β-word 7G line is divided into a local word line to drive the pure road and The main character line is coupled, wherein: the word line driving circuit is mainly composed of a first:: the first electro-optic system _ between the corresponding main character lines thereof and the The second electro-crystal system is connected between the corresponding four sub-wires and one of the two bias terminals. 2. According to the inverse of the request item i or the word line driver of the flash memory, wherein the 3-character_mover is connected in common. The inverse of the U-term 1 of the tree, the character-spindle of the memory, wherein the electro-optic system is an NMOS transistor. 4. The object of the inverse or flash memory word line according to claim 3, wherein the NMOS electro-crystalline system is a transistor having a Mitsui. 17