WO2023092290A1

WO2023092290A1 - Read only memory circuit, read only memory, and electronic device

Info

Publication number: WO2023092290A1
Application number: PCT/CN2021/132478
Authority: WO
Inventors: 袭著洋; 蔡江铮; 张雨晴; 布明恩
Original assignee: 华为技术有限公司
Priority date: 2021-11-23
Filing date: 2021-11-23
Publication date: 2023-06-01
Also published as: CN117546240A

Abstract

The present application relates to the technical field of storage, and provides a read only memory circuit, a read only memory, and an electronic device. The read only memory circuit comprises a transistor array, a switch circuit, a plurality of word lines, a plurality of bit lines, and a ground line. In the transistor array: a plurality of transistors located in a same row are connected in series in sequence, gates of a plurality of transistors located in a same column are connected to a same word line, and the plurality of bit lines are respectively arranged in one-to-one correspondence to transistors in different rows. The plurality of bit lines are connected to the ground line by means of the switch circuit. The transistor array comprises: a first transistor and a second transistor located in the same column and respectively located in two adjacent rows. The plurality of bit lines comprise: a first bit line corresponding to the plurality of transistors in the row where the first transistor is located, and a second bit line corresponding to the plurality of transistors in the row where the second transistor is located. A first electrode of the first transistor is connected to the first bit line, a second electrode of the first transistor is connected to a second electrode of the second transistor, and a first electrode of the second transistor is connected to the second bit line.

Description

Read-only memory circuit, read-only memory and electronic equipment

technical field

The present application relates to the technical field of storage, in particular to a read-only storage circuit, a read-only memory and electronic equipment.

Background technique

Read-only memory (ROM) is a semiconductor memory that works in a non-destructive readout mode, and can only read but not write information. The data stored in ROM is usually written in the chip manufacturing process. Once the information is written, it will be fixed. Even if the power is cut off, the information will not be lost, and the structure is relatively simple and easy to use. Therefore, it is often used to store various fixed programs and data. . Among them, the stored data of the mask type read-only memory (mask ROM) is programmed by the integrated circuit manufacturer, that is, factory programmed, and the stored data is provided by the customer to the manufacturer, and the data is converted into a custom mask layer. It ends up being stored in how certain metal wires are connected.

Mask ROMs are both more compact in terms of storage area per byte and at a lower cost than any other type of semiconductor memory. FIG. 1 is a memory circuit diagram of a mask ROM (hereinafter referred to as ROM) provided in the related art, and FIG. 2 is a memory cell layout corresponding to FIG. 1 . As shown in Figure 1 and Figure 2, in this ROM, it is necessary to insert a dummy (dummy) MOS between every two MOS (metal oxide semiconductor field effect transistor), as shown in Figure 1 in NMOS0 Inserting NMOSd between NMOS1 and NMOS1 will result in waste of memory cell area. In addition, in this ROM, two metal signal lines (bit line BL (bit line) and ground line VSS) need to be arranged above each row of MOS, which will also cause a waste of memory cell area.

Contents of the invention

Embodiments of the present application provide a read-only memory circuit, a read-only memory, and an electronic device, which can reduce the area of a memory unit.

An embodiment of the present application provides a read-only memory circuit, including a transistor array, a switch circuit, multiple word lines, multiple bit lines, and a ground line. The transistor array includes a plurality of transistors; wherein, in the transistor array: a plurality of transistors in the same row are connected in series in sequence, the gates of the plurality of transistors in the same column are connected to the same word line, and a plurality of bit lines are respectively connected to transistors in different rows One-to-one correspondence settings. The plurality of bit lines are connected to the ground line through the switch circuit. The transistor array includes: a first transistor and a second transistor located in the same column and respectively located in two adjacent rows; the plurality of bit lines include the first bit line and the second bit line; the first bit line and the first transistor are located The multiple transistors in the row correspond to each other, and the second bit line corresponds to the multiple transistors in the row where the second transistor is located. The first pole of the first transistor is connected to the first bit line, the second pole of the first transistor is connected to the second pole of the second transistor, and the first pole of the second transistor is connected to the second bit line.

In this read-only memory circuit, the first pole of the first transistor is connected to the first bit line, and the second pole of the first transistor is connected to the second bit line through the second transistor. In this case, when the word line is turned on The first transistor and the second transistor control the connection between the second bit line and the ground line through the switch circuit, so that the high potential stored on the first bit line can be pulled down to a low potential through the second bit line, and then the second bit line can be controlled to a low potential. Reading of a "0" signal in a transistor.

In addition, compared to the read-only memory circuit in the related art, dummy memory cells need to be arranged between adjacent memory cells, and two metal signal lines (bit lines, ground lines) need to be arranged above the memory cells. In the read-only storage circuit provided by the embodiment of the present application, each transistor is used as a storage unit for data storage, and there is no need to set up a dummy storage unit, which avoids the waste of storage area caused by the dummy storage unit; connection, the bit line corresponding to the next row of transistors can be connected to the ground wire, which can be used as the ground wire of the previous row of transistors to meet the storage requirements; and only the ground wire needs to be set separately for the last row of transistors to meet its storage requirements; it is equivalent to saving About half (50%) of the ground wire is removed, so that the area of the memory cell can be further reduced, and the density of the transistor array constrained by the metal line can be increased.

In some possible implementation manners, the transistor array further includes: a third transistor and a fourth transistor located in the same column and respectively located in two adjacent rows. The multiple bit lines include a third bit line and a fourth bit line; the third bit line corresponds to the multiple transistors in the row where the third transistor is located, and the fourth bit line corresponds to the multiple transistors in the row where the fourth transistor is located. The first pole of the third transistor is connected to the first pole of the fourth transistor, and the second pole of the third transistor is connected to the second pole of the fourth transistor. In this case, neither the first pole nor the second pole of the third transistor is connected to the corresponding bit line, so that when the third transistor is turned on through the word line, the stored high potential on the bit line will not changes, enabling the reading of a "1" signal.

In some possible implementation manners, the multiple bit lines include a fifth bit line, and the fifth bit line corresponds to the last row of transistors in the transistor array. The last row of transistors includes a fifth transistor; the first pole of the fifth transistor is connected to the fifth bit line or the ground line; the second pole of the fifth transistor is connected to the fifth bit line or the ground line. For the last row of transistors in the transistor array, the first pole and/or the second pole of some or all of the transistors are selectively connected to the ground to meet actual storage requirements.

In some possible implementation manners, the start terminals or ends of the plurality of transistors arranged in series in each row of the transistor array are connected to corresponding bit lines. By fixing the start or end (ie, source or drain) of the transistors in each row, and according to the requirement of storing data, the connection mode of the other end (ie, drain or source) of each transistor is sequentially set.

In some possible implementation manners, the transistor array includes n rows of transistors, where n is less than or equal to 32; thereby avoiding the potential impact on the subsequent bit lines due to the excessive number of bit lines located in the previous row, To ensure accurate readout of the stored data in each row of transistors.

In some possible implementations, transistors, bit lines, ground lines, and intermediate connection lines between transistors in adjacent rows are distributed on the first metal layer; multiple bit lines and ground lines are distributed on the second metal layer; the first The metal layer is located between the plurality of transistors and the second metal layer; the bit line and the ground line extend along the row direction of the transistor array; the intermediate connection line extends along the column direction of the transistor array; The location is right.

In some possible implementation manners, the position of the ground line is directly opposite to the position of the last row of transistors in the transistor array.

In some possible implementation manners, the bit line corresponding to the last row of transistors is the fifth bit line; the ground line is located on a side of the fifth bit line away from the transistor array.

The present application provides a read-only memory circuit, comprising: m rows and n columns of a plurality of transistors arranged in an array, m bit lines, n word lines and ground lines; m and n are both positive integers greater than or equal to 1 . Transistors in the same row are sequentially connected in series. The n word lines are respectively connected to the gates of the n columns of transistors in a one-to-one correspondence. The source of the transistor in the i-th row is connected to the i-th bit line, or connected to the source of the transistor in the same column in the i+1-th row. The drain of the transistor in the i-th row is connected to the i-th bit line, or connected to the drain of the transistor in the same column in the i+1-th row; 1≤i≤m-1, and i is a positive integer.

In some possible implementation manners, the sources of the transistors in the mth row are connected to the mth bit line or the ground line. The drains of the transistors in the mth row are connected to the mth bit line or the ground line.

Compared with the read-only memory circuit in the related art, dummy memory cells need to be arranged between adjacent memory cells, and two metal signal lines (bit line, ground line) need to be arranged above the memory cells, in this application In the storage circuit provided by the embodiment, each transistor is used as a storage unit for data storage, and there is no need to set up a dummy storage unit, which avoids the waste of storage area caused by the dummy storage unit; and by setting the connection between two adjacent rows of transistors, it can The bit line corresponding to the next row of transistors is connected to the ground wire as the ground wire of the previous row of transistors to meet the storage requirements; and only the ground wire needs to be set separately for the last row of transistors to meet its storage requirements; it is equivalent to saving about half ( 50%) of the ground line, so that the area of the memory cell can be further reduced, and the density of the transistor array constrained by the metal line can be increased.

In some possible implementation manners, the start terminals or ends of the multiple transistors arranged in series in m rows are all connected to the bit line. In this case, the connection mode of the other end (ie drain or source) of each transistor is sequentially set by fixing the start or end (ie source or drain) of the transistors in each row and according to the requirement of storing data.

In some possible implementation manners, the storage circuit further includes a switch circuit; the m bit lines are connected to the ground line through the switch circuit; the switch circuit is configured to control the connection between each bit line and the ground line. In this case, the m bit lines are connected to the ground line through the switch circuit, and the on-off between each bit line and the ground line VSS is controlled by the switch circuit to meet the storage requirement.

In some possible implementations, n is less than or equal to 32; thus, it is possible to avoid the influence on the potential of the subsequent bit lines due to the excessive number of bit lines located in the previous row, so as to ensure the storage data in each row of transistors for an accurate readout.

In some possible implementation manners, sources and drains of multiple transistors, bit lines, ground lines, and intermediate connection lines between transistors in adjacent rows are distributed on the first metal layer. The m bit lines and ground lines are distributed on the second metal layer. The first metal layer is located between a plurality of transistors arranged in an array of m rows and n columns and the second metal layer. The bit lines and ground lines extend in the row direction. The intermediate connection lines extend along the column direction. The position of the i-th bit line is directly opposite to the position of the transistor in the i-th row.

In some possible implementation manners, the position of the ground line is directly opposite to the position of the transistor in the mth row.

In some possible implementation manners, the ground line is located on a side of the m-th bit line away from the m-1-th bit line.

The embodiment of the present application also provides a method for reading a storage circuit as provided in any one of the aforementioned possible implementation manners, the reading method may include: precharging the 1st, 2nd, ..., x bit lines , and control the x+1, x+2,...,m bit lines to be connected to the ground line; among them, 1≤x≤m, and x is a positive integer; input the start signal to the yth word line to turn on the y column transistors, and read the stored data in the transistors located in the xth row and yth column through the xth row bit line; wherein, 1≤y≤n, and y is a positive integer.

An embodiment of the present application also provides a read-only memory, including a controller and a storage circuit as provided in any one of the foregoing possible implementation manners; the controller is connected to the storage circuit.

An embodiment of the present application further provides an electronic device, including a printed circuit board and a read-only memory provided in any of the foregoing possible implementation manners; the read-only memory is connected to the printed circuit board.

Description of drawings

Fig. 1 is a kind of storage circuit provided in the related art;

FIG. 2 is a schematic diagram of the layout of the storage circuit corresponding to FIG. 1;

FIG. 3 is a storage circuit provided by an embodiment of the present application;

FIG. 4 is a storage circuit provided by an embodiment of the present application;

FIG. 5 is a reading method of a storage circuit provided by an embodiment of the present application;

FIG. 6 is a schematic layout diagram of a memory circuit provided by an embodiment of the present application;

FIG. 7 is a schematic layout diagram of a memory circuit provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly described below in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, and Not all examples. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

The terms "first" and "second" in the description, embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be interpreted as indicating or implying relative importance, nor can they be interpreted as indicating or imply order. Words such as "connected" and "connected" are used to express intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, of a sequence of steps or elements. A method, system, product or device is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to the process, method, product or device. "Up", "Down", "Left", "Right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts, and they are used for description and clarification relative to , which may change accordingly according to changes in the orientation in which components are placed in the drawings.

It should be understood that in this application, "at least one (item)" means one or more, and "multiple" means two or more. "And/or" is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, "A and/or B" can mean: only A exists, only B exists, and A and B exist at the same time , where A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one item (piece) of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c ", where a, b, c can be single or multiple.

An embodiment of the present application provides an electronic device, which includes a printed circuit board (printed circuit board, PCB) and a read-only memory (ROM) connected to the printed circuit board. The present application does not limit the configuration form of the electronic device. For example, the electronic device may be electronic products such as a mobile phone, a tablet computer, a notebook, a vehicle computer, a smart watch, and a smart bracelet.

The above-mentioned read-only memory is provided with a controller and a read-only storage circuit (also referred to simply as a storage circuit) connected to the controller. data to be read out.

Compared with the storage circuit in Figure 1, a dummy storage unit (NMOSd) needs to be set between every two adjacent storage units (NMOS0, NMOS1), and two metal signal lines need to be arranged above the storage unit (Bit line BL, ground line VSS), the storage circuit adopted in the read-only memory that the embodiment of the present application provides, saves the dummy memory cell (equivalent to saving the quantity of 1/3 transistor), and does not need to Each row of memory cells is connected to the ground line VSS (equivalent to saving about 1/2 of the ground line), so that the area of the memory cells can be reduced.

The specific configuration of the read-only memory circuit provided by the embodiment of the present application will be described below.

As shown in FIG. 3 , the embodiment of the present application provides a read-only memory circuit, which includes a transistor array, and in the transistor array, a plurality of transistors arranged in an array in m rows and n columns, that is, the read-only The storage circuit is provided with m*n transistors (that is, storage cells) arranged in a matrix; wherein, the transistor located in the xth row and the yth column is denoted as Nx_y. x, y, m, and n are all positive integers greater than or equal to 1, and 1≤x≤m, 1≤y≤n.

It should be noted that the above-mentioned transistor may be a metal oxide semiconductor field effect transistor (MOSFET), which may be referred to as a MOS transistor for short. The MOS transistor may be an NMOS transistor or a PMOS transistor, which is not limited in this application. In the embodiments of the present application, the transistor used in the read-only memory circuit is an NMOS transistor as an example for illustration.

It should be understood that for the transistor itself, it has a source, a drain, and a gate. Referring to transistor N1_1 in FIG. 3 , the embodiment of the present application does not clearly distinguish the source s and drain d of the transistor, and the source s and drain d can be reversed, that is, the source s and drain d are equivalent Two poles; that is to say, among the two poles (first pole and second pole) of the transistor except the gate, one is the source s and the other is the drain d; for example, the first pole is the source s, Then the second pole is the drain d; the first pole is the drain d, and the second pole is the source s.

In order to clearly describe the connection relationship of each transistor in the read-only memory circuit, the embodiment of the present application defines the source s and the drain d of each transistor according to the relative position in the transistor array, and the embodiment of the present application defines each transistor on the same side as Electrodes are defined as electrodes of the same type (ie source or drain). For example, referring to Fig. 3, it is possible to define the left electrode of each transistor as source s, and the right electrode as drain d; for another example, it is possible to define the left electrode of each transistor as drain d, then the right electrode For the source s. In the following embodiments, the left electrode of each transistor is the source s, and the right electrode is the drain d as an example for schematic illustration.

On this basis, as shown in FIG. 3 , the read-only memory circuit includes m bit lines BL, n word lines WL (word line), ground line VSS, and a switch circuit C on the basis of the aforementioned transistor array. . The m bit lines BL can be respectively expressed as BL1, BL2, . . . , BLm; the n word lines WL can be respectively expressed as WL1, WL2, . . . , WLn.

As shown in Figure 3, in the transistor array, n transistors (ie Nx_1, Nx_2, ..., Nx_n) in the same row are connected in series; N1_1, N1_2), the drain d of the former transistor is electrically connected to the source s of the latter transistor. The m bit lines BL are arranged in one-to-one correspondence with the m rows of transistors. For example, the bit line BL1 is set corresponding to the transistors in the first row in the transistor array, so as to read the stored data in the transistors in the first row through the bit line BL1; the bit line BL2 is set corresponding to the transistors in the second row in the transistor array, so as to pass The bit line BL2 reads the data stored in the transistors of the second row.

It should be noted that all or part of the transistors in the same row are connected to corresponding bit lines, so as to realize reading data stored in each transistor. Regarding the specific connection manner of each transistor, it is related to the actual stored data ("0" or "1") in the transistor, and for details, reference may be made to the relevant description below.

As shown in Figure 3, the n word lines WL are arranged in one-to-one correspondence with the n columns of transistors in the transistor array, and the gates of the m transistors (ie N1_y, N2_y, ..., Nm_y) in the same column are connected to the gates of the same word The transistors in different columns are connected to different word lines. That is, n word lines ( WL1 , WL2 , . . . , WLn) are connected to gates of n columns of transistors in a one-to-one correspondence. For example, the word line WL1 is connected to the gates of the m transistors in the first column, the word line WL2 is connected to the gates of the m transistors in the second column, and so on.

As shown in FIG. 3 , the m bit lines BL are connected to the ground line VSS through the switch circuit C, so as to control the connection between each bit line BL and the ground line VSS through the switch circuit C. Schematically, as shown in FIG. 3, the switch circuit C may include m switches (K1, K2, ..., Km), and the m bit lines BL are respectively connected to the ground line VSS through different switches, so that by controlling each switch , which can realize the on-off between each bit line BL and the ground line VSS.

It should be noted that, in FIG. 3 , it is only schematically illustrated that a switch is provided between each bit line BL and the ground line VSS in the switch circuit C as an example, but the present application is not limited thereto. In some In a possible implementation, in the switch circuit C, a switch may be provided between the corresponding part of the bit line BL and the ground line VSS, for example, no switch may be provided between the first BL1 and the ground line VSS, only for the second A switch is provided between the bit line to the mth bit line and the ground line VSS.

Compared with the need to separately set the ground line VSS for each row of transistors in Figure 1, in the read-only memory circuit provided by the embodiment of the present application, m bit lines BL are connected to the ground line VSS through the switch circuit C on the basis of , in the transistors located in two adjacent rows, by connecting the transistors in the previous row to the transistors in the next row, the bit line corresponding to the transistors in the latter row can be connected to the ground wire, and can be used as the ground wire of the transistors in the previous row, To meet the storage requirements of the previous row of transistors. The connection between the transistors in each row, the bit line and the ground line in the read-only memory circuit of the present application will be described in detail below.

As shown in FIG. 3, among the transistors in the first row to the m-1th row (and that is, except the last row of transistors), the source s of any row (i-th row) transistor can be connected to the transistor corresponding to the row The bit line (BLi) can also be connected to the source s of the transistor in the same column in the next row (row i+1); wherein, 1≤i≤m-1, and i is a positive integer.

Similarly, the drain d of the transistor in the i-th row can be connected to the i-th bit line BLi, or can be connected to the drain d of the transistor in the same column in the i+1-th row.

That is to say, for any transistor Nx_y in the transistor array, there may be four connection modes.

In the first connection mode, both the source s and the drain d of the transistor Nx_y are connected to the corresponding bit line BLx.

In the second connection mode, the source s and the drain d of the transistor Nx_y are respectively connected to the source s and the drain d of the transistor N(x+1_y) located in the next row and the same column.

In the third connection mode, the source s of the transistor Nx_y is connected to the corresponding bit line BLx, and the drain d of the transistor Nx_y is connected to the drain d of the transistor N(x+1_y) in the next row and the same column.

In the fourth connection mode, the source s of the transistor Nx_y is connected to the source s of the transistor N(x+1_y) in the next row and the same column, and the drain d of the transistor Nx_y is connected to the corresponding bit line BLx.

It can be understood that in the transistor array, the specific connection mode of the source s and the drain d of the transistor directly determines the stored data ("0" or "1") in the transistor, so it can be stored according to the actual storage requirements. , to set the connection mode of the source s and the drain d of the transistor, so as to ensure that each transistor can satisfy the storage of "0" or "1".

Schematically, in the actual circuit design, the connection mode of the source s (or drain d) of the transistor can be fixed, and the drain d (or drain d) of the transistor can be set according to the storage requirement ("0" or "1") source s) connection.

For example, in some possible implementations, as shown in FIG. 3 , it is possible to design the start terminals of multiple transistors arranged in series in m rows to be connected to the bit line corresponding to the row; that is, the first column transistor (ie Nx_1) The source s of the row is connected to the bit line BLx corresponding to the row. In this case, the connection mode of the drain of the transistor in the first column is set according to the storage requirement of the transistor in the first column (ie, Nx_1), and the connection mode of the drain of the transistor in the first column (ie, Nx_1) is set. The connection mode of the drains of the 2 columns of transistors (ie Nx_2) is to meet the requirement of the second transistor for storing data, and so on, and the connection mode of the drains of the subsequent transistors can be designed sequentially from left to right.

Similarly, in some other possible implementations, it is possible to design the ends of multiple transistors arranged in series in m rows to be connected to the bit line corresponding to the row; that is, the drain of the transistor in the nth column (ie, Nx_n) is connected to On the bit line BLx corresponding to the row. In this case, set the connection mode of the source of the transistor in the nth column according to the storage requirement of the transistor in the nth column, and set the connection mode of the source of the previous transistor according to the connection mode of the drain of the transistor in the nth column , to meet the requirement of the previous transistor for storing data, and so on, the connection mode of the source of the subsequent transistor can be designed in turn from right to left.

Referring to the transistor array of 4 rows and 3 columns in FIG. 4 , the data storage of the read-only memory circuit will be described in combination with the connection manner of the source and drain of the specific transistors. In Fig. 4, the source s of the transistor in the first column (that is, Nx_1) is connected to the bit line BLx corresponding to the row as an example. The switch circuit C is not shown in Fig. 4, and the connection of the switch circuit C can refer to Fig. 3.

Take the transistor N1_1 (also called the first transistor) and the transistor N1_2 (also called the second transistor) located in the same column and located in two adjacent rows in FIG. 4 as an example. Transistor N1_1 stores "0". . Wherein, the first transistor and the second transistor do not refer to specific two transistors, and the first transistor and the second transistor may be any two transistors located in the same column and respectively located in two adjacent rows in the transistor array.

For the transistor N1_1 , the source of the transistor N1_1 (ie node r1c1 ) is fixedly connected to the bit line BL1 . As shown in FIG. 4, the drain of transistor N1_1 (that is, node r1c2) can be connected to the drain of transistor N2_1 (that is, node r2c2), so that when transistor N1_1 and transistor N2_1 are turned on through word line WL2, node r1c2 Equipotential with the bit line BL2, through the switch circuit C to control the connection between the bit line BL2 and the ground line VSS, so that the high potential stored on the bit line BL1 can be pulled down to a low potential (for the specific control method, please refer to the relevant content below), and then can Realize the reading of "0" signal.

Of course, in the case that the source of transistor N1_1 (ie node r1c1) is fixedly connected to bit line BL1, if it is necessary to store “1” in transistor N1_1, the drain of transistor N1_1 (ie node r1c2) can also be connected to bit line BL1 In this way, when the transistor N1_1 is turned on through the word line WL1, the high potential stored on the bit line BL1 will not change, so that the reading of the "1" signal can be realized.

Taking the transistor N1_2 (also called the third transistor) and the transistor N2_2 (also called the fourth transistor) located in the same column and located in two adjacent rows respectively, “1” is stored in the transistor N1_2 as an example. Wherein, the third transistor and the fourth transistor do not refer to two specific transistors, and the third transistor and the fourth transistor may be any two transistors located in the same column and respectively located in two adjacent rows in the transistor array.

For the transistor N1_2, the source of the transistor N1_2 (ie, the node r1c1) is fixedly connected to the node r2c2. As shown in Figure 4, the drain of transistor N1_2 (ie, node r1c3) can be connected to the drain of transistor N2_2 (ie, node r2c3), in which case neither the source nor the drain of transistor N1_2 is connected to the bit line BL1 In this way, when the transistor N1_2 and the transistor N2_2 are turned on through the word line WL2, the high potential stored on the bit line BL1 will not change, so that the reading of the "1" signal can be realized.

Of course, in the case that the source of transistor N1_2 (ie, node r1c1) is fixedly connected to node r2c2, if it is necessary to store "1" in transistor N1_2, the drain of transistor N1_2 (ie, node r1c3) can be connected to bit line BL1, In this way, when the transistor N1_2 and the transistor N2_2 are turned on through the word line WL2, the node r1c2 is at the same potential as the bit line BL2, and the switch circuit C can control the connection between the bit line BL2 and the ground line VSS, so that the data stored on the bit line BL1 can be The high potential is pulled down to the low potential, and then the reading of "0" signal can be realized.

Taking the transistor N2_3 as an example, the source of the transistor N2_3 (ie node r2c3) is fixedly connected to the bit line BL2.

If it is necessary to store "1" in the transistor N2_3, as shown in FIG. 4, the drain of the transistor N2_3 (that is, the node r2c4) can also be connected to the bit line BL2, so that when the transistor N2_3 is turned on through the word line WL3, the bit The stored high potential on the line BL2 does not change, so that a "1" signal can be read.

Of course, if it is necessary to store "0" in the transistor N2_3, the drain of the transistor N2_3 (that is, the node r2c4) can be connected to the drain of the transistor N3_3 (that is, the node r3c4), so that the transistor N2_3 is turned on through the word line WL3 When connecting with the transistor N3_3, the node r2c4 has the same potential as the bit line BL3, and the switch circuit C controls the bit line BL3 to be connected to the ground line VSS, so that the high potential stored on the bit line BL2 can be pulled down to a low potential, and then "0" can be realized signal reading.

In summary, compared with the read-only memory circuit in the related art, dummy memory cells need to be arranged between adjacent memory cells, and two metal signal lines (bit lines, ground lines) need to be arranged above the memory cells and In other words, in the read-only storage circuit provided by the embodiment of the present application, each transistor is used as a storage unit for data storage, and there is no need to set up a dummy storage unit, which avoids the waste of storage area caused by the dummy storage unit; and by arranging two adjacent rows of transistors The connection between the transistors in the next row can be connected to the ground wire corresponding to the bit line and used as the ground wire of the previous row of transistors to realize the storage requirement; it is equivalent to saving about half (50%) of the ground wire, which can further reduce the The area of the storage unit is small, and the density of the transistor array constrained by metal lines can be increased.

In addition, for the last row of transistors, there is no next row of transistors, so in order to meet the storage requirements of the last row of transistors, the last row of transistors can be directly connected to the ground to meet the storage requirements.

Schematically, as shown in FIG. 3 , for a plurality of transistors (also referred to as fifth transistors) in the last row (row m), the source s of the transistors in the row (row m) can be connected to the The bit line (BLm; also referred to as the fifth bit line) corresponding to the transistor can also be connected to the ground line VSS. Similarly, the drains d of the transistors in this row (that is, the mth row) can be connected to the bit line (BLm) corresponding to the transistors in this row, and can also be connected to the ground line VSS.

The reading method of the read-only memory circuit provided by the embodiment of the present application is schematically described below.

Referring to FIG. 3, take the example of reading the stored data in the transistor Nx_y (that is, any transistor) in row x and column y in the read-only memory circuit. As shown in FIG. 5, the reading method may include :

Step 01. Precharge the 1st, 2nd, ..., xth bit lines (precharge), and control the x+1, x+2, ..., mth bitlines BL to communicate with the ground line VSS.

Step 02: Input a turn-on signal to the yth word line WLy to turn on the transistor in the yth column, and read the stored data in the transistor Nx_y in the xth row and the yth column through the xth row bit line BLx.

Schematically, taking reading the stored data (“0”) in transistor N1_1 in FIG. 4 as an example, the bit line BL1 is precharged through step 01, that is, a high-level potential is input to the bit line BL1; and other The bit lines BL2, BL3, BL4 are connected to the ground line VSS. Then, through step 02, input a turn-on signal to the word line WL1 to turn on the transistor in the first column. In this case, the drain of the transistor N1_1 (that is, the node r1c2) is at the same potential as the bit line BL2 (that is, grounded), thereby inputting the bit line BL1 The high level potential of is pulled down to low potential; at this time, the stored data "0" in the transistor N1_1 is read from the bit line BL1.

Schematically, taking reading the stored data ("1") in transistor N2_3 in FIG. ; and the other bit lines BL3, BL4 are connected to the ground line VSS. Then input the turn-on signal to the word line WL3 through step 02 to turn on the transistor in the third column. In this case, the high potential on the bit line BL2 does not change; at this time, the stored data in the transistor N2_3 is read from the bit line BL2 "1".

Schematically, taking reading the stored data (“0”) in transistor N3_1 in FIG. high level potential; and connect the other bit line BL4 with the ground line VSS. Then, through step 02, input a turn-on signal to the word line WL1 to turn on the transistor in the first column. In this case, the drain of the transistor N3_1 (ie node r3c2) is at the same potential as the bit line BL4 (ie, grounded), thereby inputting the bit line BL3 The high level potential of is pulled down to low potential; at this time, the stored data "0" in the transistor N3_1 is read from the bit line BL3.

Schematically, taking reading the stored data ("0") in transistor N4_1 in FIG. BL3, BL4 input high level potential. Then input the turn-on signal to the word line WL1 through step 02 to turn on the first row of transistors, since the drain of the transistor N4_1 (namely node r4c2) is connected to the ground line VSS, the high-level potential input by the bit line BL4 is pulled down to a low potential ; At this time, the stored data "0" in the transistor N4_1 is read from the bit line BL4.

It should be understood here that since the ground line VSS is separately set for the last row of transistors in the storage circuit, when reading the stored data in the last row of transistors, only all the bit lines BL1, BL2, BL3 and BL4 can be precharged, and there is no need to connect the control bit line to the ground line VSS.

It should be noted that, since there is an electrical connection relationship between transistors in adjacent rows in the read-only memory circuit provided by the embodiment of the present application, when reading stored data from a transistor located in a certain row (row x), While precharging the bit line BLx corresponding to the transistor in row x, it is necessary to simultaneously precharge all the bit lines BL1, BL2,..., BL(x-1) located in front of the bit line BLx, so as to reduce the BL1 , BL2 , . . . , BL(x−1) affect the voltage on the bit line BLx (such as voltage fluctuation), which leads to the problem that the stored data cannot be accurately read.

In addition, in order to ensure that the stored data in each row of transistors can be accurately read out, and to avoid the potential impact on the potential of the subsequent bit lines due to the excessive number of bit lines located in the previous row, in some possible implementation methods, The number of rows in the transistor array can be set to be less than or equal to 32, ie n≤32. Schematically, n can be equal to 4, 8, 16 and so on.

The layer-to-layer distribution of the read-only memory circuit in the read-only memory will be further described below in conjunction with the layout arrangement of the above-mentioned read-only memory circuit. It should be understood here that the layout layout of the circuit is consistent with the actual distribution of devices, signal lines, etc. in the product.

As shown in Figure 6, taking a transistor array with 4 rows and 5 columns as an example for the storage circuit, when designing the layout layout of the read-only memory circuit, the source and drain of the transistor array can be set to connect with the bit line BL and the ground The line VSS and the intermediate connection line ML between transistors in adjacent rows are located on the first metal layer M1; the m bit lines BL and the ground line VSS are located on the second metal layer M1; the transistor array is distributed on the first metal layer M1 away from the second One side of the metal layer M1, that is, the first metal layer M1 is located between the transistor array and the second metal layer M2.

It should be understood here that the transistor array includes a plurality of film layer structures; for example, as shown in FIG. wait.

Referring to FIG. 6, the bit line BL and the ground line VSS located in the second metal layer M2 may extend along the row direction. That is, the i-th bit line is set at a position directly opposite to the i-th row of transistors.

For the setting of the ground line VSS, as shown in Figure 6, in some possible implementations, the ground line VSS can be set outside the last row (that is, the fourth row) of transistors, that is, the ground line VSS is set on the bit line BL4 is away from the side of the transistor array (or BL3). As shown in FIG. 7 , in some possible implementation manners, both the ground line VSS and the bit line BL4 (the last bit line) can be set at positions opposite to the transistors in the fourth row (the last row of transistors).

In addition, as shown in FIG. 6 or FIG. 7 , the middle connection line ML located on the first metal layer M1 may extend in the opposite direction along the column. In addition, the middle connection line ML can be electrically connected to the bit line BL and the ground line VSS through the via hole VIA. It should be noted that the aforementioned storage circuit is an equivalent circuit diagram, and some electrical connections in the storage circuit can be designed as equivalent connections during fabrication. For example, the drains of all transistors in the fourth column in FIG. The middle connection line ML is directly connected to the ground line VSS, and this connection mode is equivalent to that of sequentially connecting the drains of the four transistors in the fourth column to the ground line in the storage circuit.

In addition, in the ROM, one aforementioned read-only storage circuit can be set, and multiple aforementioned read-only storage circuits can also be set.

It should be noted that the “opposite” involved in the above-mentioned embodiments does not refer to the absolute center-to-centre opposition. Taking the aforementioned position where the ground line VSS and the bit line BL4 are located opposite to the transistors in the fourth row as an example, it refers to the ground line VSS and bit line BL4 can be considered as the projection of the ground line VSS and bit line BL4 on the substrate, which has an overlapping area with the projection of the transistors in the fourth row; of course, in practice, it can be specified by setting The size of the overlapping area to ensure the minimum area of the memory cell.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A read-only memory circuit, characterized in that it includes a transistor array, a switch circuit, a plurality of word lines, a plurality of bit lines, and a ground wire;

The transistor array includes a plurality of transistors; wherein, in the transistor array: the plurality of transistors located in the same row are connected in series in sequence, and the gates of the plurality of transistors located in the same column are connected to the same word line, The plurality of bit lines are arranged in one-to-one correspondence with the transistors in different rows;

The plurality of bit lines are connected to the ground line through the switch circuit;

The transistor array includes: a first transistor and a second transistor located in the same column and respectively located in two adjacent rows;

The multiple bit lines include a first bit line and a second bit line; the first bit line corresponds to the plurality of transistors in the row where the first transistor is located, and the second bit line corresponds to the first bit line The multiple transistors in the row where the second transistor is located correspond to;

The first pole of the first transistor is connected to the first bit line, the second pole of the first transistor is connected to the second pole of the second transistor, the first pole of the second transistor is connected to the The second bit line connection described above.
The read-only memory circuit according to claim 1, wherein,

The transistor array further includes: a third transistor and a fourth transistor located in the same column and respectively located in two adjacent rows;

The multiple bit lines include a third bit line and a fourth bit line; the third bit line corresponds to the plurality of transistors in the row where the third transistor is located, and the fourth bit line corresponds to the first bit line The multiple transistors in the row where the four transistors are located correspond to;

The first pole of the third transistor is connected to the first pole of the fourth transistor, and the second pole of the third transistor is connected to the second pole of the fourth transistor.
The read-only memory circuit according to claim 1 or 2, characterized in that,

The plurality of bit lines include a fifth bit line, and the fifth bit line corresponds to the last row of transistors in the transistor array;

The last row of transistors includes a fifth transistor;

The first pole of the fifth transistor is connected to the fifth bit line or the ground line;

The second pole of the fifth transistor is connected to the fifth bit line or the ground line.
The read-only memory circuit according to any one of claims 1-3, characterized in that,

The start terminals or ends of the plurality of transistors arranged in series in each row of the transistor array are connected to the corresponding bit lines.
The read-only memory circuit according to any one of claims 1-4, characterized in that,

The transistor array includes n rows of transistors, wherein n is less than or equal to 32.
The read-only memory circuit according to any one of claims 1-5, characterized in that,

The transistor, the bit line, the ground line, and the intermediate connection lines between the transistors in adjacent rows are distributed on the first metal layer;

The plurality of bit lines and the ground line are distributed on the second metal layer;

The first metal layer is located between the plurality of transistors and the second metal layer;

The bit line and the ground line extend along a row direction of the transistor array;

The intermediate connection line extends along the column direction of the transistor array;

The positions of the plurality of bit lines are respectively opposite to the positions of the transistors in each row.
The read-only memory circuit according to claim 6, wherein,

The position of the ground line is directly opposite to the position of the last row of transistors in the transistor array.
The read-only memory circuit according to claim 6, wherein,

The bit line corresponding to the last row of transistors in the transistor array is the fifth bit line;

The ground line is located on a side of the fifth bit line away from the transistor array.
A read-only memory, characterized by comprising a controller and the read-only storage circuit according to any one of claims 1-8; the controller is connected to the read-only storage circuit.
An electronic device, characterized by comprising a printed circuit board and a read-only memory according to claim 9; the read-only memory is connected to the printed circuit board.